[deliverable/linux.git] / arch / arm / boot / dts / sun7i-a20.dtsi

/*
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};
	};

	memory {
		reg = <0x40000000 0x80000000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: osc24M@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-osc-clk";
			reg = <0x01c20050 0x4>;
			clock-frequency = <24000000>;
		};

		osc32k: osc32k {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		pll1: pll1@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
		};

		/*
		 * This is a dummy clock, to be used as placeholder on
		 * other mux clocks when a specific parent clock is not
		 * yet implemented. It should be dropped when the driver
		 * is complete.
		 */
		pll6: pll6 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		cpu: cpu@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-cpu-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
		};

		axi: axi@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-axi-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&cpu>;
		};

		ahb: ahb@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&axi>;
		};

		ahb_gates: ahb_gates@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-ahb-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb>;
			clock-output-names = "ahb_usb0", "ahb_ehci0",
				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
				"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
				"ahb_nand", "ahb_sdram", "ahb_ace",
				"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
				"ahb_spi2", "ahb_spi3", "ahb_sata",
				"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
				"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
				"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
				"ahb_de_fe1", "ahb_gmac", "ahb_mp",
				"ahb_mali";
		};

		apb0: apb0@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb>;
		};

		apb0_gates: apb0_gates@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-apb0-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb0>;
			clock-output-names = "apb0_codec", "apb0_spdif",
				"apb0_ac97", "apb0_iis0", "apb0_iis1",
				"apb0_pio", "apb0_ir0", "apb0_ir1",
				"apb0_iis2", "apb0_keypad";
		};

		apb1_mux: apb1_mux@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-mux-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc24M>, <&pll6>, <&osc32k>;
		};

		apb1: apb1@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&apb1_mux>;
		};

		apb1_gates: apb1_gates@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-apb1-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_i2c0", "apb1_i2c1",
				"apb1_i2c2", "apb1_i2c3", "apb1_can",
				"apb1_scr", "apb1_ps20", "apb1_ps21",
				"apb1_i2c4", "apb1_uart0", "apb1_uart1",
				"apb1_uart2", "apb1_uart3", "apb1_uart4",
				"apb1_uart5", "apb1_uart6", "apb1_uart7";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		emac: ethernet@01c0b000 {
			compatible = "allwinner,sun4i-emac";
			reg = <0x01c0b000 0x1000>;
			interrupts = <0 55 1>;
			clocks = <&ahb_gates 17>;
			status = "disabled";
		};

		mdio@01c0b080 {
			compatible = "allwinner,sun4i-mdio";
			reg = <0x01c0b080 0x14>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun7i-a20-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <0 28 1>;
			clocks = <&apb0_gates 5>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PB22", "PB23";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart6_pins_a: uart6@0 {
				allwinner,pins = "PI12", "PI13";
				allwinner,function = "uart6";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart7_pins_a: uart7@0 {
				allwinner,pins = "PI20", "PI21";
				allwinner,function = "uart7";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-timer";
			reg = <0x01c20c00 0x90>;
			interrupts = <0 22 1>,
				     <0 23 1>,
				     <0 24 1>,
				     <0 25 1>,
				     <0 67 1>,
				     <0 68 1>;
			clocks = <&osc24M>;
		};

		wdt: watchdog@01c20c90 {
			compatible = "allwinner,sun4i-wdt";
			reg = <0x01c20c90 0x10>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <0 1 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 16>;
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <0 2 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 17>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <0 3 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 18>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <0 4 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 19>;
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <0 17 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 20>;
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
			interrupts = <0 18 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 21>;
			status = "disabled";
		};

		uart6: serial@01c29800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29800 0x400>;
			interrupts = <0 19 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 22>;
			status = "disabled";
		};

		uart7: serial@01c29c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29c00 0x400>;
			interrupts = <0 20 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 23>;
			status = "disabled";
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 0xf04>;
		};
	};
};
Commit	Line	Data
4790ecfa MR	1	/*
	2	* Copyright 2013 Maxime Ripard
	3	*
	4	* Maxime Ripard <maxime.ripard@free-electrons.com>
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
	14	/include/ "skeleton.dtsi"
	15
	16	/ {
	17	interrupt-parent = <&gic>;
	18
	19	cpus {
	20	#address-cells = <1>;
	21	#size-cells = <0>;
	22
	23	cpu@0 {
	24	compatible = "arm,cortex-a7";
	25	device_type = "cpu";
	26	reg = <0>;
	27	};
	28
	29	cpu@1 {
	30	compatible = "arm,cortex-a7";
	31	device_type = "cpu";
	32	reg = <1>;
	33	};
	34	};
	35
	36	memory {
	37	reg = <0x40000000 0x80000000>;
	38	};
	39
	40	clocks {
	41	#address-cells = <1>;
	42	#size-cells = <1>;
	43	ranges;
	44
	45	osc24M: osc24M@01c20050 {
	46	#clock-cells = <0>;
de7dc935 MR	47	compatible = "allwinner,sun4i-osc-clk";
de7dc935 MR	48	reg = <0x01c20050 0x4>;
4790ecfa MR	49	clock-frequency = <24000000>;
	50	};
	51
	52	osc32k: osc32k {
	53	#clock-cells = <0>;
	54	compatible = "fixed-clock";
	55	clock-frequency = <32768>;
	56	};
de7dc935 MR	57
	58	pll1: pll1@01c20000 {
	59	#clock-cells = <0>;
	60	compatible = "allwinner,sun4i-pll1-clk";
	61	reg = <0x01c20000 0x4>;
	62	clocks = <&osc24M>;
	63	};
	64
	65	/*
	66	* This is a dummy clock, to be used as placeholder on
	67	* other mux clocks when a specific parent clock is not
	68	* yet implemented. It should be dropped when the driver
	69	* is complete.
	70	*/
	71	pll6: pll6 {
	72	#clock-cells = <0>;
	73	compatible = "fixed-clock";
	74	clock-frequency = <0>;
	75	};
	76
	77	cpu: cpu@01c20054 {
	78	#clock-cells = <0>;
	79	compatible = "allwinner,sun4i-cpu-clk";
	80	reg = <0x01c20054 0x4>;
	81	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
	82	};
	83
	84	axi: axi@01c20054 {
	85	#clock-cells = <0>;
	86	compatible = "allwinner,sun4i-axi-clk";
	87	reg = <0x01c20054 0x4>;
	88	clocks = <&cpu>;
	89	};
	90
	91	ahb: ahb@01c20054 {
	92	#clock-cells = <0>;
	93	compatible = "allwinner,sun4i-ahb-clk";
	94	reg = <0x01c20054 0x4>;
	95	clocks = <&axi>;
	96	};
	97
	98	ahb_gates: ahb_gates@01c20060 {
	99	#clock-cells = <1>;
	100	compatible = "allwinner,sun7i-a20-ahb-gates-clk";
	101	reg = <0x01c20060 0x8>;
	102	clocks = <&ahb>;
	103	clock-output-names = "ahb_usb0", "ahb_ehci0",
	104	"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
	105	"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
	106	"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
	107	"ahb_nand", "ahb_sdram", "ahb_ace",
	108	"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
	109	"ahb_spi2", "ahb_spi3", "ahb_sata",
	110	"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
	111	"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
	112	"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
	113	"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
	114	"ahb_de_fe1", "ahb_gmac", "ahb_mp",
	115	"ahb_mali";
	116	};
	117
	118	apb0: apb0@01c20054 {
	119	#clock-cells = <0>;
	120	compatible = "allwinner,sun4i-apb0-clk";
121	reg = <0x01c20054 0x4>;
122	clocks = <&ahb>;
123	};
124
125	apb0_gates: apb0_gates@01c20068 {
126	#clock-cells = <1>;
127	compatible = "allwinner,sun7i-a20-apb0-gates-clk";
128	reg = <0x01c20068 0x4>;
129	clocks = <&apb0>;
130	clock-output-names = "apb0_codec", "apb0_spdif",
131	"apb0_ac97", "apb0_iis0", "apb0_iis1",
132	"apb0_pio", "apb0_ir0", "apb0_ir1",
133	"apb0_iis2", "apb0_keypad";
134	};
135
136	apb1_mux: apb1_mux@01c20058 {
137	#clock-cells = <0>;
138	compatible = "allwinner,sun4i-apb1-mux-clk";
139	reg = <0x01c20058 0x4>;
140	clocks = <&osc24M>, <&pll6>, <&osc32k>;
141	};
142
143	apb1: apb1@01c20058 {
144	#clock-cells = <0>;
145	compatible = "allwinner,sun4i-apb1-clk";
146	reg = <0x01c20058 0x4>;
147	clocks = <&apb1_mux>;
148	};
149
150	apb1_gates: apb1_gates@01c2006c {
151	#clock-cells = <1>;
152	compatible = "allwinner,sun7i-a20-apb1-gates-clk";
153	reg = <0x01c2006c 0x4>;
154	clocks = <&apb1>;
155	clock-output-names = "apb1_i2c0", "apb1_i2c1",
156	"apb1_i2c2", "apb1_i2c3", "apb1_can",
157	"apb1_scr", "apb1_ps20", "apb1_ps21",
158	"apb1_i2c4", "apb1_uart0", "apb1_uart1",
159	"apb1_uart2", "apb1_uart3", "apb1_uart4",
160	"apb1_uart5", "apb1_uart6", "apb1_uart7";
161	};
4790ecfa MR	162	};
	163
	164	soc@01c00000 {
	165	compatible = "simple-bus";
	166	#address-cells = <1>;
	167	#size-cells = <1>;
	168	ranges;
	169
2e804d03 MR	170	emac: ethernet@01c0b000 {
	171	compatible = "allwinner,sun4i-emac";
	172	reg = <0x01c0b000 0x1000>;
	173	interrupts = <0 55 1>;
	174	clocks = <&ahb_gates 17>;
	175	status = "disabled";
	176	};
	177
	178	mdio@01c0b080 {
	179	compatible = "allwinner,sun4i-mdio";
	180	reg = <0x01c0b080 0x14>;
	181	status = "disabled";
	182	#address-cells = <1>;
	183	#size-cells = <0>;
	184	};
	185
17eac031 MR	186	pio: pinctrl@01c20800 {
	187	compatible = "allwinner,sun7i-a20-pinctrl";
	188	reg = <0x01c20800 0x400>;
	189	interrupts = <0 28 1>;
de7dc935	190	clocks = <&apb0_gates 5>;
17eac031 MR	191	gpio-controller;
	192	interrupt-controller;
	193	#address-cells = <1>;
	194	#size-cells = <0>;
	195	#gpio-cells = <3>;
9f229ba9 MR	196
	197	uart0_pins_a: uart0@0 {
	198	allwinner,pins = "PB22", "PB23";
	199	allwinner,function = "uart0";
	200	allwinner,drive = <0>;
	201	allwinner,pull = <0>;
	202	};
	203
	204	uart6_pins_a: uart6@0 {
	205	allwinner,pins = "PI12", "PI13";
	206	allwinner,function = "uart6";
	207	allwinner,drive = <0>;
	208	allwinner,pull = <0>;
	209	};
	210
	211	uart7_pins_a: uart7@0 {
	212	allwinner,pins = "PI20", "PI21";
	213	allwinner,function = "uart7";
	214	allwinner,drive = <0>;
	215	allwinner,pull = <0>;
	216	};
17eac031 MR	217	};
17eac031 MR	218
4790ecfa MR	219	timer@01c20c00 {
	220	compatible = "allwinner,sun4i-timer";
	221	reg = <0x01c20c00 0x90>;
	222	interrupts = <0 22 1>,
	223	<0 23 1>,
	224	<0 24 1>,
	225	<0 25 1>,
	226	<0 67 1>,
	227	<0 68 1>;
	228	clocks = <&osc24M>;
	229	};
	230
	231	wdt: watchdog@01c20c90 {
	232	compatible = "allwinner,sun4i-wdt";
	233	reg = <0x01c20c90 0x10>;
	234	};
	235
	236	uart0: serial@01c28000 {
	237	compatible = "snps,dw-apb-uart";
	238	reg = <0x01c28000 0x400>;
	239	interrupts = <0 1 1>;
	240	reg-shift = <2>;
	241	reg-io-width = <4>;
de7dc935	242	clocks = <&apb1_gates 16>;
4790ecfa MR	243	status = "disabled";
	244	};
	245
	246	uart1: serial@01c28400 {
	247	compatible = "snps,dw-apb-uart";
	248	reg = <0x01c28400 0x400>;
	249	interrupts = <0 2 1>;
	250	reg-shift = <2>;
	251	reg-io-width = <4>;
de7dc935	252	clocks = <&apb1_gates 17>;
4790ecfa MR	253	status = "disabled";
	254	};
	255
	256	uart2: serial@01c28800 {
	257	compatible = "snps,dw-apb-uart";
	258	reg = <0x01c28800 0x400>;
	259	interrupts = <0 3 1>;
	260	reg-shift = <2>;
	261	reg-io-width = <4>;
de7dc935	262	clocks = <&apb1_gates 18>;
4790ecfa MR	263	status = "disabled";
	264	};
	265
	266	uart3: serial@01c28c00 {
	267	compatible = "snps,dw-apb-uart";
	268	reg = <0x01c28c00 0x400>;
	269	interrupts = <0 4 1>;
	270	reg-shift = <2>;
	271	reg-io-width = <4>;
de7dc935	272	clocks = <&apb1_gates 19>;
4790ecfa MR	273	status = "disabled";
	274	};
	275
	276	uart4: serial@01c29000 {
	277	compatible = "snps,dw-apb-uart";
	278	reg = <0x01c29000 0x400>;
	279	interrupts = <0 17 1>;
	280	reg-shift = <2>;
	281	reg-io-width = <4>;
de7dc935	282	clocks = <&apb1_gates 20>;
4790ecfa MR	283	status = "disabled";
	284	};
	285
	286	uart5: serial@01c29400 {
	287	compatible = "snps,dw-apb-uart";
	288	reg = <0x01c29400 0x400>;
	289	interrupts = <0 18 1>;
	290	reg-shift = <2>;
	291	reg-io-width = <4>;
de7dc935	292	clocks = <&apb1_gates 21>;
4790ecfa MR	293	status = "disabled";
	294	};
	295
	296	uart6: serial@01c29800 {
	297	compatible = "snps,dw-apb-uart";
	298	reg = <0x01c29800 0x400>;
	299	interrupts = <0 19 1>;
	300	reg-shift = <2>;
	301	reg-io-width = <4>;
de7dc935	302	clocks = <&apb1_gates 22>;
4790ecfa MR	303	status = "disabled";
	304	};
	305
	306	uart7: serial@01c29c00 {
	307	compatible = "snps,dw-apb-uart";
	308	reg = <0x01c29c00 0x400>;
	309	interrupts = <0 20 1>;
	310	reg-shift = <2>;
	311	reg-io-width = <4>;
de7dc935	312	clocks = <&apb1_gates 23>;
4790ecfa MR	313	status = "disabled";
	314	};
	315
	316	gic: interrupt-controller@01c81000 {
	317	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
	318	reg = <0x01c81000 0x1000>,
	319	<0x01c82000 0x1000>,
	320	<0x01c84000 0x2000>,
	321	<0x01c86000 0x2000>;
	322	interrupt-controller;
	323	#interrupt-cells = <3>;
	324	interrupts = <1 9 0xf04>;
	325	};
	326	};
	327	};