[deliverable/linux.git] / arch / arm / boot / dts / sun7i-a20.dtsi

/*
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	interrupt-parent = <&gic>;

	aliases {
		ethernet0 = &gmac;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		serial6 = &uart6;
		serial7 = &uart7;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};
	};

	memory {
		reg = <0x40000000 0x80000000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: clk@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-osc-clk";
			reg = <0x01c20050 0x4>;
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: clk@0 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};

		pll1: clk@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll1";
		};

		pll4: clk@01c20018 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-pll1-clk";
			reg = <0x01c20018 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll4";
		};

		pll5: clk@01c20020 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-pll5-clk";
			reg = <0x01c20020 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll5_ddr", "pll5_other";
		};

		pll6: clk@01c20028 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-pll6-clk";
			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll6_sata", "pll6_other", "pll6";
		};

		cpu: cpu@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-cpu-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
			clock-output-names = "cpu";
		};

		axi: axi@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-axi-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&cpu>;
			clock-output-names = "axi";
		};

		ahb: ahb@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&axi>;
			clock-output-names = "ahb";
		};

		ahb_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-ahb-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb>;
			clock-output-names = "ahb_usb0", "ahb_ehci0",
				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
				"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
				"ahb_nand", "ahb_sdram", "ahb_ace",
				"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
				"ahb_spi2", "ahb_spi3", "ahb_sata",
				"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
				"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
				"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
				"ahb_de_fe1", "ahb_gmac", "ahb_mp",
				"ahb_mali";
		};

		apb0: apb0@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb>;
			clock-output-names = "apb0";
		};

		apb0_gates: clk@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-apb0-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb0>;
			clock-output-names = "apb0_codec", "apb0_spdif",
				"apb0_ac97", "apb0_iis0", "apb0_iis1",
				"apb0_pio", "apb0_ir0", "apb0_ir1",
				"apb0_iis2", "apb0_keypad";
		};

		apb1_mux: apb1_mux@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-mux-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
			clock-output-names = "apb1_mux";
		};

		apb1: apb1@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&apb1_mux>;
			clock-output-names = "apb1";
		};

		apb1_gates: clk@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-apb1-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_i2c0", "apb1_i2c1",
				"apb1_i2c2", "apb1_i2c3", "apb1_can",
				"apb1_scr", "apb1_ps20", "apb1_ps21",
				"apb1_i2c4", "apb1_uart0", "apb1_uart1",
				"apb1_uart2", "apb1_uart3", "apb1_uart4",
				"apb1_uart5", "apb1_uart6", "apb1_uart7";
		};

		nand_clk: clk@01c20080 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20080 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "nand";
		};

		ms_clk: clk@01c20084 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20084 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ms";
		};

		mmc0_clk: clk@01c20088 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20088 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc0";
		};

		mmc1_clk: clk@01c2008c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c2008c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc1";
		};

		mmc2_clk: clk@01c20090 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20090 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc2";
		};

		mmc3_clk: clk@01c20094 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20094 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc3";
		};

		ts_clk: clk@01c20098 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c20098 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ts";
		};

		ss_clk: clk@01c2009c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c2009c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ss";
		};

		spi0_clk: clk@01c200a0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200a0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi0";
		};

		spi1_clk: clk@01c200a4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200a4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi1";
		};

		spi2_clk: clk@01c200a8 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200a8 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi2";
		};

		pata_clk: clk@01c200ac {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200ac 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "pata";
		};

		ir0_clk: clk@01c200b0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200b0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir0";
		};

		ir1_clk: clk@01c200b4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200b4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir1";
		};

		spi3_clk: clk@01c200d4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c200d4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi3";
		};

		mbus_clk: clk@01c2015c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			reg = <0x01c2015c 0x4>;
			clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
			clock-output-names = "mbus";
		};

		/*
		 * The following two are dummy clocks, placeholders used in the gmac_tx
		 * clock. The gmac driver will choose one parent depending on the PHY
		 * interface mode, using clk_set_rate auto-reparenting.
		 * The actual TX clock rate is not controlled by the gmac_tx clock.
		 */
		mii_phy_tx_clk: clk@2 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25000000>;
			clock-output-names = "mii_phy_tx";
		};

		gmac_int_tx_clk: clk@3 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <125000000>;
			clock-output-names = "gmac_int_tx";
		};

		gmac_tx_clk: clk@01c20164 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-gmac-clk";
			reg = <0x01c20164 0x4>;
			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
			clock-output-names = "gmac_tx";
		};

		/*
		 * Dummy clock used by output clocks
		 */
		osc24M_32k: clk@1 {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <750>;
			clock-mult = <1>;
			clocks = <&osc24M>;
			clock-output-names = "osc24M_32k";
		};

		clk_out_a: clk@01c201f0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-out-clk";
			reg = <0x01c201f0 0x4>;
			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
			clock-output-names = "clk_out_a";
		};

		clk_out_b: clk@01c201f4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-out-clk";
			reg = <0x01c201f4 0x4>;
			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
			clock-output-names = "clk_out_b";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		emac: ethernet@01c0b000 {
			compatible = "allwinner,sun4i-emac";
			reg = <0x01c0b000 0x1000>;
			interrupts = <0 55 4>;
			clocks = <&ahb_gates 17>;
			status = "disabled";
		};

		mdio@01c0b080 {
			compatible = "allwinner,sun4i-mdio";
			reg = <0x01c0b080 0x14>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun7i-a20-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <0 28 4>;
			clocks = <&apb0_gates 5>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PB22", "PB23";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart2_pins_a: uart2@0 {
				allwinner,pins = "PI16", "PI17", "PI18", "PI19";
				allwinner,function = "uart2";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart6_pins_a: uart6@0 {
				allwinner,pins = "PI12", "PI13";
				allwinner,function = "uart6";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart7_pins_a: uart7@0 {
				allwinner,pins = "PI20", "PI21";
				allwinner,function = "uart7";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PB0", "PB1";
				allwinner,function = "i2c0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PB18", "PB19";
				allwinner,function = "i2c1";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PB20", "PB21";
				allwinner,function = "i2c2";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			emac_pins_a: emac0@0 {
				allwinner,pins = "PA0", "PA1", "PA2",
						"PA3", "PA4", "PA5", "PA6",
						"PA7", "PA8", "PA9", "PA10",
						"PA11", "PA12", "PA13", "PA14",
						"PA15", "PA16";
				allwinner,function = "emac";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			clk_out_a_pins_a: clk_out_a@0 {
				allwinner,pins = "PI12";
				allwinner,function = "clk_out_a";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			clk_out_b_pins_a: clk_out_b@0 {
				allwinner,pins = "PI13";
				allwinner,function = "clk_out_b";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			gmac_pins_mii_a: gmac_mii@0 {
				allwinner,pins = "PA0", "PA1", "PA2",
						"PA3", "PA4", "PA5", "PA6",
						"PA7", "PA8", "PA9", "PA10",
						"PA11", "PA12", "PA13", "PA14",
						"PA15", "PA16";
				allwinner,function = "gmac";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			gmac_pins_rgmii_a: gmac_rgmii@0 {
				allwinner,pins = "PA0", "PA1", "PA2",
						"PA3", "PA4", "PA5", "PA6",
						"PA7", "PA8", "PA10",
						"PA11", "PA12", "PA13",
						"PA15", "PA16";
				allwinner,function = "gmac";
				/*
				 * data lines in RGMII mode use DDR mode
				 * and need a higher signal drive strength
				 */
				allwinner,drive = <3>;
				allwinner,pull = <0>;
			};
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-timer";
			reg = <0x01c20c00 0x90>;
			interrupts = <0 22 4>,
				     <0 23 4>,
				     <0 24 4>,
				     <0 25 4>,
				     <0 67 4>,
				     <0 68 4>;
			clocks = <&osc24M>;
		};

		wdt: watchdog@01c20c90 {
			compatible = "allwinner,sun4i-wdt";
			reg = <0x01c20c90 0x10>;
		};

		rtc: rtc@01c20d00 {
			compatible = "allwinner,sun7i-a20-rtc";
			reg = <0x01c20d00 0x20>;
			interrupts = <0 24 1>;
		};

		sid: eeprom@01c23800 {
			compatible = "allwinner,sun7i-a20-sid";
			reg = <0x01c23800 0x200>;
		};

		rtp: rtp@01c25000 {
			compatible = "allwinner,sun4i-ts";
			reg = <0x01c25000 0x100>;
			interrupts = <0 29 4>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <0 1 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 16>;
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <0 2 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 17>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <0 3 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 18>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <0 4 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 19>;
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <0 17 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 20>;
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
			interrupts = <0 18 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 21>;
			status = "disabled";
		};

		uart6: serial@01c29800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29800 0x400>;
			interrupts = <0 19 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 22>;
			status = "disabled";
		};

		uart7: serial@01c29c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29c00 0x400>;
			interrupts = <0 20 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 23>;
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <0 7 4>;
			clocks = <&apb1_gates 0>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <0 8 4>;
			clocks = <&apb1_gates 1>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <0 9 4>;
			clocks = <&apb1_gates 2>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c3: i2c@01c2b800 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2b800 0x400>;
			interrupts = <0 88 4>;
			clocks = <&apb1_gates 3>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c4: i2c@01c2bc00 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2bc00 0x400>;
			interrupts = <0 89 4>;
			clocks = <&apb1_gates 15>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		gmac: ethernet@01c50000 {
			compatible = "allwinner,sun7i-a20-gmac";
			reg = <0x01c50000 0x10000>;
			interrupts = <0 85 4>;
			interrupt-names = "macirq";
			clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
			clock-names = "stmmaceth", "allwinner_gmac_tx";
			snps,pbl = <2>;
			snps,fixed-burst;
			snps,force_sf_dma_mode;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		hstimer@01c60000 {
			compatible = "allwinner,sun7i-a20-hstimer";
			reg = <0x01c60000 0x1000>;
			interrupts = <0 81 1>,
				     <0 82 1>,
				     <0 83 1>,
				     <0 84 1>;
			clocks = <&ahb_gates 28>;
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 0xf04>;
		};
	};
};
Commit	Line	Data
4790ecfa MR	1	/*
	2	* Copyright 2013 Maxime Ripard
	3	*
	4	* Maxime Ripard <maxime.ripard@free-electrons.com>
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
	14	/include/ "skeleton.dtsi"
	15
	16	/ {
	17	interrupt-parent = <&gic>;
	18
e751cce9	19	aliases {
18428f77	20	ethernet0 = &gmac;
4566b4be MR	21	serial0 = &uart0;
	22	serial1 = &uart1;
	23	serial2 = &uart2;
	24	serial3 = &uart3;
	25	serial4 = &uart4;
	26	serial5 = &uart5;
	27	serial6 = &uart6;
	28	serial7 = &uart7;
e751cce9 EL	29	};
e751cce9 EL	30
4790ecfa MR	31	cpus {
	32	#address-cells = <1>;
	33	#size-cells = <0>;
	34
	35	cpu@0 {
	36	compatible = "arm,cortex-a7";
	37	device_type = "cpu";
	38	reg = <0>;
	39	};
	40
	41	cpu@1 {
	42	compatible = "arm,cortex-a7";
	43	device_type = "cpu";
	44	reg = <1>;
	45	};
	46	};
	47
	48	memory {
	49	reg = <0x40000000 0x80000000>;
	50	};
	51
	52	clocks {
	53	#address-cells = <1>;
	54	#size-cells = <1>;
	55	ranges;
	56
06067a2f	57	osc24M: clk@01c20050 {
4790ecfa	58	#clock-cells = <0>;
de7dc935 MR	59	compatible = "allwinner,sun4i-osc-clk";
de7dc935 MR	60	reg = <0x01c20050 0x4>;
4790ecfa	61	clock-frequency = <24000000>;
06067a2f	62	clock-output-names = "osc24M";
4790ecfa MR	63	};
4790ecfa MR	64
673fac74	65	osc32k: clk@0 {
4790ecfa MR	66	#clock-cells = <0>;
	67	compatible = "fixed-clock";
	68	clock-frequency = <32768>;
673fac74	69	clock-output-names = "osc32k";
4790ecfa	70	};
de7dc935	71
06067a2f	72	pll1: clk@01c20000 {
de7dc935 MR	73	#clock-cells = <0>;
	74	compatible = "allwinner,sun4i-pll1-clk";
	75	reg = <0x01c20000 0x4>;
	76	clocks = <&osc24M>;
06067a2f	77	clock-output-names = "pll1";
de7dc935 MR	78	};
de7dc935 MR	79
06067a2f	80	pll4: clk@01c20018 {
de7dc935	81	#clock-cells = <0>;
ec5589f7 EL	82	compatible = "allwinner,sun4i-pll1-clk";
	83	reg = <0x01c20018 0x4>;
	84	clocks = <&osc24M>;
06067a2f	85	clock-output-names = "pll4";
ec5589f7 EL	86	};
ec5589f7 EL	87
06067a2f	88	pll5: clk@01c20020 {
c3e5e66b EL	89	#clock-cells = <1>;
	90	compatible = "allwinner,sun4i-pll5-clk";
	91	reg = <0x01c20020 0x4>;
	92	clocks = <&osc24M>;
	93	clock-output-names = "pll5_ddr", "pll5_other";
	94	};
	95
06067a2f	96	pll6: clk@01c20028 {
c3e5e66b EL	97	#clock-cells = <1>;
	98	compatible = "allwinner,sun4i-pll6-clk";
	99	reg = <0x01c20028 0x4>;
	100	clocks = <&osc24M>;
	101	clock-output-names = "pll6_sata", "pll6_other", "pll6";
de7dc935 MR	102	};
	103
	104	cpu: cpu@01c20054 {
	105	#clock-cells = <0>;
	106	compatible = "allwinner,sun4i-cpu-clk";
	107	reg = <0x01c20054 0x4>;
c3e5e66b	108	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
06067a2f	109	clock-output-names = "cpu";
de7dc935 MR	110	};
	111
	112	axi: axi@01c20054 {
	113	#clock-cells = <0>;
	114	compatible = "allwinner,sun4i-axi-clk";
	115	reg = <0x01c20054 0x4>;
	116	clocks = <&cpu>;
06067a2f	117	clock-output-names = "axi";
de7dc935 MR	118	};
	119
	120	ahb: ahb@01c20054 {
	121	#clock-cells = <0>;
	122	compatible = "allwinner,sun4i-ahb-clk";
	123	reg = <0x01c20054 0x4>;
	124	clocks = <&axi>;
06067a2f	125	clock-output-names = "ahb";
de7dc935 MR	126	};
de7dc935 MR	127
06067a2f	128	ahb_gates: clk@01c20060 {
de7dc935 MR	129	#clock-cells = <1>;
	130	compatible = "allwinner,sun7i-a20-ahb-gates-clk";
	131	reg = <0x01c20060 0x8>;
	132	clocks = <&ahb>;
	133	clock-output-names = "ahb_usb0", "ahb_ehci0",
	134	"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
	135	"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
	136	"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
	137	"ahb_nand", "ahb_sdram", "ahb_ace",
	138	"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
	139	"ahb_spi2", "ahb_spi3", "ahb_sata",
	140	"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
	141	"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
	142	"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
	143	"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
	144	"ahb_de_fe1", "ahb_gmac", "ahb_mp",
	145	"ahb_mali";
	146	};
	147
	148	apb0: apb0@01c20054 {
	149	#clock-cells = <0>;
	150	compatible = "allwinner,sun4i-apb0-clk";
	151	reg = <0x01c20054 0x4>;
	152	clocks = <&ahb>;
06067a2f	153	clock-output-names = "apb0";
de7dc935 MR	154	};
de7dc935 MR	155
06067a2f	156	apb0_gates: clk@01c20068 {
de7dc935 MR	157	#clock-cells = <1>;
	158	compatible = "allwinner,sun7i-a20-apb0-gates-clk";
	159	reg = <0x01c20068 0x4>;
	160	clocks = <&apb0>;
	161	clock-output-names = "apb0_codec", "apb0_spdif",
	162	"apb0_ac97", "apb0_iis0", "apb0_iis1",
	163	"apb0_pio", "apb0_ir0", "apb0_ir1",
	164	"apb0_iis2", "apb0_keypad";
	165	};
	166
	167	apb1_mux: apb1_mux@01c20058 {
	168	#clock-cells = <0>;
	169	compatible = "allwinner,sun4i-apb1-mux-clk";
	170	reg = <0x01c20058 0x4>;
c3e5e66b	171	clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
06067a2f	172	clock-output-names = "apb1_mux";
de7dc935 MR	173	};
	174
	175	apb1: apb1@01c20058 {
	176	#clock-cells = <0>;
	177	compatible = "allwinner,sun4i-apb1-clk";
	178	reg = <0x01c20058 0x4>;
	179	clocks = <&apb1_mux>;
06067a2f	180	clock-output-names = "apb1";
de7dc935 MR	181	};
de7dc935 MR	182
06067a2f	183	apb1_gates: clk@01c2006c {
de7dc935 MR	184	#clock-cells = <1>;
	185	compatible = "allwinner,sun7i-a20-apb1-gates-clk";
	186	reg = <0x01c2006c 0x4>;
	187	clocks = <&apb1>;
	188	clock-output-names = "apb1_i2c0", "apb1_i2c1",
	189	"apb1_i2c2", "apb1_i2c3", "apb1_can",
	190	"apb1_scr", "apb1_ps20", "apb1_ps21",
	191	"apb1_i2c4", "apb1_uart0", "apb1_uart1",
	192	"apb1_uart2", "apb1_uart3", "apb1_uart4",
	193	"apb1_uart5", "apb1_uart6", "apb1_uart7";
	194	};
1c92b95b EL	195
	196	nand_clk: clk@01c20080 {
	197	#clock-cells = <0>;
	198	compatible = "allwinner,sun4i-mod0-clk";
	199	reg = <0x01c20080 0x4>;
	200	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	201	clock-output-names = "nand";
	202	};
	203
	204	ms_clk: clk@01c20084 {
	205	#clock-cells = <0>;
	206	compatible = "allwinner,sun4i-mod0-clk";
	207	reg = <0x01c20084 0x4>;
	208	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	209	clock-output-names = "ms";
	210	};
	211
	212	mmc0_clk: clk@01c20088 {
	213	#clock-cells = <0>;
	214	compatible = "allwinner,sun4i-mod0-clk";
	215	reg = <0x01c20088 0x4>;
	216	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	217	clock-output-names = "mmc0";
	218	};
	219
	220	mmc1_clk: clk@01c2008c {
	221	#clock-cells = <0>;
	222	compatible = "allwinner,sun4i-mod0-clk";
	223	reg = <0x01c2008c 0x4>;
	224	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	225	clock-output-names = "mmc1";
	226	};
	227
	228	mmc2_clk: clk@01c20090 {
	229	#clock-cells = <0>;
	230	compatible = "allwinner,sun4i-mod0-clk";
	231	reg = <0x01c20090 0x4>;
	232	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	233	clock-output-names = "mmc2";
	234	};
	235
	236	mmc3_clk: clk@01c20094 {
	237	#clock-cells = <0>;
	238	compatible = "allwinner,sun4i-mod0-clk";
	239	reg = <0x01c20094 0x4>;
	240	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	241	clock-output-names = "mmc3";
	242	};
	243
	244	ts_clk: clk@01c20098 {
	245	#clock-cells = <0>;
	246	compatible = "allwinner,sun4i-mod0-clk";
	247	reg = <0x01c20098 0x4>;
	248	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	249	clock-output-names = "ts";
	250	};
	251
	252	ss_clk: clk@01c2009c {
	253	#clock-cells = <0>;
	254	compatible = "allwinner,sun4i-mod0-clk";
	255	reg = <0x01c2009c 0x4>;
	256	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	257	clock-output-names = "ss";
	258	};
259
260	spi0_clk: clk@01c200a0 {
261	#clock-cells = <0>;
262	compatible = "allwinner,sun4i-mod0-clk";
263	reg = <0x01c200a0 0x4>;
264	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
265	clock-output-names = "spi0";
266	};
267
268	spi1_clk: clk@01c200a4 {
269	#clock-cells = <0>;
270	compatible = "allwinner,sun4i-mod0-clk";
271	reg = <0x01c200a4 0x4>;
272	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
273	clock-output-names = "spi1";
274	};
275
276	spi2_clk: clk@01c200a8 {
277	#clock-cells = <0>;
278	compatible = "allwinner,sun4i-mod0-clk";
279	reg = <0x01c200a8 0x4>;
280	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
281	clock-output-names = "spi2";
282	};
283
284	pata_clk: clk@01c200ac {
285	#clock-cells = <0>;
286	compatible = "allwinner,sun4i-mod0-clk";
287	reg = <0x01c200ac 0x4>;
288	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289	clock-output-names = "pata";
290	};
291
292	ir0_clk: clk@01c200b0 {
293	#clock-cells = <0>;
294	compatible = "allwinner,sun4i-mod0-clk";
295	reg = <0x01c200b0 0x4>;
296	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
297	clock-output-names = "ir0";
298	};
299
300	ir1_clk: clk@01c200b4 {
301	#clock-cells = <0>;
302	compatible = "allwinner,sun4i-mod0-clk";
303	reg = <0x01c200b4 0x4>;
304	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
305	clock-output-names = "ir1";
306	};
307
308	spi3_clk: clk@01c200d4 {
309	#clock-cells = <0>;
310	compatible = "allwinner,sun4i-mod0-clk";
311	reg = <0x01c200d4 0x4>;
312	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
313	clock-output-names = "spi3";
314	};
118c07ae EL	315
	316	mbus_clk: clk@01c2015c {
	317	#clock-cells = <0>;
	318	compatible = "allwinner,sun4i-mod0-clk";
	319	reg = <0x01c2015c 0x4>;
	320	clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
	321	clock-output-names = "mbus";
	322	};
0aff0370	323
daed5a81 CYT	324	/*
	325	* The following two are dummy clocks, placeholders used in the gmac_tx
	326	* clock. The gmac driver will choose one parent depending on the PHY
	327	* interface mode, using clk_set_rate auto-reparenting.
	328	* The actual TX clock rate is not controlled by the gmac_tx clock.
	329	*/
	330	mii_phy_tx_clk: clk@2 {
	331	#clock-cells = <0>;
	332	compatible = "fixed-clock";
	333	clock-frequency = <25000000>;
	334	clock-output-names = "mii_phy_tx";
	335	};
	336
	337	gmac_int_tx_clk: clk@3 {
	338	#clock-cells = <0>;
	339	compatible = "fixed-clock";
	340	clock-frequency = <125000000>;
	341	clock-output-names = "gmac_int_tx";
	342	};
	343
	344	gmac_tx_clk: clk@01c20164 {
	345	#clock-cells = <0>;
	346	compatible = "allwinner,sun7i-a20-gmac-clk";
	347	reg = <0x01c20164 0x4>;
	348	clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
	349	clock-output-names = "gmac_tx";
	350	};
	351
0aff0370 CYT	352	/*
	353	* Dummy clock used by output clocks
	354	*/
	355	osc24M_32k: clk@1 {
	356	#clock-cells = <0>;
	357	compatible = "fixed-factor-clock";
	358	clock-div = <750>;
	359	clock-mult = <1>;
	360	clocks = <&osc24M>;
	361	clock-output-names = "osc24M_32k";
	362	};
	363
	364	clk_out_a: clk@01c201f0 {
	365	#clock-cells = <0>;
	366	compatible = "allwinner,sun7i-a20-out-clk";
	367	reg = <0x01c201f0 0x4>;
	368	clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
	369	clock-output-names = "clk_out_a";
	370	};
	371
	372	clk_out_b: clk@01c201f4 {
	373	#clock-cells = <0>;
	374	compatible = "allwinner,sun7i-a20-out-clk";
	375	reg = <0x01c201f4 0x4>;
	376	clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
	377	clock-output-names = "clk_out_b";
	378	};
4790ecfa MR	379	};
	380
	381	soc@01c00000 {
	382	compatible = "simple-bus";
	383	#address-cells = <1>;
	384	#size-cells = <1>;
	385	ranges;
	386
2e804d03 MR	387	emac: ethernet@01c0b000 {
	388	compatible = "allwinner,sun4i-emac";
	389	reg = <0x01c0b000 0x1000>;
378d0aee	390	interrupts = <0 55 4>;
2e804d03 MR	391	clocks = <&ahb_gates 17>;
	392	status = "disabled";
	393	};
	394
	395	mdio@01c0b080 {
	396	compatible = "allwinner,sun4i-mdio";
	397	reg = <0x01c0b080 0x14>;
	398	status = "disabled";
	399	#address-cells = <1>;
	400	#size-cells = <0>;
	401	};
	402
17eac031 MR	403	pio: pinctrl@01c20800 {
	404	compatible = "allwinner,sun7i-a20-pinctrl";
	405	reg = <0x01c20800 0x400>;
378d0aee	406	interrupts = <0 28 4>;
de7dc935	407	clocks = <&apb0_gates 5>;
17eac031 MR	408	gpio-controller;
	409	interrupt-controller;
	410	#address-cells = <1>;
	411	#size-cells = <0>;
	412	#gpio-cells = <3>;
9f229ba9 MR	413
	414	uart0_pins_a: uart0@0 {
	415	allwinner,pins = "PB22", "PB23";
	416	allwinner,function = "uart0";
	417	allwinner,drive = <0>;
	418	allwinner,pull = <0>;
	419	};
	420
4261ec43 CYT	421	uart2_pins_a: uart2@0 {
	422	allwinner,pins = "PI16", "PI17", "PI18", "PI19";
	423	allwinner,function = "uart2";
	424	allwinner,drive = <0>;
	425	allwinner,pull = <0>;
	426	};
	427
9f229ba9 MR	428	uart6_pins_a: uart6@0 {
	429	allwinner,pins = "PI12", "PI13";
	430	allwinner,function = "uart6";
	431	allwinner,drive = <0>;
	432	allwinner,pull = <0>;
	433	};
	434
	435	uart7_pins_a: uart7@0 {
	436	allwinner,pins = "PI20", "PI21";
	437	allwinner,function = "uart7";
	438	allwinner,drive = <0>;
	439	allwinner,pull = <0>;
	440	};
756084c5	441
e5496a31 MR	442	i2c0_pins_a: i2c0@0 {
	443	allwinner,pins = "PB0", "PB1";
	444	allwinner,function = "i2c0";
	445	allwinner,drive = <0>;
	446	allwinner,pull = <0>;
	447	};
	448
	449	i2c1_pins_a: i2c1@0 {
	450	allwinner,pins = "PB18", "PB19";
	451	allwinner,function = "i2c1";
	452	allwinner,drive = <0>;
	453	allwinner,pull = <0>;
	454	};
	455
	456	i2c2_pins_a: i2c2@0 {
	457	allwinner,pins = "PB20", "PB21";
	458	allwinner,function = "i2c2";
	459	allwinner,drive = <0>;
	460	allwinner,pull = <0>;
	461	};
	462
756084c5 MR	463	emac_pins_a: emac0@0 {
	464	allwinner,pins = "PA0", "PA1", "PA2",
	465	"PA3", "PA4", "PA5", "PA6",
	466	"PA7", "PA8", "PA9", "PA10",
	467	"PA11", "PA12", "PA13", "PA14",
	468	"PA15", "PA16";
	469	allwinner,function = "emac";
	470	allwinner,drive = <0>;
	471	allwinner,pull = <0>;
	472	};
f2e0759e CYT	473
	474	clk_out_a_pins_a: clk_out_a@0 {
	475	allwinner,pins = "PI12";
	476	allwinner,function = "clk_out_a";
	477	allwinner,drive = <0>;
	478	allwinner,pull = <0>;
	479	};
	480
	481	clk_out_b_pins_a: clk_out_b@0 {
	482	allwinner,pins = "PI13";
	483	allwinner,function = "clk_out_b";
	484	allwinner,drive = <0>;
	485	allwinner,pull = <0>;
	486	};
129ccbcd CYT	487
	488	gmac_pins_mii_a: gmac_mii@0 {
	489	allwinner,pins = "PA0", "PA1", "PA2",
	490	"PA3", "PA4", "PA5", "PA6",
	491	"PA7", "PA8", "PA9", "PA10",
	492	"PA11", "PA12", "PA13", "PA14",
	493	"PA15", "PA16";
	494	allwinner,function = "gmac";
	495	allwinner,drive = <0>;
	496	allwinner,pull = <0>;
	497	};
	498
	499	gmac_pins_rgmii_a: gmac_rgmii@0 {
	500	allwinner,pins = "PA0", "PA1", "PA2",
	501	"PA3", "PA4", "PA5", "PA6",
	502	"PA7", "PA8", "PA10",
	503	"PA11", "PA12", "PA13",
	504	"PA15", "PA16";
	505	allwinner,function = "gmac";
	506	/*
	507	* data lines in RGMII mode use DDR mode
	508	* and need a higher signal drive strength
	509	*/
	510	allwinner,drive = <3>;
	511	allwinner,pull = <0>;
	512	};
17eac031 MR	513	};
17eac031 MR	514
4790ecfa MR	515	timer@01c20c00 {
	516	compatible = "allwinner,sun4i-timer";
	517	reg = <0x01c20c00 0x90>;
378d0aee MR	518	interrupts = <0 22 4>,
	519	<0 23 4>,
	520	<0 24 4>,
	521	<0 25 4>,
	522	<0 67 4>,
	523	<0 68 4>;
4790ecfa MR	524	clocks = <&osc24M>;
	525	};
	526
	527	wdt: watchdog@01c20c90 {
	528	compatible = "allwinner,sun4i-wdt";
	529	reg = <0x01c20c90 0x10>;
	530	};
	531
b5d905c7 CC	532	rtc: rtc@01c20d00 {
	533	compatible = "allwinner,sun7i-a20-rtc";
	534	reg = <0x01c20d00 0x20>;
	535	interrupts = <0 24 1>;
	536	};
	537
2bad969f OS	538	sid: eeprom@01c23800 {
	539	compatible = "allwinner,sun7i-a20-sid";
	540	reg = <0x01c23800 0x200>;
	541	};
	542
00f7ed8d HG	543	rtp: rtp@01c25000 {
	544	compatible = "allwinner,sun4i-ts";
	545	reg = <0x01c25000 0x100>;
	546	interrupts = <0 29 4>;
	547	};
	548
4790ecfa MR	549	uart0: serial@01c28000 {
	550	compatible = "snps,dw-apb-uart";
	551	reg = <0x01c28000 0x400>;
378d0aee	552	interrupts = <0 1 4>;
4790ecfa MR	553	reg-shift = <2>;
4790ecfa MR	554	reg-io-width = <4>;
de7dc935	555	clocks = <&apb1_gates 16>;
4790ecfa MR	556	status = "disabled";
	557	};
	558
	559	uart1: serial@01c28400 {
	560	compatible = "snps,dw-apb-uart";
	561	reg = <0x01c28400 0x400>;
378d0aee	562	interrupts = <0 2 4>;
4790ecfa MR	563	reg-shift = <2>;
4790ecfa MR	564	reg-io-width = <4>;
de7dc935	565	clocks = <&apb1_gates 17>;
4790ecfa MR	566	status = "disabled";
	567	};
	568
	569	uart2: serial@01c28800 {
	570	compatible = "snps,dw-apb-uart";
	571	reg = <0x01c28800 0x400>;
378d0aee	572	interrupts = <0 3 4>;
4790ecfa MR	573	reg-shift = <2>;
4790ecfa MR	574	reg-io-width = <4>;
de7dc935	575	clocks = <&apb1_gates 18>;
4790ecfa MR	576	status = "disabled";
	577	};
	578
	579	uart3: serial@01c28c00 {
	580	compatible = "snps,dw-apb-uart";
	581	reg = <0x01c28c00 0x400>;
378d0aee	582	interrupts = <0 4 4>;
4790ecfa MR	583	reg-shift = <2>;
4790ecfa MR	584	reg-io-width = <4>;
de7dc935	585	clocks = <&apb1_gates 19>;
4790ecfa MR	586	status = "disabled";
	587	};
	588
	589	uart4: serial@01c29000 {
	590	compatible = "snps,dw-apb-uart";
	591	reg = <0x01c29000 0x400>;
378d0aee	592	interrupts = <0 17 4>;
4790ecfa MR	593	reg-shift = <2>;
4790ecfa MR	594	reg-io-width = <4>;
de7dc935	595	clocks = <&apb1_gates 20>;
4790ecfa MR	596	status = "disabled";
	597	};
	598
	599	uart5: serial@01c29400 {
	600	compatible = "snps,dw-apb-uart";
	601	reg = <0x01c29400 0x400>;
378d0aee	602	interrupts = <0 18 4>;
4790ecfa MR	603	reg-shift = <2>;
4790ecfa MR	604	reg-io-width = <4>;
de7dc935	605	clocks = <&apb1_gates 21>;
4790ecfa MR	606	status = "disabled";
	607	};
	608
	609	uart6: serial@01c29800 {
	610	compatible = "snps,dw-apb-uart";
	611	reg = <0x01c29800 0x400>;
378d0aee	612	interrupts = <0 19 4>;
4790ecfa MR	613	reg-shift = <2>;
4790ecfa MR	614	reg-io-width = <4>;
de7dc935	615	clocks = <&apb1_gates 22>;
4790ecfa MR	616	status = "disabled";
	617	};
	618
	619	uart7: serial@01c29c00 {
	620	compatible = "snps,dw-apb-uart";
	621	reg = <0x01c29c00 0x400>;
378d0aee	622	interrupts = <0 20 4>;
4790ecfa MR	623	reg-shift = <2>;
4790ecfa MR	624	reg-io-width = <4>;
de7dc935	625	clocks = <&apb1_gates 23>;
4790ecfa MR	626	status = "disabled";
	627	};
	628
428abbb8 MR	629	i2c0: i2c@01c2ac00 {
	630	compatible = "allwinner,sun4i-i2c";
	631	reg = <0x01c2ac00 0x400>;
378d0aee	632	interrupts = <0 7 4>;
428abbb8 MR	633	clocks = <&apb1_gates 0>;
	634	clock-frequency = <100000>;
	635	status = "disabled";
	636	};
	637
	638	i2c1: i2c@01c2b000 {
	639	compatible = "allwinner,sun4i-i2c";
	640	reg = <0x01c2b000 0x400>;
378d0aee	641	interrupts = <0 8 4>;
428abbb8 MR	642	clocks = <&apb1_gates 1>;
	643	clock-frequency = <100000>;
	644	status = "disabled";
	645	};
	646
	647	i2c2: i2c@01c2b400 {
	648	compatible = "allwinner,sun4i-i2c";
	649	reg = <0x01c2b400 0x400>;
378d0aee	650	interrupts = <0 9 4>;
428abbb8 MR	651	clocks = <&apb1_gates 2>;
	652	clock-frequency = <100000>;
	653	status = "disabled";
	654	};
	655
	656	i2c3: i2c@01c2b800 {
	657	compatible = "allwinner,sun4i-i2c";
	658	reg = <0x01c2b800 0x400>;
378d0aee	659	interrupts = <0 88 4>;
428abbb8 MR	660	clocks = <&apb1_gates 3>;
	661	clock-frequency = <100000>;
	662	status = "disabled";
	663	};
	664
	665	i2c4: i2c@01c2bc00 {
	666	compatible = "allwinner,sun4i-i2c";
	667	reg = <0x01c2bc00 0x400>;
378d0aee	668	interrupts = <0 89 4>;
428abbb8 MR	669	clocks = <&apb1_gates 15>;
	670	clock-frequency = <100000>;
	671	status = "disabled";
	672	};
	673
c40b8d58 CYT	674	gmac: ethernet@01c50000 {
	675	compatible = "allwinner,sun7i-a20-gmac";
	676	reg = <0x01c50000 0x10000>;
	677	interrupts = <0 85 4>;
	678	interrupt-names = "macirq";
	679	clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
	680	clock-names = "stmmaceth", "allwinner_gmac_tx";
	681	snps,pbl = <2>;
	682	snps,fixed-burst;
	683	snps,force_sf_dma_mode;
	684	status = "disabled";
	685	#address-cells = <1>;
	686	#size-cells = <0>;
	687	};
	688
31f8ad38 MR	689	hstimer@01c60000 {
	690	compatible = "allwinner,sun7i-a20-hstimer";
	691	reg = <0x01c60000 0x1000>;
	692	interrupts = <0 81 1>,
	693	<0 82 1>,
	694	<0 83 1>,
	695	<0 84 1>;
	696	clocks = <&ahb_gates 28>;
	697	};
	698
4790ecfa MR	699	gic: interrupt-controller@01c81000 {
	700	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
	701	reg = <0x01c81000 0x1000>,
	702	<0x01c82000 0x1000>,
	703	<0x01c84000 0x2000>,
	704	<0x01c86000 0x2000>;
	705	interrupt-controller;
	706	#interrupt-cells = <3>;
	707	interrupts = <1 9 0xf04>;
	708	};
	709	};
	710	};