Commit | Line | Data |
---|---|---|
4790ecfa MR |
1 | /* |
2 | * Copyright 2013 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
394c56ce MR |
6 | * This file is dual-licensed: you can use it either under the terms |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
4790ecfa | 10 | * |
5186d83a | 11 | * a) This file is free software; you can redistribute it and/or |
394c56ce MR |
12 | * modify it under the terms of the GNU General Public License as |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
5186d83a | 16 | * This file is distributed in the hope that it will be useful, |
394c56ce MR |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public | |
5186d83a | 22 | * License along with this file; if not, write to the Free |
394c56ce MR |
23 | * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
24 | * MA 02110-1301 USA | |
25 | * | |
26 | * Or, alternatively, | |
27 | * | |
28 | * b) Permission is hereby granted, free of charge, to any person | |
29 | * obtaining a copy of this software and associated documentation | |
30 | * files (the "Software"), to deal in the Software without | |
31 | * restriction, including without limitation the rights to use, | |
32 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
33 | * sell copies of the Software, and to permit persons to whom the | |
34 | * Software is furnished to do so, subject to the following | |
35 | * conditions: | |
36 | * | |
37 | * The above copyright notice and this permission notice shall be | |
38 | * included in all copies or substantial portions of the Software. | |
39 | * | |
40 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
41 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
42 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
43 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
44 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
45 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
46 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
47 | * OTHER DEALINGS IN THE SOFTWARE. | |
4790ecfa MR |
48 | */ |
49 | ||
50 | /include/ "skeleton.dtsi" | |
51 | ||
52 | / { | |
53 | interrupt-parent = <&gic>; | |
54 | ||
e751cce9 | 55 | aliases { |
18428f77 | 56 | ethernet0 = &gmac; |
4566b4be MR |
57 | serial0 = &uart0; |
58 | serial1 = &uart1; | |
59 | serial2 = &uart2; | |
60 | serial3 = &uart3; | |
61 | serial4 = &uart4; | |
62 | serial5 = &uart5; | |
63 | serial6 = &uart6; | |
64 | serial7 = &uart7; | |
e751cce9 EL |
65 | }; |
66 | ||
8efc5c2b HG |
67 | chosen { |
68 | #address-cells = <1>; | |
69 | #size-cells = <1>; | |
70 | ranges; | |
71 | ||
a9f8cda3 HG |
72 | framebuffer@0 { |
73 | compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; | |
74 | allwinner,pipeline = "de_be0-lcd0-hdmi"; | |
678e75d3 HG |
75 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, |
76 | <&ahb_gates 44>; | |
8efc5c2b HG |
77 | status = "disabled"; |
78 | }; | |
79 | }; | |
80 | ||
4790ecfa MR |
81 | cpus { |
82 | #address-cells = <1>; | |
83 | #size-cells = <0>; | |
84 | ||
85 | cpu@0 { | |
86 | compatible = "arm,cortex-a7"; | |
87 | device_type = "cpu"; | |
88 | reg = <0>; | |
89 | }; | |
90 | ||
91 | cpu@1 { | |
92 | compatible = "arm,cortex-a7"; | |
93 | device_type = "cpu"; | |
94 | reg = <1>; | |
95 | }; | |
96 | }; | |
97 | ||
98 | memory { | |
99 | reg = <0x40000000 0x80000000>; | |
100 | }; | |
101 | ||
7902763e MZ |
102 | timer { |
103 | compatible = "arm,armv7-timer"; | |
104 | interrupts = <1 13 0xf08>, | |
105 | <1 14 0xf08>, | |
106 | <1 11 0xf08>, | |
107 | <1 10 0xf08>; | |
108 | }; | |
109 | ||
e29ea4d3 MR |
110 | pmu { |
111 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; | |
112 | interrupts = <0 120 4>, | |
113 | <0 121 4>; | |
114 | }; | |
115 | ||
4790ecfa MR |
116 | clocks { |
117 | #address-cells = <1>; | |
118 | #size-cells = <1>; | |
119 | ranges; | |
120 | ||
06067a2f | 121 | osc24M: clk@01c20050 { |
4790ecfa | 122 | #clock-cells = <0>; |
bf6534a1 | 123 | compatible = "allwinner,sun4i-a10-osc-clk"; |
de7dc935 | 124 | reg = <0x01c20050 0x4>; |
4790ecfa | 125 | clock-frequency = <24000000>; |
06067a2f | 126 | clock-output-names = "osc24M"; |
4790ecfa MR |
127 | }; |
128 | ||
673fac74 | 129 | osc32k: clk@0 { |
4790ecfa MR |
130 | #clock-cells = <0>; |
131 | compatible = "fixed-clock"; | |
132 | clock-frequency = <32768>; | |
673fac74 | 133 | clock-output-names = "osc32k"; |
4790ecfa | 134 | }; |
de7dc935 | 135 | |
06067a2f | 136 | pll1: clk@01c20000 { |
de7dc935 | 137 | #clock-cells = <0>; |
bf6534a1 | 138 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
de7dc935 MR |
139 | reg = <0x01c20000 0x4>; |
140 | clocks = <&osc24M>; | |
06067a2f | 141 | clock-output-names = "pll1"; |
de7dc935 MR |
142 | }; |
143 | ||
06067a2f | 144 | pll4: clk@01c20018 { |
de7dc935 | 145 | #clock-cells = <0>; |
04ebcb54 | 146 | compatible = "allwinner,sun7i-a20-pll4-clk"; |
ec5589f7 EL |
147 | reg = <0x01c20018 0x4>; |
148 | clocks = <&osc24M>; | |
06067a2f | 149 | clock-output-names = "pll4"; |
ec5589f7 EL |
150 | }; |
151 | ||
06067a2f | 152 | pll5: clk@01c20020 { |
c3e5e66b | 153 | #clock-cells = <1>; |
bf6534a1 | 154 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
c3e5e66b EL |
155 | reg = <0x01c20020 0x4>; |
156 | clocks = <&osc24M>; | |
157 | clock-output-names = "pll5_ddr", "pll5_other"; | |
158 | }; | |
159 | ||
06067a2f | 160 | pll6: clk@01c20028 { |
c3e5e66b | 161 | #clock-cells = <1>; |
bf6534a1 | 162 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
c3e5e66b EL |
163 | reg = <0x01c20028 0x4>; |
164 | clocks = <&osc24M>; | |
165 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
de7dc935 MR |
166 | }; |
167 | ||
04ebcb54 EL |
168 | pll8: clk@01c20040 { |
169 | #clock-cells = <0>; | |
170 | compatible = "allwinner,sun7i-a20-pll4-clk"; | |
171 | reg = <0x01c20040 0x4>; | |
172 | clocks = <&osc24M>; | |
173 | clock-output-names = "pll8"; | |
174 | }; | |
175 | ||
de7dc935 MR |
176 | cpu: cpu@01c20054 { |
177 | #clock-cells = <0>; | |
bf6534a1 | 178 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
de7dc935 | 179 | reg = <0x01c20054 0x4>; |
c3e5e66b | 180 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; |
06067a2f | 181 | clock-output-names = "cpu"; |
de7dc935 MR |
182 | }; |
183 | ||
184 | axi: axi@01c20054 { | |
185 | #clock-cells = <0>; | |
bf6534a1 | 186 | compatible = "allwinner,sun4i-a10-axi-clk"; |
de7dc935 MR |
187 | reg = <0x01c20054 0x4>; |
188 | clocks = <&cpu>; | |
06067a2f | 189 | clock-output-names = "axi"; |
de7dc935 MR |
190 | }; |
191 | ||
192 | ahb: ahb@01c20054 { | |
193 | #clock-cells = <0>; | |
bf6534a1 | 194 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
de7dc935 MR |
195 | reg = <0x01c20054 0x4>; |
196 | clocks = <&axi>; | |
06067a2f | 197 | clock-output-names = "ahb"; |
de7dc935 MR |
198 | }; |
199 | ||
06067a2f | 200 | ahb_gates: clk@01c20060 { |
de7dc935 MR |
201 | #clock-cells = <1>; |
202 | compatible = "allwinner,sun7i-a20-ahb-gates-clk"; | |
203 | reg = <0x01c20060 0x8>; | |
204 | clocks = <&ahb>; | |
205 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
206 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", | |
207 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
208 | "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", | |
209 | "ahb_nand", "ahb_sdram", "ahb_ace", | |
210 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", | |
211 | "ahb_spi2", "ahb_spi3", "ahb_sata", | |
212 | "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", | |
213 | "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", | |
214 | "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", | |
215 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
216 | "ahb_de_fe1", "ahb_gmac", "ahb_mp", | |
217 | "ahb_mali"; | |
218 | }; | |
219 | ||
220 | apb0: apb0@01c20054 { | |
221 | #clock-cells = <0>; | |
bf6534a1 | 222 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
de7dc935 MR |
223 | reg = <0x01c20054 0x4>; |
224 | clocks = <&ahb>; | |
06067a2f | 225 | clock-output-names = "apb0"; |
de7dc935 MR |
226 | }; |
227 | ||
06067a2f | 228 | apb0_gates: clk@01c20068 { |
de7dc935 MR |
229 | #clock-cells = <1>; |
230 | compatible = "allwinner,sun7i-a20-apb0-gates-clk"; | |
231 | reg = <0x01c20068 0x4>; | |
232 | clocks = <&apb0>; | |
233 | clock-output-names = "apb0_codec", "apb0_spdif", | |
234 | "apb0_ac97", "apb0_iis0", "apb0_iis1", | |
235 | "apb0_pio", "apb0_ir0", "apb0_ir1", | |
236 | "apb0_iis2", "apb0_keypad"; | |
237 | }; | |
238 | ||
acbcc0f0 | 239 | apb1: clk@01c20058 { |
de7dc935 | 240 | #clock-cells = <0>; |
bf6534a1 | 241 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
de7dc935 | 242 | reg = <0x01c20058 0x4>; |
acbcc0f0 | 243 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
06067a2f | 244 | clock-output-names = "apb1"; |
de7dc935 MR |
245 | }; |
246 | ||
06067a2f | 247 | apb1_gates: clk@01c2006c { |
de7dc935 MR |
248 | #clock-cells = <1>; |
249 | compatible = "allwinner,sun7i-a20-apb1-gates-clk"; | |
250 | reg = <0x01c2006c 0x4>; | |
251 | clocks = <&apb1>; | |
252 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
253 | "apb1_i2c2", "apb1_i2c3", "apb1_can", | |
254 | "apb1_scr", "apb1_ps20", "apb1_ps21", | |
255 | "apb1_i2c4", "apb1_uart0", "apb1_uart1", | |
256 | "apb1_uart2", "apb1_uart3", "apb1_uart4", | |
257 | "apb1_uart5", "apb1_uart6", "apb1_uart7"; | |
258 | }; | |
1c92b95b EL |
259 | |
260 | nand_clk: clk@01c20080 { | |
261 | #clock-cells = <0>; | |
bf6534a1 | 262 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
263 | reg = <0x01c20080 0x4>; |
264 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
265 | clock-output-names = "nand"; | |
266 | }; | |
267 | ||
268 | ms_clk: clk@01c20084 { | |
269 | #clock-cells = <0>; | |
bf6534a1 | 270 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
271 | reg = <0x01c20084 0x4>; |
272 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
273 | clock-output-names = "ms"; | |
274 | }; | |
275 | ||
276 | mmc0_clk: clk@01c20088 { | |
277 | #clock-cells = <0>; | |
bf6534a1 | 278 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
279 | reg = <0x01c20088 0x4>; |
280 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
281 | clock-output-names = "mmc0"; | |
282 | }; | |
283 | ||
284 | mmc1_clk: clk@01c2008c { | |
285 | #clock-cells = <0>; | |
bf6534a1 | 286 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
287 | reg = <0x01c2008c 0x4>; |
288 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
289 | clock-output-names = "mmc1"; | |
290 | }; | |
291 | ||
292 | mmc2_clk: clk@01c20090 { | |
293 | #clock-cells = <0>; | |
bf6534a1 | 294 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
295 | reg = <0x01c20090 0x4>; |
296 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
297 | clock-output-names = "mmc2"; | |
298 | }; | |
299 | ||
300 | mmc3_clk: clk@01c20094 { | |
301 | #clock-cells = <0>; | |
bf6534a1 | 302 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
303 | reg = <0x01c20094 0x4>; |
304 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
305 | clock-output-names = "mmc3"; | |
306 | }; | |
307 | ||
308 | ts_clk: clk@01c20098 { | |
309 | #clock-cells = <0>; | |
bf6534a1 | 310 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
311 | reg = <0x01c20098 0x4>; |
312 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
313 | clock-output-names = "ts"; | |
314 | }; | |
315 | ||
316 | ss_clk: clk@01c2009c { | |
317 | #clock-cells = <0>; | |
bf6534a1 | 318 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
319 | reg = <0x01c2009c 0x4>; |
320 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
321 | clock-output-names = "ss"; | |
322 | }; | |
323 | ||
324 | spi0_clk: clk@01c200a0 { | |
325 | #clock-cells = <0>; | |
bf6534a1 | 326 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
327 | reg = <0x01c200a0 0x4>; |
328 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
329 | clock-output-names = "spi0"; | |
330 | }; | |
331 | ||
332 | spi1_clk: clk@01c200a4 { | |
333 | #clock-cells = <0>; | |
bf6534a1 | 334 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
335 | reg = <0x01c200a4 0x4>; |
336 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
337 | clock-output-names = "spi1"; | |
338 | }; | |
339 | ||
340 | spi2_clk: clk@01c200a8 { | |
341 | #clock-cells = <0>; | |
bf6534a1 | 342 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
343 | reg = <0x01c200a8 0x4>; |
344 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
345 | clock-output-names = "spi2"; | |
346 | }; | |
347 | ||
348 | pata_clk: clk@01c200ac { | |
349 | #clock-cells = <0>; | |
bf6534a1 | 350 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
351 | reg = <0x01c200ac 0x4>; |
352 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
353 | clock-output-names = "pata"; | |
354 | }; | |
355 | ||
356 | ir0_clk: clk@01c200b0 { | |
357 | #clock-cells = <0>; | |
bf6534a1 | 358 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
359 | reg = <0x01c200b0 0x4>; |
360 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
361 | clock-output-names = "ir0"; | |
362 | }; | |
363 | ||
364 | ir1_clk: clk@01c200b4 { | |
365 | #clock-cells = <0>; | |
bf6534a1 | 366 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
367 | reg = <0x01c200b4 0x4>; |
368 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
369 | clock-output-names = "ir1"; | |
370 | }; | |
371 | ||
434e41b3 RB |
372 | usb_clk: clk@01c200cc { |
373 | #clock-cells = <1>; | |
374 | #reset-cells = <1>; | |
375 | compatible = "allwinner,sun4i-a10-usb-clk"; | |
376 | reg = <0x01c200cc 0x4>; | |
377 | clocks = <&pll6 1>; | |
378 | clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; | |
379 | }; | |
380 | ||
1c92b95b EL |
381 | spi3_clk: clk@01c200d4 { |
382 | #clock-cells = <0>; | |
bf6534a1 | 383 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
384 | reg = <0x01c200d4 0x4>; |
385 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
386 | clock-output-names = "spi3"; | |
387 | }; | |
118c07ae EL |
388 | |
389 | mbus_clk: clk@01c2015c { | |
390 | #clock-cells = <0>; | |
7868c5eb | 391 | compatible = "allwinner,sun5i-a13-mbus-clk"; |
118c07ae EL |
392 | reg = <0x01c2015c 0x4>; |
393 | clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; | |
394 | clock-output-names = "mbus"; | |
395 | }; | |
0aff0370 | 396 | |
daed5a81 CYT |
397 | /* |
398 | * The following two are dummy clocks, placeholders used in the gmac_tx | |
399 | * clock. The gmac driver will choose one parent depending on the PHY | |
400 | * interface mode, using clk_set_rate auto-reparenting. | |
401 | * The actual TX clock rate is not controlled by the gmac_tx clock. | |
402 | */ | |
403 | mii_phy_tx_clk: clk@2 { | |
404 | #clock-cells = <0>; | |
405 | compatible = "fixed-clock"; | |
406 | clock-frequency = <25000000>; | |
407 | clock-output-names = "mii_phy_tx"; | |
408 | }; | |
409 | ||
410 | gmac_int_tx_clk: clk@3 { | |
411 | #clock-cells = <0>; | |
412 | compatible = "fixed-clock"; | |
413 | clock-frequency = <125000000>; | |
414 | clock-output-names = "gmac_int_tx"; | |
415 | }; | |
416 | ||
417 | gmac_tx_clk: clk@01c20164 { | |
418 | #clock-cells = <0>; | |
419 | compatible = "allwinner,sun7i-a20-gmac-clk"; | |
420 | reg = <0x01c20164 0x4>; | |
421 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | |
422 | clock-output-names = "gmac_tx"; | |
423 | }; | |
424 | ||
0aff0370 CYT |
425 | /* |
426 | * Dummy clock used by output clocks | |
427 | */ | |
428 | osc24M_32k: clk@1 { | |
429 | #clock-cells = <0>; | |
430 | compatible = "fixed-factor-clock"; | |
431 | clock-div = <750>; | |
432 | clock-mult = <1>; | |
433 | clocks = <&osc24M>; | |
434 | clock-output-names = "osc24M_32k"; | |
435 | }; | |
436 | ||
437 | clk_out_a: clk@01c201f0 { | |
438 | #clock-cells = <0>; | |
439 | compatible = "allwinner,sun7i-a20-out-clk"; | |
440 | reg = <0x01c201f0 0x4>; | |
441 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
442 | clock-output-names = "clk_out_a"; | |
443 | }; | |
444 | ||
445 | clk_out_b: clk@01c201f4 { | |
446 | #clock-cells = <0>; | |
447 | compatible = "allwinner,sun7i-a20-out-clk"; | |
448 | reg = <0x01c201f4 0x4>; | |
449 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
450 | clock-output-names = "clk_out_b"; | |
451 | }; | |
4790ecfa MR |
452 | }; |
453 | ||
454 | soc@01c00000 { | |
455 | compatible = "simple-bus"; | |
456 | #address-cells = <1>; | |
457 | #size-cells = <1>; | |
458 | ranges; | |
459 | ||
8ff973a2 CC |
460 | nmi_intc: interrupt-controller@01c00030 { |
461 | compatible = "allwinner,sun7i-a20-sc-nmi"; | |
462 | interrupt-controller; | |
463 | #interrupt-cells = <2>; | |
464 | reg = <0x01c00030 0x0c>; | |
465 | interrupts = <0 0 4>; | |
466 | }; | |
467 | ||
316e0b0e EL |
468 | dma: dma-controller@01c02000 { |
469 | compatible = "allwinner,sun4i-a10-dma"; | |
470 | reg = <0x01c02000 0x1000>; | |
471 | interrupts = <0 27 4>; | |
472 | clocks = <&ahb_gates 6>; | |
473 | #dma-cells = <2>; | |
474 | }; | |
475 | ||
36ab3e73 MR |
476 | spi0: spi@01c05000 { |
477 | compatible = "allwinner,sun4i-a10-spi"; | |
478 | reg = <0x01c05000 0x1000>; | |
479 | interrupts = <0 10 4>; | |
480 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
481 | clock-names = "ahb", "mod"; | |
ffec7210 EL |
482 | dmas = <&dma 1 27>, <&dma 1 26>; |
483 | dma-names = "rx", "tx"; | |
36ab3e73 MR |
484 | status = "disabled"; |
485 | #address-cells = <1>; | |
486 | #size-cells = <0>; | |
487 | }; | |
488 | ||
489 | spi1: spi@01c06000 { | |
490 | compatible = "allwinner,sun4i-a10-spi"; | |
491 | reg = <0x01c06000 0x1000>; | |
492 | interrupts = <0 11 4>; | |
493 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
494 | clock-names = "ahb", "mod"; | |
ffec7210 EL |
495 | dmas = <&dma 1 9>, <&dma 1 8>; |
496 | dma-names = "rx", "tx"; | |
36ab3e73 MR |
497 | status = "disabled"; |
498 | #address-cells = <1>; | |
499 | #size-cells = <0>; | |
500 | }; | |
501 | ||
2e804d03 | 502 | emac: ethernet@01c0b000 { |
1c70e099 | 503 | compatible = "allwinner,sun4i-a10-emac"; |
2e804d03 | 504 | reg = <0x01c0b000 0x1000>; |
378d0aee | 505 | interrupts = <0 55 4>; |
2e804d03 MR |
506 | clocks = <&ahb_gates 17>; |
507 | status = "disabled"; | |
508 | }; | |
509 | ||
510 | mdio@01c0b080 { | |
1c70e099 | 511 | compatible = "allwinner,sun4i-a10-mdio"; |
2e804d03 MR |
512 | reg = <0x01c0b080 0x14>; |
513 | status = "disabled"; | |
514 | #address-cells = <1>; | |
515 | #size-cells = <0>; | |
516 | }; | |
517 | ||
dd29ce53 HG |
518 | mmc0: mmc@01c0f000 { |
519 | compatible = "allwinner,sun5i-a13-mmc"; | |
520 | reg = <0x01c0f000 0x1000>; | |
521 | clocks = <&ahb_gates 8>, <&mmc0_clk>; | |
522 | clock-names = "ahb", "mmc"; | |
523 | interrupts = <0 32 4>; | |
524 | status = "disabled"; | |
525 | }; | |
526 | ||
527 | mmc1: mmc@01c10000 { | |
528 | compatible = "allwinner,sun5i-a13-mmc"; | |
529 | reg = <0x01c10000 0x1000>; | |
530 | clocks = <&ahb_gates 9>, <&mmc1_clk>; | |
531 | clock-names = "ahb", "mmc"; | |
532 | interrupts = <0 33 4>; | |
533 | status = "disabled"; | |
534 | }; | |
535 | ||
536 | mmc2: mmc@01c11000 { | |
537 | compatible = "allwinner,sun5i-a13-mmc"; | |
538 | reg = <0x01c11000 0x1000>; | |
539 | clocks = <&ahb_gates 10>, <&mmc2_clk>; | |
540 | clock-names = "ahb", "mmc"; | |
541 | interrupts = <0 34 4>; | |
542 | status = "disabled"; | |
543 | }; | |
544 | ||
545 | mmc3: mmc@01c12000 { | |
546 | compatible = "allwinner,sun5i-a13-mmc"; | |
547 | reg = <0x01c12000 0x1000>; | |
548 | clocks = <&ahb_gates 11>, <&mmc3_clk>; | |
549 | clock-names = "ahb", "mmc"; | |
550 | interrupts = <0 35 4>; | |
551 | status = "disabled"; | |
552 | }; | |
553 | ||
9debd0a2 RB |
554 | usbphy: phy@01c13400 { |
555 | #phy-cells = <1>; | |
556 | compatible = "allwinner,sun7i-a20-usb-phy"; | |
557 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
558 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
559 | clocks = <&usb_clk 8>; | |
560 | clock-names = "usb_phy"; | |
134c60ad RB |
561 | resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; |
562 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; | |
9debd0a2 RB |
563 | status = "disabled"; |
564 | }; | |
565 | ||
566 | ehci0: usb@01c14000 { | |
567 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | |
568 | reg = <0x01c14000 0x100>; | |
569 | interrupts = <0 39 4>; | |
570 | clocks = <&ahb_gates 1>; | |
571 | phys = <&usbphy 1>; | |
572 | phy-names = "usb"; | |
573 | status = "disabled"; | |
574 | }; | |
575 | ||
576 | ohci0: usb@01c14400 { | |
577 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | |
578 | reg = <0x01c14400 0x100>; | |
579 | interrupts = <0 64 4>; | |
580 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
581 | phys = <&usbphy 1>; | |
582 | phy-names = "usb"; | |
583 | status = "disabled"; | |
584 | }; | |
585 | ||
36ab3e73 MR |
586 | spi2: spi@01c17000 { |
587 | compatible = "allwinner,sun4i-a10-spi"; | |
588 | reg = <0x01c17000 0x1000>; | |
589 | interrupts = <0 12 4>; | |
590 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
591 | clock-names = "ahb", "mod"; | |
ffec7210 EL |
592 | dmas = <&dma 1 29>, <&dma 1 28>; |
593 | dma-names = "rx", "tx"; | |
36ab3e73 MR |
594 | status = "disabled"; |
595 | #address-cells = <1>; | |
596 | #size-cells = <0>; | |
597 | }; | |
598 | ||
902febf9 HG |
599 | ahci: sata@01c18000 { |
600 | compatible = "allwinner,sun4i-a10-ahci"; | |
601 | reg = <0x01c18000 0x1000>; | |
602 | interrupts = <0 56 4>; | |
603 | clocks = <&pll6 0>, <&ahb_gates 25>; | |
604 | status = "disabled"; | |
605 | }; | |
606 | ||
9debd0a2 RB |
607 | ehci1: usb@01c1c000 { |
608 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | |
609 | reg = <0x01c1c000 0x100>; | |
610 | interrupts = <0 40 4>; | |
611 | clocks = <&ahb_gates 3>; | |
612 | phys = <&usbphy 2>; | |
613 | phy-names = "usb"; | |
614 | status = "disabled"; | |
615 | }; | |
616 | ||
617 | ohci1: usb@01c1c400 { | |
618 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | |
619 | reg = <0x01c1c400 0x100>; | |
620 | interrupts = <0 65 4>; | |
621 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | |
622 | phys = <&usbphy 2>; | |
623 | phy-names = "usb"; | |
624 | status = "disabled"; | |
625 | }; | |
626 | ||
36ab3e73 MR |
627 | spi3: spi@01c1f000 { |
628 | compatible = "allwinner,sun4i-a10-spi"; | |
629 | reg = <0x01c1f000 0x1000>; | |
630 | interrupts = <0 50 4>; | |
631 | clocks = <&ahb_gates 23>, <&spi3_clk>; | |
632 | clock-names = "ahb", "mod"; | |
ffec7210 EL |
633 | dmas = <&dma 1 31>, <&dma 1 30>; |
634 | dma-names = "rx", "tx"; | |
36ab3e73 | 635 | status = "disabled"; |
2e804d03 MR |
636 | #address-cells = <1>; |
637 | #size-cells = <0>; | |
638 | }; | |
639 | ||
17eac031 MR |
640 | pio: pinctrl@01c20800 { |
641 | compatible = "allwinner,sun7i-a20-pinctrl"; | |
642 | reg = <0x01c20800 0x400>; | |
378d0aee | 643 | interrupts = <0 28 4>; |
de7dc935 | 644 | clocks = <&apb0_gates 5>; |
17eac031 MR |
645 | gpio-controller; |
646 | interrupt-controller; | |
7d4ff96d | 647 | #interrupt-cells = <2>; |
17eac031 MR |
648 | #size-cells = <0>; |
649 | #gpio-cells = <3>; | |
9f229ba9 | 650 | |
fd7898a2 AB |
651 | pwm0_pins_a: pwm0@0 { |
652 | allwinner,pins = "PB2"; | |
653 | allwinner,function = "pwm"; | |
654 | allwinner,drive = <0>; | |
655 | allwinner,pull = <0>; | |
656 | }; | |
657 | ||
658 | pwm1_pins_a: pwm1@0 { | |
659 | allwinner,pins = "PI3"; | |
660 | allwinner,function = "pwm"; | |
661 | allwinner,drive = <0>; | |
662 | allwinner,pull = <0>; | |
663 | }; | |
664 | ||
9f229ba9 MR |
665 | uart0_pins_a: uart0@0 { |
666 | allwinner,pins = "PB22", "PB23"; | |
667 | allwinner,function = "uart0"; | |
668 | allwinner,drive = <0>; | |
669 | allwinner,pull = <0>; | |
670 | }; | |
671 | ||
4261ec43 CYT |
672 | uart2_pins_a: uart2@0 { |
673 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | |
674 | allwinner,function = "uart2"; | |
675 | allwinner,drive = <0>; | |
676 | allwinner,pull = <0>; | |
677 | }; | |
678 | ||
7b5bace3 WW |
679 | uart3_pins_a: uart3@0 { |
680 | allwinner,pins = "PG6", "PG7", "PG8", "PG9"; | |
681 | allwinner,function = "uart3"; | |
682 | allwinner,drive = <0>; | |
683 | allwinner,pull = <0>; | |
684 | }; | |
685 | ||
0510e4b5 HG |
686 | uart3_pins_b: uart3@1 { |
687 | allwinner,pins = "PH0", "PH1"; | |
688 | allwinner,function = "uart3"; | |
689 | allwinner,drive = <0>; | |
690 | allwinner,pull = <0>; | |
691 | }; | |
692 | ||
7b5bace3 WW |
693 | uart4_pins_a: uart4@0 { |
694 | allwinner,pins = "PG10", "PG11"; | |
695 | allwinner,function = "uart4"; | |
696 | allwinner,drive = <0>; | |
697 | allwinner,pull = <0>; | |
698 | }; | |
699 | ||
700 | uart5_pins_a: uart5@0 { | |
701 | allwinner,pins = "PI10", "PI11"; | |
702 | allwinner,function = "uart5"; | |
703 | allwinner,drive = <0>; | |
704 | allwinner,pull = <0>; | |
705 | }; | |
706 | ||
9f229ba9 MR |
707 | uart6_pins_a: uart6@0 { |
708 | allwinner,pins = "PI12", "PI13"; | |
709 | allwinner,function = "uart6"; | |
710 | allwinner,drive = <0>; | |
711 | allwinner,pull = <0>; | |
712 | }; | |
713 | ||
714 | uart7_pins_a: uart7@0 { | |
715 | allwinner,pins = "PI20", "PI21"; | |
716 | allwinner,function = "uart7"; | |
717 | allwinner,drive = <0>; | |
718 | allwinner,pull = <0>; | |
719 | }; | |
756084c5 | 720 | |
e5496a31 MR |
721 | i2c0_pins_a: i2c0@0 { |
722 | allwinner,pins = "PB0", "PB1"; | |
723 | allwinner,function = "i2c0"; | |
724 | allwinner,drive = <0>; | |
725 | allwinner,pull = <0>; | |
726 | }; | |
727 | ||
728 | i2c1_pins_a: i2c1@0 { | |
729 | allwinner,pins = "PB18", "PB19"; | |
730 | allwinner,function = "i2c1"; | |
731 | allwinner,drive = <0>; | |
732 | allwinner,pull = <0>; | |
733 | }; | |
734 | ||
735 | i2c2_pins_a: i2c2@0 { | |
736 | allwinner,pins = "PB20", "PB21"; | |
737 | allwinner,function = "i2c2"; | |
738 | allwinner,drive = <0>; | |
739 | allwinner,pull = <0>; | |
740 | }; | |
741 | ||
7b5bace3 WW |
742 | i2c3_pins_a: i2c3@0 { |
743 | allwinner,pins = "PI0", "PI1"; | |
744 | allwinner,function = "i2c3"; | |
745 | allwinner,drive = <0>; | |
746 | allwinner,pull = <0>; | |
747 | }; | |
748 | ||
756084c5 MR |
749 | emac_pins_a: emac0@0 { |
750 | allwinner,pins = "PA0", "PA1", "PA2", | |
751 | "PA3", "PA4", "PA5", "PA6", | |
752 | "PA7", "PA8", "PA9", "PA10", | |
753 | "PA11", "PA12", "PA13", "PA14", | |
754 | "PA15", "PA16"; | |
755 | allwinner,function = "emac"; | |
756 | allwinner,drive = <0>; | |
757 | allwinner,pull = <0>; | |
758 | }; | |
f2e0759e CYT |
759 | |
760 | clk_out_a_pins_a: clk_out_a@0 { | |
761 | allwinner,pins = "PI12"; | |
762 | allwinner,function = "clk_out_a"; | |
763 | allwinner,drive = <0>; | |
764 | allwinner,pull = <0>; | |
765 | }; | |
766 | ||
767 | clk_out_b_pins_a: clk_out_b@0 { | |
768 | allwinner,pins = "PI13"; | |
769 | allwinner,function = "clk_out_b"; | |
770 | allwinner,drive = <0>; | |
771 | allwinner,pull = <0>; | |
772 | }; | |
129ccbcd CYT |
773 | |
774 | gmac_pins_mii_a: gmac_mii@0 { | |
775 | allwinner,pins = "PA0", "PA1", "PA2", | |
776 | "PA3", "PA4", "PA5", "PA6", | |
777 | "PA7", "PA8", "PA9", "PA10", | |
778 | "PA11", "PA12", "PA13", "PA14", | |
779 | "PA15", "PA16"; | |
780 | allwinner,function = "gmac"; | |
781 | allwinner,drive = <0>; | |
782 | allwinner,pull = <0>; | |
783 | }; | |
784 | ||
785 | gmac_pins_rgmii_a: gmac_rgmii@0 { | |
786 | allwinner,pins = "PA0", "PA1", "PA2", | |
787 | "PA3", "PA4", "PA5", "PA6", | |
788 | "PA7", "PA8", "PA10", | |
789 | "PA11", "PA12", "PA13", | |
790 | "PA15", "PA16"; | |
791 | allwinner,function = "gmac"; | |
792 | /* | |
793 | * data lines in RGMII mode use DDR mode | |
794 | * and need a higher signal drive strength | |
795 | */ | |
796 | allwinner,drive = <3>; | |
797 | allwinner,pull = <0>; | |
798 | }; | |
412f2c6f | 799 | |
2dad53b5 HG |
800 | spi0_pins_a: spi0@0 { |
801 | allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14"; | |
802 | allwinner,function = "spi0"; | |
803 | allwinner,drive = <0>; | |
804 | allwinner,pull = <0>; | |
805 | }; | |
806 | ||
412f2c6f MR |
807 | spi1_pins_a: spi1@0 { |
808 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | |
809 | allwinner,function = "spi1"; | |
810 | allwinner,drive = <0>; | |
811 | allwinner,pull = <0>; | |
812 | }; | |
813 | ||
814 | spi2_pins_a: spi2@0 { | |
815 | allwinner,pins = "PC19", "PC20", "PC21", "PC22"; | |
816 | allwinner,function = "spi2"; | |
817 | allwinner,drive = <0>; | |
818 | allwinner,pull = <0>; | |
7b5bace3 WW |
819 | }; |
820 | ||
821 | spi2_pins_b: spi2@1 { | |
822 | allwinner,pins = "PB14", "PB15", "PB16", "PB17"; | |
823 | allwinner,function = "spi2"; | |
824 | allwinner,drive = <0>; | |
825 | allwinner,pull = <0>; | |
412f2c6f | 826 | }; |
11fbedf4 HG |
827 | |
828 | mmc0_pins_a: mmc0@0 { | |
829 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | |
830 | allwinner,function = "mmc0"; | |
831 | allwinner,drive = <2>; | |
832 | allwinner,pull = <0>; | |
833 | }; | |
834 | ||
835 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | |
836 | allwinner,pins = "PH1"; | |
837 | allwinner,function = "gpio_in"; | |
838 | allwinner,drive = <0>; | |
839 | allwinner,pull = <1>; | |
840 | }; | |
841 | ||
8fa82326 HG |
842 | mmc2_pins_a: mmc2@0 { |
843 | allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11"; | |
844 | allwinner,function = "mmc2"; | |
845 | allwinner,drive = <2>; | |
846 | allwinner,pull = <1>; | |
847 | }; | |
848 | ||
11fbedf4 HG |
849 | mmc3_pins_a: mmc3@0 { |
850 | allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; | |
851 | allwinner,function = "mmc3"; | |
852 | allwinner,drive = <2>; | |
853 | allwinner,pull = <0>; | |
854 | }; | |
0fc2b7af AB |
855 | |
856 | ir0_pins_a: ir0@0 { | |
857 | allwinner,pins = "PB3","PB4"; | |
858 | allwinner,function = "ir0"; | |
859 | allwinner,drive = <0>; | |
860 | allwinner,pull = <0>; | |
861 | }; | |
862 | ||
863 | ir1_pins_a: ir1@0 { | |
864 | allwinner,pins = "PB22","PB23"; | |
865 | allwinner,function = "ir1"; | |
866 | allwinner,drive = <0>; | |
867 | allwinner,pull = <0>; | |
868 | }; | |
17eac031 MR |
869 | }; |
870 | ||
4790ecfa | 871 | timer@01c20c00 { |
b4f26440 | 872 | compatible = "allwinner,sun4i-a10-timer"; |
4790ecfa | 873 | reg = <0x01c20c00 0x90>; |
378d0aee MR |
874 | interrupts = <0 22 4>, |
875 | <0 23 4>, | |
876 | <0 24 4>, | |
877 | <0 25 4>, | |
878 | <0 67 4>, | |
879 | <0 68 4>; | |
4790ecfa MR |
880 | clocks = <&osc24M>; |
881 | }; | |
882 | ||
883 | wdt: watchdog@01c20c90 { | |
ca5d04d9 | 884 | compatible = "allwinner,sun4i-a10-wdt"; |
4790ecfa MR |
885 | reg = <0x01c20c90 0x10>; |
886 | }; | |
887 | ||
b5d905c7 CC |
888 | rtc: rtc@01c20d00 { |
889 | compatible = "allwinner,sun7i-a20-rtc"; | |
890 | reg = <0x01c20d00 0x20>; | |
2f418987 | 891 | interrupts = <0 24 4>; |
b5d905c7 CC |
892 | }; |
893 | ||
8ec40c25 AB |
894 | pwm: pwm@01c20e00 { |
895 | compatible = "allwinner,sun7i-a20-pwm"; | |
896 | reg = <0x01c20e00 0xc>; | |
897 | clocks = <&osc24M>; | |
898 | #pwm-cells = <3>; | |
899 | status = "disabled"; | |
900 | }; | |
901 | ||
c1a0ee3d | 902 | ir0: ir@01c21800 { |
1715a389 | 903 | compatible = "allwinner,sun4i-a10-ir"; |
c1a0ee3d AB |
904 | clocks = <&apb0_gates 6>, <&ir0_clk>; |
905 | clock-names = "apb", "ir"; | |
906 | interrupts = <0 5 4>; | |
907 | reg = <0x01c21800 0x40>; | |
908 | status = "disabled"; | |
909 | }; | |
910 | ||
911 | ir1: ir@01c21c00 { | |
1715a389 | 912 | compatible = "allwinner,sun4i-a10-ir"; |
c1a0ee3d AB |
913 | clocks = <&apb0_gates 7>, <&ir1_clk>; |
914 | clock-names = "apb", "ir"; | |
915 | interrupts = <0 6 4>; | |
916 | reg = <0x01c21c00 0x40>; | |
917 | status = "disabled"; | |
918 | }; | |
919 | ||
a6a2d644 HG |
920 | lradc: lradc@01c22800 { |
921 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
922 | reg = <0x01c22800 0x100>; | |
923 | interrupts = <0 31 4>; | |
924 | status = "disabled"; | |
925 | }; | |
926 | ||
2bad969f OS |
927 | sid: eeprom@01c23800 { |
928 | compatible = "allwinner,sun7i-a20-sid"; | |
929 | reg = <0x01c23800 0x200>; | |
930 | }; | |
931 | ||
00f7ed8d | 932 | rtp: rtp@01c25000 { |
40dd8f3b | 933 | compatible = "allwinner,sun4i-a10-ts"; |
00f7ed8d HG |
934 | reg = <0x01c25000 0x100>; |
935 | interrupts = <0 29 4>; | |
936 | }; | |
937 | ||
4790ecfa MR |
938 | uart0: serial@01c28000 { |
939 | compatible = "snps,dw-apb-uart"; | |
940 | reg = <0x01c28000 0x400>; | |
378d0aee | 941 | interrupts = <0 1 4>; |
4790ecfa MR |
942 | reg-shift = <2>; |
943 | reg-io-width = <4>; | |
de7dc935 | 944 | clocks = <&apb1_gates 16>; |
4790ecfa MR |
945 | status = "disabled"; |
946 | }; | |
947 | ||
948 | uart1: serial@01c28400 { | |
949 | compatible = "snps,dw-apb-uart"; | |
950 | reg = <0x01c28400 0x400>; | |
378d0aee | 951 | interrupts = <0 2 4>; |
4790ecfa MR |
952 | reg-shift = <2>; |
953 | reg-io-width = <4>; | |
de7dc935 | 954 | clocks = <&apb1_gates 17>; |
4790ecfa MR |
955 | status = "disabled"; |
956 | }; | |
957 | ||
958 | uart2: serial@01c28800 { | |
959 | compatible = "snps,dw-apb-uart"; | |
960 | reg = <0x01c28800 0x400>; | |
378d0aee | 961 | interrupts = <0 3 4>; |
4790ecfa MR |
962 | reg-shift = <2>; |
963 | reg-io-width = <4>; | |
de7dc935 | 964 | clocks = <&apb1_gates 18>; |
4790ecfa MR |
965 | status = "disabled"; |
966 | }; | |
967 | ||
968 | uart3: serial@01c28c00 { | |
969 | compatible = "snps,dw-apb-uart"; | |
970 | reg = <0x01c28c00 0x400>; | |
378d0aee | 971 | interrupts = <0 4 4>; |
4790ecfa MR |
972 | reg-shift = <2>; |
973 | reg-io-width = <4>; | |
de7dc935 | 974 | clocks = <&apb1_gates 19>; |
4790ecfa MR |
975 | status = "disabled"; |
976 | }; | |
977 | ||
978 | uart4: serial@01c29000 { | |
979 | compatible = "snps,dw-apb-uart"; | |
980 | reg = <0x01c29000 0x400>; | |
378d0aee | 981 | interrupts = <0 17 4>; |
4790ecfa MR |
982 | reg-shift = <2>; |
983 | reg-io-width = <4>; | |
de7dc935 | 984 | clocks = <&apb1_gates 20>; |
4790ecfa MR |
985 | status = "disabled"; |
986 | }; | |
987 | ||
988 | uart5: serial@01c29400 { | |
989 | compatible = "snps,dw-apb-uart"; | |
990 | reg = <0x01c29400 0x400>; | |
378d0aee | 991 | interrupts = <0 18 4>; |
4790ecfa MR |
992 | reg-shift = <2>; |
993 | reg-io-width = <4>; | |
de7dc935 | 994 | clocks = <&apb1_gates 21>; |
4790ecfa MR |
995 | status = "disabled"; |
996 | }; | |
997 | ||
998 | uart6: serial@01c29800 { | |
999 | compatible = "snps,dw-apb-uart"; | |
1000 | reg = <0x01c29800 0x400>; | |
378d0aee | 1001 | interrupts = <0 19 4>; |
4790ecfa MR |
1002 | reg-shift = <2>; |
1003 | reg-io-width = <4>; | |
de7dc935 | 1004 | clocks = <&apb1_gates 22>; |
4790ecfa MR |
1005 | status = "disabled"; |
1006 | }; | |
1007 | ||
1008 | uart7: serial@01c29c00 { | |
1009 | compatible = "snps,dw-apb-uart"; | |
1010 | reg = <0x01c29c00 0x400>; | |
378d0aee | 1011 | interrupts = <0 20 4>; |
4790ecfa MR |
1012 | reg-shift = <2>; |
1013 | reg-io-width = <4>; | |
de7dc935 | 1014 | clocks = <&apb1_gates 23>; |
4790ecfa MR |
1015 | status = "disabled"; |
1016 | }; | |
1017 | ||
428abbb8 | 1018 | i2c0: i2c@01c2ac00 { |
d275545e | 1019 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
428abbb8 | 1020 | reg = <0x01c2ac00 0x400>; |
378d0aee | 1021 | interrupts = <0 7 4>; |
428abbb8 | 1022 | clocks = <&apb1_gates 0>; |
428abbb8 | 1023 | status = "disabled"; |
d1412aed HG |
1024 | #address-cells = <1>; |
1025 | #size-cells = <0>; | |
428abbb8 MR |
1026 | }; |
1027 | ||
1028 | i2c1: i2c@01c2b000 { | |
d275545e | 1029 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
428abbb8 | 1030 | reg = <0x01c2b000 0x400>; |
378d0aee | 1031 | interrupts = <0 8 4>; |
428abbb8 | 1032 | clocks = <&apb1_gates 1>; |
428abbb8 | 1033 | status = "disabled"; |
d1412aed HG |
1034 | #address-cells = <1>; |
1035 | #size-cells = <0>; | |
428abbb8 MR |
1036 | }; |
1037 | ||
1038 | i2c2: i2c@01c2b400 { | |
d275545e | 1039 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
428abbb8 | 1040 | reg = <0x01c2b400 0x400>; |
378d0aee | 1041 | interrupts = <0 9 4>; |
428abbb8 | 1042 | clocks = <&apb1_gates 2>; |
428abbb8 | 1043 | status = "disabled"; |
d1412aed HG |
1044 | #address-cells = <1>; |
1045 | #size-cells = <0>; | |
428abbb8 MR |
1046 | }; |
1047 | ||
1048 | i2c3: i2c@01c2b800 { | |
d275545e | 1049 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
428abbb8 | 1050 | reg = <0x01c2b800 0x400>; |
378d0aee | 1051 | interrupts = <0 88 4>; |
428abbb8 | 1052 | clocks = <&apb1_gates 3>; |
428abbb8 | 1053 | status = "disabled"; |
d1412aed HG |
1054 | #address-cells = <1>; |
1055 | #size-cells = <0>; | |
428abbb8 MR |
1056 | }; |
1057 | ||
a3867045 | 1058 | i2c4: i2c@01c2c000 { |
d275545e | 1059 | compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; |
a3867045 | 1060 | reg = <0x01c2c000 0x400>; |
378d0aee | 1061 | interrupts = <0 89 4>; |
428abbb8 | 1062 | clocks = <&apb1_gates 15>; |
428abbb8 | 1063 | status = "disabled"; |
d1412aed HG |
1064 | #address-cells = <1>; |
1065 | #size-cells = <0>; | |
428abbb8 MR |
1066 | }; |
1067 | ||
c40b8d58 CYT |
1068 | gmac: ethernet@01c50000 { |
1069 | compatible = "allwinner,sun7i-a20-gmac"; | |
1070 | reg = <0x01c50000 0x10000>; | |
1071 | interrupts = <0 85 4>; | |
1072 | interrupt-names = "macirq"; | |
1073 | clocks = <&ahb_gates 49>, <&gmac_tx_clk>; | |
1074 | clock-names = "stmmaceth", "allwinner_gmac_tx"; | |
1075 | snps,pbl = <2>; | |
1076 | snps,fixed-burst; | |
1077 | snps,force_sf_dma_mode; | |
1078 | status = "disabled"; | |
1079 | #address-cells = <1>; | |
1080 | #size-cells = <0>; | |
1081 | }; | |
1082 | ||
31f8ad38 MR |
1083 | hstimer@01c60000 { |
1084 | compatible = "allwinner,sun7i-a20-hstimer"; | |
1085 | reg = <0x01c60000 0x1000>; | |
2f418987 MR |
1086 | interrupts = <0 81 4>, |
1087 | <0 82 4>, | |
1088 | <0 83 4>, | |
1089 | <0 84 4>; | |
31f8ad38 MR |
1090 | clocks = <&ahb_gates 28>; |
1091 | }; | |
1092 | ||
4790ecfa MR |
1093 | gic: interrupt-controller@01c81000 { |
1094 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
1095 | reg = <0x01c81000 0x1000>, | |
1096 | <0x01c82000 0x1000>, | |
1097 | <0x01c84000 0x2000>, | |
1098 | <0x01c86000 0x2000>; | |
1099 | interrupt-controller; | |
1100 | #interrupt-cells = <3>; | |
1101 | interrupts = <1 9 0xf04>; | |
1102 | }; | |
1103 | }; | |
1104 | }; |