Commit | Line | Data |
---|---|---|
4790ecfa MR |
1 | /* |
2 | * Copyright 2013 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
394c56ce MR |
6 | * This file is dual-licensed: you can use it either under the terms |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
4790ecfa | 10 | * |
5186d83a | 11 | * a) This file is free software; you can redistribute it and/or |
394c56ce MR |
12 | * modify it under the terms of the GNU General Public License as |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
5186d83a | 16 | * This file is distributed in the hope that it will be useful, |
394c56ce MR |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
394c56ce MR |
21 | * Or, alternatively, |
22 | * | |
23 | * b) Permission is hereby granted, free of charge, to any person | |
24 | * obtaining a copy of this software and associated documentation | |
25 | * files (the "Software"), to deal in the Software without | |
26 | * restriction, including without limitation the rights to use, | |
27 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
28 | * sell copies of the Software, and to permit persons to whom the | |
29 | * Software is furnished to do so, subject to the following | |
30 | * conditions: | |
31 | * | |
32 | * The above copyright notice and this permission notice shall be | |
33 | * included in all copies or substantial portions of the Software. | |
34 | * | |
35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
42 | * OTHER DEALINGS IN THE SOFTWARE. | |
4790ecfa MR |
43 | */ |
44 | ||
71455701 | 45 | #include "skeleton.dtsi" |
4790ecfa | 46 | |
19882b84 | 47 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
b6d34248 | 48 | #include <dt-bindings/thermal/thermal.h> |
19882b84 | 49 | |
1f9f6a78 | 50 | #include <dt-bindings/dma/sun4i-a10.h> |
092a0c3b | 51 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
4790ecfa MR |
52 | |
53 | / { | |
54 | interrupt-parent = <&gic>; | |
55 | ||
e751cce9 | 56 | aliases { |
18428f77 | 57 | ethernet0 = &gmac; |
e751cce9 EL |
58 | }; |
59 | ||
8efc5c2b HG |
60 | chosen { |
61 | #address-cells = <1>; | |
62 | #size-cells = <1>; | |
63 | ranges; | |
64 | ||
a9f8cda3 | 65 | framebuffer@0 { |
d8cacaa3 MR |
66 | compatible = "allwinner,simple-framebuffer", |
67 | "simple-framebuffer"; | |
a9f8cda3 | 68 | allwinner,pipeline = "de_be0-lcd0-hdmi"; |
678e75d3 HG |
69 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, |
70 | <&ahb_gates 44>; | |
8efc5c2b HG |
71 | status = "disabled"; |
72 | }; | |
fd18c7ea HG |
73 | |
74 | framebuffer@1 { | |
75 | compatible = "allwinner,simple-framebuffer", | |
76 | "simple-framebuffer"; | |
77 | allwinner,pipeline = "de_be0-lcd0"; | |
78 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>; | |
79 | status = "disabled"; | |
80 | }; | |
81 | ||
82 | framebuffer@2 { | |
83 | compatible = "allwinner,simple-framebuffer", | |
84 | "simple-framebuffer"; | |
85 | allwinner,pipeline = "de_be0-lcd0-tve0"; | |
86 | clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, | |
87 | <&ahb_gates 44>; | |
88 | status = "disabled"; | |
89 | }; | |
8efc5c2b HG |
90 | }; |
91 | ||
4790ecfa MR |
92 | cpus { |
93 | #address-cells = <1>; | |
94 | #size-cells = <0>; | |
95 | ||
d96b7161 | 96 | cpu0: cpu@0 { |
4790ecfa MR |
97 | compatible = "arm,cortex-a7"; |
98 | device_type = "cpu"; | |
99 | reg = <0>; | |
d96b7161 CYT |
100 | clocks = <&cpu>; |
101 | clock-latency = <244144>; /* 8 32k periods */ | |
102 | operating-points = < | |
8358aada MR |
103 | /* kHz uV */ |
104 | 960000 1400000 | |
105 | 912000 1400000 | |
106 | 864000 1300000 | |
107 | 720000 1200000 | |
108 | 528000 1100000 | |
109 | 312000 1000000 | |
110 | 144000 900000 | |
d96b7161 CYT |
111 | >; |
112 | #cooling-cells = <2>; | |
113 | cooling-min-level = <0>; | |
370a9b5f | 114 | cooling-max-level = <6>; |
4790ecfa MR |
115 | }; |
116 | ||
117 | cpu@1 { | |
118 | compatible = "arm,cortex-a7"; | |
119 | device_type = "cpu"; | |
120 | reg = <1>; | |
121 | }; | |
122 | }; | |
123 | ||
b6d34248 CYT |
124 | thermal-zones { |
125 | cpu_thermal { | |
126 | /* milliseconds */ | |
127 | polling-delay-passive = <250>; | |
128 | polling-delay = <1000>; | |
129 | thermal-sensors = <&rtp>; | |
130 | ||
131 | cooling-maps { | |
132 | map0 { | |
133 | trip = <&cpu_alert0>; | |
134 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
135 | }; | |
136 | }; | |
137 | ||
138 | trips { | |
139 | cpu_alert0: cpu_alert0 { | |
140 | /* milliCelsius */ | |
141 | temperature = <75000>; | |
142 | hysteresis = <2000>; | |
143 | type = "passive"; | |
144 | }; | |
145 | ||
146 | cpu_crit: cpu_crit { | |
147 | /* milliCelsius */ | |
148 | temperature = <100000>; | |
149 | hysteresis = <2000>; | |
150 | type = "critical"; | |
151 | }; | |
152 | }; | |
153 | }; | |
154 | }; | |
155 | ||
4790ecfa MR |
156 | memory { |
157 | reg = <0x40000000 0x80000000>; | |
158 | }; | |
159 | ||
7902763e MZ |
160 | timer { |
161 | compatible = "arm,armv7-timer"; | |
19882b84 MR |
162 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
163 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
164 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
165 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
7902763e MZ |
166 | }; |
167 | ||
e29ea4d3 MR |
168 | pmu { |
169 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; | |
19882b84 MR |
170 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
171 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; | |
e29ea4d3 MR |
172 | }; |
173 | ||
4790ecfa MR |
174 | clocks { |
175 | #address-cells = <1>; | |
176 | #size-cells = <1>; | |
177 | ranges; | |
178 | ||
06067a2f | 179 | osc24M: clk@01c20050 { |
4790ecfa | 180 | #clock-cells = <0>; |
bf6534a1 | 181 | compatible = "allwinner,sun4i-a10-osc-clk"; |
de7dc935 | 182 | reg = <0x01c20050 0x4>; |
4790ecfa | 183 | clock-frequency = <24000000>; |
06067a2f | 184 | clock-output-names = "osc24M"; |
4790ecfa MR |
185 | }; |
186 | ||
673fac74 | 187 | osc32k: clk@0 { |
4790ecfa MR |
188 | #clock-cells = <0>; |
189 | compatible = "fixed-clock"; | |
190 | clock-frequency = <32768>; | |
673fac74 | 191 | clock-output-names = "osc32k"; |
4790ecfa | 192 | }; |
de7dc935 | 193 | |
06067a2f | 194 | pll1: clk@01c20000 { |
de7dc935 | 195 | #clock-cells = <0>; |
bf6534a1 | 196 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
de7dc935 MR |
197 | reg = <0x01c20000 0x4>; |
198 | clocks = <&osc24M>; | |
06067a2f | 199 | clock-output-names = "pll1"; |
de7dc935 MR |
200 | }; |
201 | ||
06067a2f | 202 | pll4: clk@01c20018 { |
de7dc935 | 203 | #clock-cells = <0>; |
04ebcb54 | 204 | compatible = "allwinner,sun7i-a20-pll4-clk"; |
ec5589f7 EL |
205 | reg = <0x01c20018 0x4>; |
206 | clocks = <&osc24M>; | |
06067a2f | 207 | clock-output-names = "pll4"; |
ec5589f7 EL |
208 | }; |
209 | ||
06067a2f | 210 | pll5: clk@01c20020 { |
c3e5e66b | 211 | #clock-cells = <1>; |
bf6534a1 | 212 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
c3e5e66b EL |
213 | reg = <0x01c20020 0x4>; |
214 | clocks = <&osc24M>; | |
215 | clock-output-names = "pll5_ddr", "pll5_other"; | |
216 | }; | |
217 | ||
06067a2f | 218 | pll6: clk@01c20028 { |
c3e5e66b | 219 | #clock-cells = <1>; |
bf6534a1 | 220 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
c3e5e66b EL |
221 | reg = <0x01c20028 0x4>; |
222 | clocks = <&osc24M>; | |
2186df37 CYT |
223 | clock-output-names = "pll6_sata", "pll6_other", "pll6", |
224 | "pll6_div_4"; | |
de7dc935 MR |
225 | }; |
226 | ||
04ebcb54 EL |
227 | pll8: clk@01c20040 { |
228 | #clock-cells = <0>; | |
229 | compatible = "allwinner,sun7i-a20-pll4-clk"; | |
230 | reg = <0x01c20040 0x4>; | |
231 | clocks = <&osc24M>; | |
232 | clock-output-names = "pll8"; | |
233 | }; | |
234 | ||
de7dc935 MR |
235 | cpu: cpu@01c20054 { |
236 | #clock-cells = <0>; | |
bf6534a1 | 237 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
de7dc935 | 238 | reg = <0x01c20054 0x4>; |
c3e5e66b | 239 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; |
06067a2f | 240 | clock-output-names = "cpu"; |
de7dc935 MR |
241 | }; |
242 | ||
243 | axi: axi@01c20054 { | |
244 | #clock-cells = <0>; | |
bf6534a1 | 245 | compatible = "allwinner,sun4i-a10-axi-clk"; |
de7dc935 MR |
246 | reg = <0x01c20054 0x4>; |
247 | clocks = <&cpu>; | |
06067a2f | 248 | clock-output-names = "axi"; |
de7dc935 MR |
249 | }; |
250 | ||
251 | ahb: ahb@01c20054 { | |
252 | #clock-cells = <0>; | |
2186df37 | 253 | compatible = "allwinner,sun5i-a13-ahb-clk"; |
de7dc935 | 254 | reg = <0x01c20054 0x4>; |
2186df37 | 255 | clocks = <&axi>, <&pll6 3>, <&pll6 1>; |
06067a2f | 256 | clock-output-names = "ahb"; |
2186df37 CYT |
257 | /* |
258 | * Use PLL6 as parent, instead of CPU/AXI | |
259 | * which has rate changes due to cpufreq | |
260 | */ | |
261 | assigned-clocks = <&ahb>; | |
262 | assigned-clock-parents = <&pll6 3>; | |
de7dc935 MR |
263 | }; |
264 | ||
06067a2f | 265 | ahb_gates: clk@01c20060 { |
de7dc935 MR |
266 | #clock-cells = <1>; |
267 | compatible = "allwinner,sun7i-a20-ahb-gates-clk"; | |
268 | reg = <0x01c20060 0x8>; | |
269 | clocks = <&ahb>; | |
270 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
271 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", | |
272 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
273 | "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", | |
274 | "ahb_nand", "ahb_sdram", "ahb_ace", | |
275 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", | |
276 | "ahb_spi2", "ahb_spi3", "ahb_sata", | |
277 | "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", | |
278 | "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", | |
279 | "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", | |
280 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
281 | "ahb_de_fe1", "ahb_gmac", "ahb_mp", | |
282 | "ahb_mali"; | |
283 | }; | |
284 | ||
285 | apb0: apb0@01c20054 { | |
286 | #clock-cells = <0>; | |
bf6534a1 | 287 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
de7dc935 MR |
288 | reg = <0x01c20054 0x4>; |
289 | clocks = <&ahb>; | |
06067a2f | 290 | clock-output-names = "apb0"; |
de7dc935 MR |
291 | }; |
292 | ||
06067a2f | 293 | apb0_gates: clk@01c20068 { |
de7dc935 MR |
294 | #clock-cells = <1>; |
295 | compatible = "allwinner,sun7i-a20-apb0-gates-clk"; | |
296 | reg = <0x01c20068 0x4>; | |
297 | clocks = <&apb0>; | |
298 | clock-output-names = "apb0_codec", "apb0_spdif", | |
299 | "apb0_ac97", "apb0_iis0", "apb0_iis1", | |
300 | "apb0_pio", "apb0_ir0", "apb0_ir1", | |
301 | "apb0_iis2", "apb0_keypad"; | |
302 | }; | |
303 | ||
acbcc0f0 | 304 | apb1: clk@01c20058 { |
de7dc935 | 305 | #clock-cells = <0>; |
bf6534a1 | 306 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
de7dc935 | 307 | reg = <0x01c20058 0x4>; |
acbcc0f0 | 308 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
06067a2f | 309 | clock-output-names = "apb1"; |
de7dc935 MR |
310 | }; |
311 | ||
06067a2f | 312 | apb1_gates: clk@01c2006c { |
de7dc935 MR |
313 | #clock-cells = <1>; |
314 | compatible = "allwinner,sun7i-a20-apb1-gates-clk"; | |
315 | reg = <0x01c2006c 0x4>; | |
316 | clocks = <&apb1>; | |
317 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
318 | "apb1_i2c2", "apb1_i2c3", "apb1_can", | |
319 | "apb1_scr", "apb1_ps20", "apb1_ps21", | |
320 | "apb1_i2c4", "apb1_uart0", "apb1_uart1", | |
321 | "apb1_uart2", "apb1_uart3", "apb1_uart4", | |
322 | "apb1_uart5", "apb1_uart6", "apb1_uart7"; | |
323 | }; | |
1c92b95b EL |
324 | |
325 | nand_clk: clk@01c20080 { | |
326 | #clock-cells = <0>; | |
bf6534a1 | 327 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
328 | reg = <0x01c20080 0x4>; |
329 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
330 | clock-output-names = "nand"; | |
331 | }; | |
332 | ||
333 | ms_clk: clk@01c20084 { | |
334 | #clock-cells = <0>; | |
bf6534a1 | 335 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
336 | reg = <0x01c20084 0x4>; |
337 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
338 | clock-output-names = "ms"; | |
339 | }; | |
340 | ||
341 | mmc0_clk: clk@01c20088 { | |
d8c3a392 MR |
342 | #clock-cells = <1>; |
343 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
1c92b95b EL |
344 | reg = <0x01c20088 0x4>; |
345 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
346 | clock-output-names = "mmc0", |
347 | "mmc0_output", | |
348 | "mmc0_sample"; | |
1c92b95b EL |
349 | }; |
350 | ||
351 | mmc1_clk: clk@01c2008c { | |
d8c3a392 MR |
352 | #clock-cells = <1>; |
353 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
1c92b95b EL |
354 | reg = <0x01c2008c 0x4>; |
355 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
356 | clock-output-names = "mmc1", |
357 | "mmc1_output", | |
358 | "mmc1_sample"; | |
1c92b95b EL |
359 | }; |
360 | ||
361 | mmc2_clk: clk@01c20090 { | |
d8c3a392 MR |
362 | #clock-cells = <1>; |
363 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
1c92b95b EL |
364 | reg = <0x01c20090 0x4>; |
365 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
366 | clock-output-names = "mmc2", |
367 | "mmc2_output", | |
368 | "mmc2_sample"; | |
1c92b95b EL |
369 | }; |
370 | ||
371 | mmc3_clk: clk@01c20094 { | |
d8c3a392 MR |
372 | #clock-cells = <1>; |
373 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
1c92b95b EL |
374 | reg = <0x01c20094 0x4>; |
375 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
376 | clock-output-names = "mmc3", |
377 | "mmc3_output", | |
378 | "mmc3_sample"; | |
1c92b95b EL |
379 | }; |
380 | ||
381 | ts_clk: clk@01c20098 { | |
382 | #clock-cells = <0>; | |
bf6534a1 | 383 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
384 | reg = <0x01c20098 0x4>; |
385 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
386 | clock-output-names = "ts"; | |
387 | }; | |
388 | ||
389 | ss_clk: clk@01c2009c { | |
390 | #clock-cells = <0>; | |
bf6534a1 | 391 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
392 | reg = <0x01c2009c 0x4>; |
393 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
394 | clock-output-names = "ss"; | |
395 | }; | |
396 | ||
397 | spi0_clk: clk@01c200a0 { | |
398 | #clock-cells = <0>; | |
bf6534a1 | 399 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
400 | reg = <0x01c200a0 0x4>; |
401 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
402 | clock-output-names = "spi0"; | |
403 | }; | |
404 | ||
405 | spi1_clk: clk@01c200a4 { | |
406 | #clock-cells = <0>; | |
bf6534a1 | 407 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
408 | reg = <0x01c200a4 0x4>; |
409 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
410 | clock-output-names = "spi1"; | |
411 | }; | |
412 | ||
413 | spi2_clk: clk@01c200a8 { | |
414 | #clock-cells = <0>; | |
bf6534a1 | 415 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
416 | reg = <0x01c200a8 0x4>; |
417 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
418 | clock-output-names = "spi2"; | |
419 | }; | |
420 | ||
421 | pata_clk: clk@01c200ac { | |
422 | #clock-cells = <0>; | |
bf6534a1 | 423 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
424 | reg = <0x01c200ac 0x4>; |
425 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
426 | clock-output-names = "pata"; | |
427 | }; | |
428 | ||
429 | ir0_clk: clk@01c200b0 { | |
430 | #clock-cells = <0>; | |
bf6534a1 | 431 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
432 | reg = <0x01c200b0 0x4>; |
433 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
434 | clock-output-names = "ir0"; | |
435 | }; | |
436 | ||
437 | ir1_clk: clk@01c200b4 { | |
438 | #clock-cells = <0>; | |
bf6534a1 | 439 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
440 | reg = <0x01c200b4 0x4>; |
441 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
442 | clock-output-names = "ir1"; | |
443 | }; | |
444 | ||
434e41b3 RB |
445 | usb_clk: clk@01c200cc { |
446 | #clock-cells = <1>; | |
8358aada | 447 | #reset-cells = <1>; |
434e41b3 RB |
448 | compatible = "allwinner,sun4i-a10-usb-clk"; |
449 | reg = <0x01c200cc 0x4>; | |
450 | clocks = <&pll6 1>; | |
d8cacaa3 MR |
451 | clock-output-names = "usb_ohci0", "usb_ohci1", |
452 | "usb_phy"; | |
434e41b3 RB |
453 | }; |
454 | ||
1c92b95b EL |
455 | spi3_clk: clk@01c200d4 { |
456 | #clock-cells = <0>; | |
bf6534a1 | 457 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
1c92b95b EL |
458 | reg = <0x01c200d4 0x4>; |
459 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
460 | clock-output-names = "spi3"; | |
461 | }; | |
118c07ae EL |
462 | |
463 | mbus_clk: clk@01c2015c { | |
464 | #clock-cells = <0>; | |
7868c5eb | 465 | compatible = "allwinner,sun5i-a13-mbus-clk"; |
118c07ae EL |
466 | reg = <0x01c2015c 0x4>; |
467 | clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; | |
468 | clock-output-names = "mbus"; | |
469 | }; | |
0aff0370 | 470 | |
daed5a81 | 471 | /* |
d8cacaa3 MR |
472 | * The following two are dummy clocks, placeholders |
473 | * used in the gmac_tx clock. The gmac driver will | |
474 | * choose one parent depending on the PHY interface | |
475 | * mode, using clk_set_rate auto-reparenting. | |
476 | * | |
477 | * The actual TX clock rate is not controlled by the | |
478 | * gmac_tx clock. | |
daed5a81 CYT |
479 | */ |
480 | mii_phy_tx_clk: clk@2 { | |
481 | #clock-cells = <0>; | |
482 | compatible = "fixed-clock"; | |
483 | clock-frequency = <25000000>; | |
484 | clock-output-names = "mii_phy_tx"; | |
485 | }; | |
486 | ||
487 | gmac_int_tx_clk: clk@3 { | |
488 | #clock-cells = <0>; | |
489 | compatible = "fixed-clock"; | |
490 | clock-frequency = <125000000>; | |
491 | clock-output-names = "gmac_int_tx"; | |
492 | }; | |
493 | ||
494 | gmac_tx_clk: clk@01c20164 { | |
495 | #clock-cells = <0>; | |
496 | compatible = "allwinner,sun7i-a20-gmac-clk"; | |
497 | reg = <0x01c20164 0x4>; | |
498 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | |
499 | clock-output-names = "gmac_tx"; | |
500 | }; | |
501 | ||
0aff0370 CYT |
502 | /* |
503 | * Dummy clock used by output clocks | |
504 | */ | |
505 | osc24M_32k: clk@1 { | |
506 | #clock-cells = <0>; | |
507 | compatible = "fixed-factor-clock"; | |
508 | clock-div = <750>; | |
509 | clock-mult = <1>; | |
510 | clocks = <&osc24M>; | |
511 | clock-output-names = "osc24M_32k"; | |
512 | }; | |
513 | ||
514 | clk_out_a: clk@01c201f0 { | |
515 | #clock-cells = <0>; | |
516 | compatible = "allwinner,sun7i-a20-out-clk"; | |
517 | reg = <0x01c201f0 0x4>; | |
518 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
519 | clock-output-names = "clk_out_a"; | |
520 | }; | |
521 | ||
522 | clk_out_b: clk@01c201f4 { | |
523 | #clock-cells = <0>; | |
524 | compatible = "allwinner,sun7i-a20-out-clk"; | |
525 | reg = <0x01c201f4 0x4>; | |
526 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
527 | clock-output-names = "clk_out_b"; | |
528 | }; | |
4790ecfa MR |
529 | }; |
530 | ||
ccb4ada2 MR |
531 | /* |
532 | * Note we use the address where the mmio registers start, not where | |
533 | * the SRAM blocks start, this cannot be changed because that would be | |
534 | * a devicetree ABI change. | |
535 | */ | |
4790ecfa MR |
536 | soc@01c00000 { |
537 | compatible = "simple-bus"; | |
538 | #address-cells = <1>; | |
539 | #size-cells = <1>; | |
540 | ranges; | |
541 | ||
ccb4ada2 MR |
542 | sram@00000000 { |
543 | compatible = "allwinner,sun4i-a10-sram"; | |
544 | reg = <0x00000000 0x4000>; | |
545 | allwinner,sram-name = "A1"; | |
546 | }; | |
547 | ||
548 | sram@00004000 { | |
549 | compatible = "allwinner,sun4i-a10-sram"; | |
550 | reg = <0x00004000 0x4000>; | |
551 | allwinner,sram-name = "A2"; | |
552 | }; | |
553 | ||
554 | sram@00008000 { | |
555 | compatible = "allwinner,sun4i-a10-sram"; | |
556 | reg = <0x00008000 0x4000>; | |
557 | allwinner,sram-name = "A3-A4"; | |
558 | }; | |
559 | ||
560 | sram@00010000 { | |
561 | compatible = "allwinner,sun4i-a10-sram"; | |
562 | reg = <0x00010000 0x1000>; | |
563 | allwinner,sram-name = "D"; | |
564 | }; | |
565 | ||
566 | sram-controller@01c00000 { | |
567 | compatible = "allwinner,sun4i-a10-sram-controller"; | |
568 | reg = <0x01c00000 0x30>; | |
569 | }; | |
570 | ||
8ff973a2 CC |
571 | nmi_intc: interrupt-controller@01c00030 { |
572 | compatible = "allwinner,sun7i-a20-sc-nmi"; | |
573 | interrupt-controller; | |
574 | #interrupt-cells = <2>; | |
575 | reg = <0x01c00030 0x0c>; | |
19882b84 | 576 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
8ff973a2 CC |
577 | }; |
578 | ||
316e0b0e EL |
579 | dma: dma-controller@01c02000 { |
580 | compatible = "allwinner,sun4i-a10-dma"; | |
581 | reg = <0x01c02000 0x1000>; | |
19882b84 | 582 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
316e0b0e EL |
583 | clocks = <&ahb_gates 6>; |
584 | #dma-cells = <2>; | |
585 | }; | |
586 | ||
36ab3e73 MR |
587 | spi0: spi@01c05000 { |
588 | compatible = "allwinner,sun4i-a10-spi"; | |
589 | reg = <0x01c05000 0x1000>; | |
19882b84 | 590 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
36ab3e73 MR |
591 | clocks = <&ahb_gates 20>, <&spi0_clk>; |
592 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
593 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, |
594 | <&dma SUN4I_DMA_DEDICATED 26>; | |
ffec7210 | 595 | dma-names = "rx", "tx"; |
36ab3e73 MR |
596 | status = "disabled"; |
597 | #address-cells = <1>; | |
598 | #size-cells = <0>; | |
599 | }; | |
600 | ||
601 | spi1: spi@01c06000 { | |
602 | compatible = "allwinner,sun4i-a10-spi"; | |
603 | reg = <0x01c06000 0x1000>; | |
19882b84 | 604 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
36ab3e73 MR |
605 | clocks = <&ahb_gates 21>, <&spi1_clk>; |
606 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
607 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, |
608 | <&dma SUN4I_DMA_DEDICATED 8>; | |
ffec7210 | 609 | dma-names = "rx", "tx"; |
36ab3e73 MR |
610 | status = "disabled"; |
611 | #address-cells = <1>; | |
612 | #size-cells = <0>; | |
613 | }; | |
614 | ||
2e804d03 | 615 | emac: ethernet@01c0b000 { |
1c70e099 | 616 | compatible = "allwinner,sun4i-a10-emac"; |
2e804d03 | 617 | reg = <0x01c0b000 0x1000>; |
19882b84 | 618 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
2e804d03 MR |
619 | clocks = <&ahb_gates 17>; |
620 | status = "disabled"; | |
621 | }; | |
622 | ||
92395f56 | 623 | mdio: mdio@01c0b080 { |
1c70e099 | 624 | compatible = "allwinner,sun4i-a10-mdio"; |
2e804d03 MR |
625 | reg = <0x01c0b080 0x14>; |
626 | status = "disabled"; | |
627 | #address-cells = <1>; | |
628 | #size-cells = <0>; | |
629 | }; | |
630 | ||
dd29ce53 HG |
631 | mmc0: mmc@01c0f000 { |
632 | compatible = "allwinner,sun5i-a13-mmc"; | |
633 | reg = <0x01c0f000 0x1000>; | |
d8c3a392 MR |
634 | clocks = <&ahb_gates 8>, |
635 | <&mmc0_clk 0>, | |
636 | <&mmc0_clk 1>, | |
637 | <&mmc0_clk 2>; | |
638 | clock-names = "ahb", | |
639 | "mmc", | |
640 | "output", | |
641 | "sample"; | |
19882b84 | 642 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
dd29ce53 | 643 | status = "disabled"; |
4c1bb9c3 HG |
644 | #address-cells = <1>; |
645 | #size-cells = <0>; | |
dd29ce53 HG |
646 | }; |
647 | ||
648 | mmc1: mmc@01c10000 { | |
649 | compatible = "allwinner,sun5i-a13-mmc"; | |
650 | reg = <0x01c10000 0x1000>; | |
d8c3a392 MR |
651 | clocks = <&ahb_gates 9>, |
652 | <&mmc1_clk 0>, | |
653 | <&mmc1_clk 1>, | |
654 | <&mmc1_clk 2>; | |
655 | clock-names = "ahb", | |
656 | "mmc", | |
657 | "output", | |
658 | "sample"; | |
19882b84 | 659 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
dd29ce53 | 660 | status = "disabled"; |
4c1bb9c3 HG |
661 | #address-cells = <1>; |
662 | #size-cells = <0>; | |
dd29ce53 HG |
663 | }; |
664 | ||
665 | mmc2: mmc@01c11000 { | |
666 | compatible = "allwinner,sun5i-a13-mmc"; | |
667 | reg = <0x01c11000 0x1000>; | |
d8c3a392 MR |
668 | clocks = <&ahb_gates 10>, |
669 | <&mmc2_clk 0>, | |
670 | <&mmc2_clk 1>, | |
671 | <&mmc2_clk 2>; | |
672 | clock-names = "ahb", | |
673 | "mmc", | |
674 | "output", | |
675 | "sample"; | |
19882b84 | 676 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
dd29ce53 | 677 | status = "disabled"; |
4c1bb9c3 HG |
678 | #address-cells = <1>; |
679 | #size-cells = <0>; | |
dd29ce53 HG |
680 | }; |
681 | ||
682 | mmc3: mmc@01c12000 { | |
683 | compatible = "allwinner,sun5i-a13-mmc"; | |
684 | reg = <0x01c12000 0x1000>; | |
d8c3a392 MR |
685 | clocks = <&ahb_gates 11>, |
686 | <&mmc3_clk 0>, | |
687 | <&mmc3_clk 1>, | |
688 | <&mmc3_clk 2>; | |
689 | clock-names = "ahb", | |
690 | "mmc", | |
691 | "output", | |
692 | "sample"; | |
19882b84 | 693 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
dd29ce53 | 694 | status = "disabled"; |
4c1bb9c3 HG |
695 | #address-cells = <1>; |
696 | #size-cells = <0>; | |
dd29ce53 HG |
697 | }; |
698 | ||
9debd0a2 RB |
699 | usbphy: phy@01c13400 { |
700 | #phy-cells = <1>; | |
701 | compatible = "allwinner,sun7i-a20-usb-phy"; | |
702 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
703 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
704 | clocks = <&usb_clk 8>; | |
705 | clock-names = "usb_phy"; | |
134c60ad RB |
706 | resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; |
707 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; | |
9debd0a2 RB |
708 | status = "disabled"; |
709 | }; | |
710 | ||
711 | ehci0: usb@01c14000 { | |
712 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | |
713 | reg = <0x01c14000 0x100>; | |
19882b84 | 714 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
9debd0a2 RB |
715 | clocks = <&ahb_gates 1>; |
716 | phys = <&usbphy 1>; | |
717 | phy-names = "usb"; | |
718 | status = "disabled"; | |
719 | }; | |
720 | ||
721 | ohci0: usb@01c14400 { | |
722 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | |
723 | reg = <0x01c14400 0x100>; | |
19882b84 | 724 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
9debd0a2 RB |
725 | clocks = <&usb_clk 6>, <&ahb_gates 2>; |
726 | phys = <&usbphy 1>; | |
727 | phy-names = "usb"; | |
728 | status = "disabled"; | |
729 | }; | |
730 | ||
36ab3e73 MR |
731 | spi2: spi@01c17000 { |
732 | compatible = "allwinner,sun4i-a10-spi"; | |
733 | reg = <0x01c17000 0x1000>; | |
19882b84 | 734 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
36ab3e73 MR |
735 | clocks = <&ahb_gates 22>, <&spi2_clk>; |
736 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
737 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, |
738 | <&dma SUN4I_DMA_DEDICATED 28>; | |
ffec7210 | 739 | dma-names = "rx", "tx"; |
36ab3e73 MR |
740 | status = "disabled"; |
741 | #address-cells = <1>; | |
742 | #size-cells = <0>; | |
743 | }; | |
744 | ||
902febf9 HG |
745 | ahci: sata@01c18000 { |
746 | compatible = "allwinner,sun4i-a10-ahci"; | |
747 | reg = <0x01c18000 0x1000>; | |
19882b84 | 748 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
902febf9 HG |
749 | clocks = <&pll6 0>, <&ahb_gates 25>; |
750 | status = "disabled"; | |
751 | }; | |
752 | ||
9debd0a2 RB |
753 | ehci1: usb@01c1c000 { |
754 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | |
755 | reg = <0x01c1c000 0x100>; | |
19882b84 | 756 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
9debd0a2 RB |
757 | clocks = <&ahb_gates 3>; |
758 | phys = <&usbphy 2>; | |
759 | phy-names = "usb"; | |
760 | status = "disabled"; | |
761 | }; | |
762 | ||
763 | ohci1: usb@01c1c400 { | |
764 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | |
765 | reg = <0x01c1c400 0x100>; | |
19882b84 | 766 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
9debd0a2 RB |
767 | clocks = <&usb_clk 7>, <&ahb_gates 4>; |
768 | phys = <&usbphy 2>; | |
769 | phy-names = "usb"; | |
770 | status = "disabled"; | |
771 | }; | |
772 | ||
36ab3e73 MR |
773 | spi3: spi@01c1f000 { |
774 | compatible = "allwinner,sun4i-a10-spi"; | |
775 | reg = <0x01c1f000 0x1000>; | |
19882b84 | 776 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
36ab3e73 MR |
777 | clocks = <&ahb_gates 23>, <&spi3_clk>; |
778 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
779 | dmas = <&dma SUN4I_DMA_DEDICATED 31>, |
780 | <&dma SUN4I_DMA_DEDICATED 30>; | |
ffec7210 | 781 | dma-names = "rx", "tx"; |
36ab3e73 | 782 | status = "disabled"; |
2e804d03 MR |
783 | #address-cells = <1>; |
784 | #size-cells = <0>; | |
785 | }; | |
786 | ||
17eac031 MR |
787 | pio: pinctrl@01c20800 { |
788 | compatible = "allwinner,sun7i-a20-pinctrl"; | |
789 | reg = <0x01c20800 0x400>; | |
19882b84 | 790 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
de7dc935 | 791 | clocks = <&apb0_gates 5>; |
17eac031 MR |
792 | gpio-controller; |
793 | interrupt-controller; | |
7d4ff96d | 794 | #interrupt-cells = <2>; |
17eac031 MR |
795 | #size-cells = <0>; |
796 | #gpio-cells = <3>; | |
9f229ba9 | 797 | |
fd7898a2 AB |
798 | pwm0_pins_a: pwm0@0 { |
799 | allwinner,pins = "PB2"; | |
800 | allwinner,function = "pwm"; | |
092a0c3b MR |
801 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
802 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
fd7898a2 AB |
803 | }; |
804 | ||
805 | pwm1_pins_a: pwm1@0 { | |
806 | allwinner,pins = "PI3"; | |
807 | allwinner,function = "pwm"; | |
092a0c3b MR |
808 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
809 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
fd7898a2 AB |
810 | }; |
811 | ||
9f229ba9 MR |
812 | uart0_pins_a: uart0@0 { |
813 | allwinner,pins = "PB22", "PB23"; | |
814 | allwinner,function = "uart0"; | |
092a0c3b MR |
815 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
816 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
9f229ba9 MR |
817 | }; |
818 | ||
4261ec43 CYT |
819 | uart2_pins_a: uart2@0 { |
820 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | |
821 | allwinner,function = "uart2"; | |
092a0c3b MR |
822 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
823 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
4261ec43 CYT |
824 | }; |
825 | ||
7b5bace3 WW |
826 | uart3_pins_a: uart3@0 { |
827 | allwinner,pins = "PG6", "PG7", "PG8", "PG9"; | |
828 | allwinner,function = "uart3"; | |
092a0c3b MR |
829 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
830 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
7b5bace3 WW |
831 | }; |
832 | ||
0510e4b5 HG |
833 | uart3_pins_b: uart3@1 { |
834 | allwinner,pins = "PH0", "PH1"; | |
835 | allwinner,function = "uart3"; | |
092a0c3b MR |
836 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
837 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
0510e4b5 HG |
838 | }; |
839 | ||
7b5bace3 WW |
840 | uart4_pins_a: uart4@0 { |
841 | allwinner,pins = "PG10", "PG11"; | |
842 | allwinner,function = "uart4"; | |
092a0c3b MR |
843 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
844 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
7b5bace3 WW |
845 | }; |
846 | ||
847 | uart5_pins_a: uart5@0 { | |
848 | allwinner,pins = "PI10", "PI11"; | |
849 | allwinner,function = "uart5"; | |
092a0c3b MR |
850 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
851 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
7b5bace3 WW |
852 | }; |
853 | ||
9f229ba9 MR |
854 | uart6_pins_a: uart6@0 { |
855 | allwinner,pins = "PI12", "PI13"; | |
856 | allwinner,function = "uart6"; | |
092a0c3b MR |
857 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
858 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
9f229ba9 MR |
859 | }; |
860 | ||
861 | uart7_pins_a: uart7@0 { | |
862 | allwinner,pins = "PI20", "PI21"; | |
863 | allwinner,function = "uart7"; | |
092a0c3b MR |
864 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
865 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
9f229ba9 | 866 | }; |
756084c5 | 867 | |
e5496a31 MR |
868 | i2c0_pins_a: i2c0@0 { |
869 | allwinner,pins = "PB0", "PB1"; | |
870 | allwinner,function = "i2c0"; | |
092a0c3b MR |
871 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
872 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
e5496a31 MR |
873 | }; |
874 | ||
875 | i2c1_pins_a: i2c1@0 { | |
876 | allwinner,pins = "PB18", "PB19"; | |
877 | allwinner,function = "i2c1"; | |
092a0c3b MR |
878 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
879 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
e5496a31 MR |
880 | }; |
881 | ||
882 | i2c2_pins_a: i2c2@0 { | |
883 | allwinner,pins = "PB20", "PB21"; | |
884 | allwinner,function = "i2c2"; | |
092a0c3b MR |
885 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
886 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
e5496a31 MR |
887 | }; |
888 | ||
7b5bace3 WW |
889 | i2c3_pins_a: i2c3@0 { |
890 | allwinner,pins = "PI0", "PI1"; | |
891 | allwinner,function = "i2c3"; | |
092a0c3b MR |
892 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
893 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
7b5bace3 WW |
894 | }; |
895 | ||
756084c5 MR |
896 | emac_pins_a: emac0@0 { |
897 | allwinner,pins = "PA0", "PA1", "PA2", | |
898 | "PA3", "PA4", "PA5", "PA6", | |
899 | "PA7", "PA8", "PA9", "PA10", | |
900 | "PA11", "PA12", "PA13", "PA14", | |
901 | "PA15", "PA16"; | |
902 | allwinner,function = "emac"; | |
092a0c3b MR |
903 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
904 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
756084c5 | 905 | }; |
f2e0759e CYT |
906 | |
907 | clk_out_a_pins_a: clk_out_a@0 { | |
908 | allwinner,pins = "PI12"; | |
909 | allwinner,function = "clk_out_a"; | |
092a0c3b MR |
910 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
911 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
f2e0759e CYT |
912 | }; |
913 | ||
914 | clk_out_b_pins_a: clk_out_b@0 { | |
915 | allwinner,pins = "PI13"; | |
916 | allwinner,function = "clk_out_b"; | |
092a0c3b MR |
917 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
918 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
f2e0759e | 919 | }; |
129ccbcd CYT |
920 | |
921 | gmac_pins_mii_a: gmac_mii@0 { | |
922 | allwinner,pins = "PA0", "PA1", "PA2", | |
923 | "PA3", "PA4", "PA5", "PA6", | |
924 | "PA7", "PA8", "PA9", "PA10", | |
925 | "PA11", "PA12", "PA13", "PA14", | |
926 | "PA15", "PA16"; | |
927 | allwinner,function = "gmac"; | |
092a0c3b MR |
928 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
929 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
129ccbcd CYT |
930 | }; |
931 | ||
932 | gmac_pins_rgmii_a: gmac_rgmii@0 { | |
933 | allwinner,pins = "PA0", "PA1", "PA2", | |
934 | "PA3", "PA4", "PA5", "PA6", | |
935 | "PA7", "PA8", "PA10", | |
936 | "PA11", "PA12", "PA13", | |
937 | "PA15", "PA16"; | |
938 | allwinner,function = "gmac"; | |
939 | /* | |
940 | * data lines in RGMII mode use DDR mode | |
941 | * and need a higher signal drive strength | |
942 | */ | |
092a0c3b MR |
943 | allwinner,drive = <SUN4I_PINCTRL_40_MA>; |
944 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
129ccbcd | 945 | }; |
412f2c6f | 946 | |
2dad53b5 | 947 | spi0_pins_a: spi0@0 { |
f3022c6c MR |
948 | allwinner,pins = "PI11", "PI12", "PI13"; |
949 | allwinner,function = "spi0"; | |
950 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
951 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
952 | }; | |
953 | ||
954 | spi0_cs0_pins_a: spi0_cs0@0 { | |
955 | allwinner,pins = "PI10"; | |
956 | allwinner,function = "spi0"; | |
957 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
958 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
959 | }; | |
960 | ||
961 | spi0_cs1_pins_a: spi0_cs1@0 { | |
962 | allwinner,pins = "PI14"; | |
2dad53b5 | 963 | allwinner,function = "spi0"; |
092a0c3b MR |
964 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
965 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
2dad53b5 HG |
966 | }; |
967 | ||
412f2c6f | 968 | spi1_pins_a: spi1@0 { |
f3022c6c MR |
969 | allwinner,pins = "PI17", "PI18", "PI19"; |
970 | allwinner,function = "spi1"; | |
971 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
972 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
973 | }; | |
974 | ||
975 | spi1_cs0_pins_a: spi1_cs0@0 { | |
976 | allwinner,pins = "PI16"; | |
412f2c6f | 977 | allwinner,function = "spi1"; |
092a0c3b MR |
978 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
979 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
412f2c6f MR |
980 | }; |
981 | ||
982 | spi2_pins_a: spi2@0 { | |
f3022c6c | 983 | allwinner,pins = "PC20", "PC21", "PC22"; |
412f2c6f | 984 | allwinner,function = "spi2"; |
092a0c3b MR |
985 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
986 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
7b5bace3 WW |
987 | }; |
988 | ||
989 | spi2_pins_b: spi2@1 { | |
f3022c6c MR |
990 | allwinner,pins = "PB15", "PB16", "PB17"; |
991 | allwinner,function = "spi2"; | |
992 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
993 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
994 | }; | |
995 | ||
996 | spi2_cs0_pins_a: spi2_cs0@0 { | |
997 | allwinner,pins = "PC19"; | |
998 | allwinner,function = "spi2"; | |
999 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1000 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1001 | }; | |
1002 | ||
1003 | spi2_cs0_pins_b: spi2_cs0@1 { | |
1004 | allwinner,pins = "PB14"; | |
7b5bace3 | 1005 | allwinner,function = "spi2"; |
092a0c3b MR |
1006 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1007 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
412f2c6f | 1008 | }; |
11fbedf4 HG |
1009 | |
1010 | mmc0_pins_a: mmc0@0 { | |
d8cacaa3 MR |
1011 | allwinner,pins = "PF0", "PF1", "PF2", |
1012 | "PF3", "PF4", "PF5"; | |
11fbedf4 | 1013 | allwinner,function = "mmc0"; |
092a0c3b MR |
1014 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
1015 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
11fbedf4 HG |
1016 | }; |
1017 | ||
1018 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | |
1019 | allwinner,pins = "PH1"; | |
1020 | allwinner,function = "gpio_in"; | |
092a0c3b MR |
1021 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1022 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
11fbedf4 HG |
1023 | }; |
1024 | ||
8fa82326 | 1025 | mmc2_pins_a: mmc2@0 { |
d8cacaa3 MR |
1026 | allwinner,pins = "PC6", "PC7", "PC8", |
1027 | "PC9", "PC10", "PC11"; | |
8fa82326 | 1028 | allwinner,function = "mmc2"; |
092a0c3b MR |
1029 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
1030 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
8fa82326 HG |
1031 | }; |
1032 | ||
11fbedf4 | 1033 | mmc3_pins_a: mmc3@0 { |
d8cacaa3 MR |
1034 | allwinner,pins = "PI4", "PI5", "PI6", |
1035 | "PI7", "PI8", "PI9"; | |
11fbedf4 | 1036 | allwinner,function = "mmc3"; |
092a0c3b MR |
1037 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
1038 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
11fbedf4 | 1039 | }; |
0fc2b7af | 1040 | |
469a22e6 MC |
1041 | ir0_rx_pins_a: ir0@0 { |
1042 | allwinner,pins = "PB4"; | |
0fc2b7af | 1043 | allwinner,function = "ir0"; |
092a0c3b MR |
1044 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1045 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
0fc2b7af AB |
1046 | }; |
1047 | ||
469a22e6 MC |
1048 | ir0_tx_pins_a: ir0@1 { |
1049 | allwinner,pins = "PB3"; | |
1050 | allwinner,function = "ir0"; | |
1051 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1052 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1053 | }; | |
1054 | ||
1055 | ir1_rx_pins_a: ir1@0 { | |
1056 | allwinner,pins = "PB23"; | |
1057 | allwinner,function = "ir1"; | |
1058 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1059 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1060 | }; | |
1061 | ||
1062 | ir1_tx_pins_a: ir1@1 { | |
1063 | allwinner,pins = "PB22"; | |
0fc2b7af | 1064 | allwinner,function = "ir1"; |
092a0c3b MR |
1065 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
1066 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
0fc2b7af | 1067 | }; |
1e8d1567 VP |
1068 | |
1069 | ps20_pins_a: ps20@0 { | |
1070 | allwinner,pins = "PI20", "PI21"; | |
1071 | allwinner,function = "ps2"; | |
1072 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1073 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1074 | }; | |
1075 | ||
1076 | ps21_pins_a: ps21@0 { | |
1077 | allwinner,pins = "PH12", "PH13"; | |
1078 | allwinner,function = "ps2"; | |
1079 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
1080 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
0fc2b7af | 1081 | }; |
17eac031 MR |
1082 | }; |
1083 | ||
4790ecfa | 1084 | timer@01c20c00 { |
b4f26440 | 1085 | compatible = "allwinner,sun4i-a10-timer"; |
4790ecfa | 1086 | reg = <0x01c20c00 0x90>; |
19882b84 MR |
1087 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, |
1088 | <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, | |
1089 | <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, | |
1090 | <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, | |
1091 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | |
1092 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
4790ecfa MR |
1093 | clocks = <&osc24M>; |
1094 | }; | |
1095 | ||
1096 | wdt: watchdog@01c20c90 { | |
ca5d04d9 | 1097 | compatible = "allwinner,sun4i-a10-wdt"; |
4790ecfa MR |
1098 | reg = <0x01c20c90 0x10>; |
1099 | }; | |
1100 | ||
b5d905c7 CC |
1101 | rtc: rtc@01c20d00 { |
1102 | compatible = "allwinner,sun7i-a20-rtc"; | |
1103 | reg = <0x01c20d00 0x20>; | |
19882b84 | 1104 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
b5d905c7 CC |
1105 | }; |
1106 | ||
8ec40c25 AB |
1107 | pwm: pwm@01c20e00 { |
1108 | compatible = "allwinner,sun7i-a20-pwm"; | |
1109 | reg = <0x01c20e00 0xc>; | |
1110 | clocks = <&osc24M>; | |
1111 | #pwm-cells = <3>; | |
1112 | status = "disabled"; | |
1113 | }; | |
1114 | ||
c1a0ee3d | 1115 | ir0: ir@01c21800 { |
1715a389 | 1116 | compatible = "allwinner,sun4i-a10-ir"; |
c1a0ee3d AB |
1117 | clocks = <&apb0_gates 6>, <&ir0_clk>; |
1118 | clock-names = "apb", "ir"; | |
19882b84 | 1119 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
c1a0ee3d AB |
1120 | reg = <0x01c21800 0x40>; |
1121 | status = "disabled"; | |
1122 | }; | |
1123 | ||
1124 | ir1: ir@01c21c00 { | |
1715a389 | 1125 | compatible = "allwinner,sun4i-a10-ir"; |
c1a0ee3d AB |
1126 | clocks = <&apb0_gates 7>, <&ir1_clk>; |
1127 | clock-names = "apb", "ir"; | |
19882b84 | 1128 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
c1a0ee3d AB |
1129 | reg = <0x01c21c00 0x40>; |
1130 | status = "disabled"; | |
1131 | }; | |
1132 | ||
a6a2d644 HG |
1133 | lradc: lradc@01c22800 { |
1134 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
1135 | reg = <0x01c22800 0x100>; | |
19882b84 | 1136 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
a6a2d644 HG |
1137 | status = "disabled"; |
1138 | }; | |
1139 | ||
2bad969f OS |
1140 | sid: eeprom@01c23800 { |
1141 | compatible = "allwinner,sun7i-a20-sid"; | |
1142 | reg = <0x01c23800 0x200>; | |
1143 | }; | |
1144 | ||
00f7ed8d | 1145 | rtp: rtp@01c25000 { |
8bf1b9b3 | 1146 | compatible = "allwinner,sun5i-a13-ts"; |
00f7ed8d | 1147 | reg = <0x01c25000 0x100>; |
19882b84 | 1148 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
41e7afb1 | 1149 | #thermal-sensor-cells = <0>; |
00f7ed8d HG |
1150 | }; |
1151 | ||
4790ecfa MR |
1152 | uart0: serial@01c28000 { |
1153 | compatible = "snps,dw-apb-uart"; | |
1154 | reg = <0x01c28000 0x400>; | |
19882b84 | 1155 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1156 | reg-shift = <2>; |
1157 | reg-io-width = <4>; | |
de7dc935 | 1158 | clocks = <&apb1_gates 16>; |
4790ecfa MR |
1159 | status = "disabled"; |
1160 | }; | |
1161 | ||
1162 | uart1: serial@01c28400 { | |
1163 | compatible = "snps,dw-apb-uart"; | |
1164 | reg = <0x01c28400 0x400>; | |
19882b84 | 1165 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1166 | reg-shift = <2>; |
1167 | reg-io-width = <4>; | |
de7dc935 | 1168 | clocks = <&apb1_gates 17>; |
4790ecfa MR |
1169 | status = "disabled"; |
1170 | }; | |
1171 | ||
1172 | uart2: serial@01c28800 { | |
1173 | compatible = "snps,dw-apb-uart"; | |
1174 | reg = <0x01c28800 0x400>; | |
19882b84 | 1175 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1176 | reg-shift = <2>; |
1177 | reg-io-width = <4>; | |
de7dc935 | 1178 | clocks = <&apb1_gates 18>; |
4790ecfa MR |
1179 | status = "disabled"; |
1180 | }; | |
1181 | ||
1182 | uart3: serial@01c28c00 { | |
1183 | compatible = "snps,dw-apb-uart"; | |
1184 | reg = <0x01c28c00 0x400>; | |
19882b84 | 1185 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1186 | reg-shift = <2>; |
1187 | reg-io-width = <4>; | |
de7dc935 | 1188 | clocks = <&apb1_gates 19>; |
4790ecfa MR |
1189 | status = "disabled"; |
1190 | }; | |
1191 | ||
1192 | uart4: serial@01c29000 { | |
1193 | compatible = "snps,dw-apb-uart"; | |
1194 | reg = <0x01c29000 0x400>; | |
19882b84 | 1195 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1196 | reg-shift = <2>; |
1197 | reg-io-width = <4>; | |
de7dc935 | 1198 | clocks = <&apb1_gates 20>; |
4790ecfa MR |
1199 | status = "disabled"; |
1200 | }; | |
1201 | ||
1202 | uart5: serial@01c29400 { | |
1203 | compatible = "snps,dw-apb-uart"; | |
1204 | reg = <0x01c29400 0x400>; | |
19882b84 | 1205 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1206 | reg-shift = <2>; |
1207 | reg-io-width = <4>; | |
de7dc935 | 1208 | clocks = <&apb1_gates 21>; |
4790ecfa MR |
1209 | status = "disabled"; |
1210 | }; | |
1211 | ||
1212 | uart6: serial@01c29800 { | |
1213 | compatible = "snps,dw-apb-uart"; | |
1214 | reg = <0x01c29800 0x400>; | |
19882b84 | 1215 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1216 | reg-shift = <2>; |
1217 | reg-io-width = <4>; | |
de7dc935 | 1218 | clocks = <&apb1_gates 22>; |
4790ecfa MR |
1219 | status = "disabled"; |
1220 | }; | |
1221 | ||
1222 | uart7: serial@01c29c00 { | |
1223 | compatible = "snps,dw-apb-uart"; | |
1224 | reg = <0x01c29c00 0x400>; | |
19882b84 | 1225 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
4790ecfa MR |
1226 | reg-shift = <2>; |
1227 | reg-io-width = <4>; | |
de7dc935 | 1228 | clocks = <&apb1_gates 23>; |
4790ecfa MR |
1229 | status = "disabled"; |
1230 | }; | |
1231 | ||
428abbb8 | 1232 | i2c0: i2c@01c2ac00 { |
d8cacaa3 MR |
1233 | compatible = "allwinner,sun7i-a20-i2c", |
1234 | "allwinner,sun4i-a10-i2c"; | |
428abbb8 | 1235 | reg = <0x01c2ac00 0x400>; |
19882b84 | 1236 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
428abbb8 | 1237 | clocks = <&apb1_gates 0>; |
428abbb8 | 1238 | status = "disabled"; |
d1412aed HG |
1239 | #address-cells = <1>; |
1240 | #size-cells = <0>; | |
428abbb8 MR |
1241 | }; |
1242 | ||
1243 | i2c1: i2c@01c2b000 { | |
d8cacaa3 MR |
1244 | compatible = "allwinner,sun7i-a20-i2c", |
1245 | "allwinner,sun4i-a10-i2c"; | |
428abbb8 | 1246 | reg = <0x01c2b000 0x400>; |
19882b84 | 1247 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
428abbb8 | 1248 | clocks = <&apb1_gates 1>; |
428abbb8 | 1249 | status = "disabled"; |
d1412aed HG |
1250 | #address-cells = <1>; |
1251 | #size-cells = <0>; | |
428abbb8 MR |
1252 | }; |
1253 | ||
1254 | i2c2: i2c@01c2b400 { | |
d8cacaa3 MR |
1255 | compatible = "allwinner,sun7i-a20-i2c", |
1256 | "allwinner,sun4i-a10-i2c"; | |
428abbb8 | 1257 | reg = <0x01c2b400 0x400>; |
19882b84 | 1258 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
428abbb8 | 1259 | clocks = <&apb1_gates 2>; |
428abbb8 | 1260 | status = "disabled"; |
d1412aed HG |
1261 | #address-cells = <1>; |
1262 | #size-cells = <0>; | |
428abbb8 MR |
1263 | }; |
1264 | ||
1265 | i2c3: i2c@01c2b800 { | |
d8cacaa3 MR |
1266 | compatible = "allwinner,sun7i-a20-i2c", |
1267 | "allwinner,sun4i-a10-i2c"; | |
428abbb8 | 1268 | reg = <0x01c2b800 0x400>; |
19882b84 | 1269 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
428abbb8 | 1270 | clocks = <&apb1_gates 3>; |
428abbb8 | 1271 | status = "disabled"; |
d1412aed HG |
1272 | #address-cells = <1>; |
1273 | #size-cells = <0>; | |
428abbb8 MR |
1274 | }; |
1275 | ||
a3867045 | 1276 | i2c4: i2c@01c2c000 { |
d8cacaa3 MR |
1277 | compatible = "allwinner,sun7i-a20-i2c", |
1278 | "allwinner,sun4i-a10-i2c"; | |
a3867045 | 1279 | reg = <0x01c2c000 0x400>; |
19882b84 | 1280 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
428abbb8 | 1281 | clocks = <&apb1_gates 15>; |
428abbb8 | 1282 | status = "disabled"; |
d1412aed HG |
1283 | #address-cells = <1>; |
1284 | #size-cells = <0>; | |
428abbb8 MR |
1285 | }; |
1286 | ||
c40b8d58 CYT |
1287 | gmac: ethernet@01c50000 { |
1288 | compatible = "allwinner,sun7i-a20-gmac"; | |
1289 | reg = <0x01c50000 0x10000>; | |
19882b84 | 1290 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
c40b8d58 CYT |
1291 | interrupt-names = "macirq"; |
1292 | clocks = <&ahb_gates 49>, <&gmac_tx_clk>; | |
1293 | clock-names = "stmmaceth", "allwinner_gmac_tx"; | |
1294 | snps,pbl = <2>; | |
1295 | snps,fixed-burst; | |
1296 | snps,force_sf_dma_mode; | |
1297 | status = "disabled"; | |
1298 | #address-cells = <1>; | |
1299 | #size-cells = <0>; | |
1300 | }; | |
1301 | ||
31f8ad38 MR |
1302 | hstimer@01c60000 { |
1303 | compatible = "allwinner,sun7i-a20-hstimer"; | |
1304 | reg = <0x01c60000 0x1000>; | |
19882b84 MR |
1305 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, |
1306 | <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, | |
1307 | <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, | |
1308 | <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
31f8ad38 MR |
1309 | clocks = <&ahb_gates 28>; |
1310 | }; | |
1311 | ||
4790ecfa MR |
1312 | gic: interrupt-controller@01c81000 { |
1313 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
1314 | reg = <0x01c81000 0x1000>, | |
1315 | <0x01c82000 0x1000>, | |
1316 | <0x01c84000 0x2000>, | |
1317 | <0x01c86000 0x2000>; | |
1318 | interrupt-controller; | |
1319 | #interrupt-cells = <3>; | |
19882b84 | 1320 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
4790ecfa | 1321 | }; |
196654ae VP |
1322 | |
1323 | ps20: ps2@01c2a000 { | |
1324 | compatible = "allwinner,sun4i-a10-ps2"; | |
1325 | reg = <0x01c2a000 0x400>; | |
1326 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
1327 | clocks = <&apb1_gates 6>; | |
1328 | status = "disabled"; | |
1329 | }; | |
1330 | ||
1331 | ps21: ps2@01c2a400 { | |
1332 | compatible = "allwinner,sun4i-a10-ps2"; | |
1333 | reg = <0x01c2a400 0x400>; | |
1334 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
1335 | clocks = <&apb1_gates 7>; | |
1336 | status = "disabled"; | |
4790ecfa MR |
1337 | }; |
1338 | }; | |
1339 | }; |