[deliverable/linux.git] / arch / arm / boot / dts / sun8i-a23-a33.dtsi

/*
 * Copyright 2014 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
	interrupt-parent = <&gic>;

	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		framebuffer@0 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0";
			clocks = <&pll6 0>;
			status = "disabled";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <24000000>;
		arm,cpu-registers-not-fw-configured;
	};

	cpus {
		enable-method = "allwinner,sun8i-a23";
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: osc24M_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: osc32k_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};

		pll1: clk@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun8i-a23-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll1";
		};

		/* dummy clock until actually implemented */
		pll5: pll5_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
			clock-output-names = "pll5";
		};

		pll6: clk@01c20028 {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-pll6-clk";
			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll6", "pll6x2";
		};

		cpu: cpu_clk@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-cpu-clk";
			reg = <0x01c20050 0x4>;

			/*
			 * PLL1 is listed twice here.
			 * While it looks suspicious, it's actually documented
			 * that way both in the datasheet and in the code from
			 * Allwinner.
			 */
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
			clock-output-names = "cpu";
		};

		axi: axi_clk@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun8i-a23-axi-clk";
			reg = <0x01c20050 0x4>;
			clocks = <&cpu>;
			clock-output-names = "axi";
		};

		ahb1: ahb1_clk@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-ahb1-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
			clock-output-names = "ahb1";
		};

		apb1: apb1_clk@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb1>;
			clock-output-names = "apb1";
		};

		ahb1_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb1>;
			clock-output-names = "ahb1_mipidsi", "ahb1_dma",
					"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
					"ahb1_nand", "ahb1_sdram",
					"ahb1_hstimer", "ahb1_spi0",
					"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
					"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
					"ahb1_csi", "ahb1_be",	"ahb1_fe",
					"ahb1_gpu", "ahb1_spinlock",
					"ahb1_drc";
		};

		apb1_gates: clk@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun8i-a23-apb1-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_codec", "apb1_pio",
					"apb1_daudio0",	"apb1_daudio1";
		};

		apb2: clk@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb1-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
			clock-output-names = "apb2";
		};

		apb2_gates: clk@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun8i-a23-apb2-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb2>;
			clock-output-names = "apb2_i2c0", "apb2_i2c1",
					"apb2_i2c2", "apb2_uart0",
					"apb2_uart1", "apb2_uart2",
					"apb2_uart3", "apb2_uart4";
		};

		mmc0_clk: clk@01c20088 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c20088 0x4>;
			clocks = <&osc24M>, <&pll6 0>;
			clock-output-names = "mmc0",
					     "mmc0_output",
					     "mmc0_sample";
		};

		mmc1_clk: clk@01c2008c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c2008c 0x4>;
			clocks = <&osc24M>, <&pll6 0>;
			clock-output-names = "mmc1",
					     "mmc1_output",
					     "mmc1_sample";
		};

		mmc2_clk: clk@01c20090 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c20090 0x4>;
			clocks = <&osc24M>, <&pll6 0>;
			clock-output-names = "mmc2",
					     "mmc2_output",
					     "mmc2_sample";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		dma: dma-controller@01c02000 {
			compatible = "allwinner,sun8i-a23-dma";
			reg = <0x01c02000 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ahb1_gates 6>;
			resets = <&ahb1_rst 6>;
			#dma-cells = <1>;
		};

		mmc0: mmc@01c0f000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&ahb1_gates 8>,
				 <&mmc0_clk 0>,
				 <&mmc0_clk 1>,
				 <&mmc0_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ahb1_rst 8>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc1: mmc@01c10000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c10000 0x1000>;
			clocks = <&ahb1_gates 9>,
				 <&mmc1_clk 0>,
				 <&mmc1_clk 1>,
				 <&mmc1_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ahb1_rst 9>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc2: mmc@01c11000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c11000 0x1000>;
			clocks = <&ahb1_gates 10>,
				 <&mmc2_clk 0>,
				 <&mmc2_clk 1>,
				 <&mmc2_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ahb1_rst 10>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		pio: pinctrl@01c20800 {
			/* compatible gets set in SoC specific dtsi file */
			reg = <0x01c20800 0x400>;
			/* interrupts get set in SoC specific dtsi file */
			clocks = <&apb1_gates 5>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PF2", "PF4";
				allwinner,function = "uart0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc0_pins_a: mmc0@0 {
				allwinner,pins = "PF0", "PF1", "PF2",
						 "PF3", "PF4", "PF5";
				allwinner,function = "mmc0";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc1_pins_a: mmc1@0 {
				allwinner,pins = "PG0", "PG1", "PG2",
						 "PG3", "PG4", "PG5";
				allwinner,function = "mmc1";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PH2", "PH3";
				allwinner,function = "i2c0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PH4", "PH5";
				allwinner,function = "i2c1";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PE12", "PE13";
				allwinner,function = "i2c2";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};
		};

		ahb1_rst: reset@01c202c0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202c0 0xc>;
		};

		apb1_rst: reset@01c202d0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202d0 0x4>;
		};

		apb2_rst: reset@01c202d8 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202d8 0x4>;
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0xa0>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24M>;
		};

		wdt0: watchdog@01c20ca0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x01c20ca0 0x20>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		};

		lradc: lradc@01c22800 {
			compatible = "allwinner,sun4i-a10-lradc-keys";
			reg = <0x01c22800 0x100>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 16>;
			resets = <&apb2_rst 16>;
			dmas = <&dma 6>, <&dma 6>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 17>;
			resets = <&apb2_rst 17>;
			dmas = <&dma 7>, <&dma 7>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 18>;
			resets = <&apb2_rst 18>;
			dmas = <&dma 8>, <&dma 8>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 19>;
			resets = <&apb2_rst 19>;
			dmas = <&dma 9>, <&dma 9>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 20>;
			resets = <&apb2_rst 20>;
			dmas = <&dma 10>, <&dma 10>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb2_gates 0>;
			resets = <&apb2_rst 0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb2_gates 1>;
			resets = <&apb2_rst 1>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb2_gates 2>;
			resets = <&apb2_rst 2>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		rtc: rtc@01f00000 {
			compatible = "allwinner,sun6i-a31-rtc";
			reg = <0x01f00000 0x54>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		};

		prcm@01f01400 {
			compatible = "allwinner,sun8i-a23-prcm";
			reg = <0x01f01400 0x200>;

			ar100: ar100_clk {
				compatible = "fixed-factor-clock";
				#clock-cells = <0>;
				clock-div = <1>;
				clock-mult = <1>;
				clocks = <&osc24M>;
				clock-output-names = "ar100";
			};

			ahb0: ahb0_clk {
				compatible = "fixed-factor-clock";
				#clock-cells = <0>;
				clock-div = <1>;
				clock-mult = <1>;
				clocks = <&ar100>;
				clock-output-names = "ahb0";
			};

			apb0: apb0_clk {
				compatible = "allwinner,sun8i-a23-apb0-clk";
				#clock-cells = <0>;
				clocks = <&ahb0>;
				clock-output-names = "apb0";
			};

			apb0_gates: apb0_gates_clk {
				compatible = "allwinner,sun8i-a23-apb0-gates-clk";
				#clock-cells = <1>;
				clocks = <&apb0>;
				clock-output-names = "apb0_pio", "apb0_timer",
						"apb0_rsb", "apb0_uart",
						"apb0_i2c";
			};

			apb0_rst: apb0_rst {
				compatible = "allwinner,sun6i-a31-clock-reset";
				#reset-cells = <1>;
			};
		};

		cpucfg@01f01c00 {
			compatible = "allwinner,sun8i-a23-cpuconfig";
			reg = <0x01f01c00 0x300>;
		};

		r_uart: serial@01f02800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01f02800 0x400>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb0_gates 4>;
			resets = <&apb0_rst 4>;
			status = "disabled";
		};

		r_pio: pinctrl@01f02c00 {
			compatible = "allwinner,sun8i-a23-r-pinctrl";
			reg = <0x01f02c00 0x400>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb0_gates 0>;
			resets = <&apb0_rst 0>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			r_uart_pins_a: r_uart@0 {
				allwinner,pins = "PL2", "PL3";
				allwinner,function = "s_uart";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};
		};
	};
};
Commit	Line	Data
a0e9e9be VP	1	/*
	2	* Copyright 2014 Chen-Yu Tsai
	3	*
	4	* Chen-Yu Tsai <wens@csie.org>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This file is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This file is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43	*/
	44
	45	#include "skeleton.dtsi"
	46
	47	#include <dt-bindings/interrupt-controller/arm-gic.h>
	48
	49	#include <dt-bindings/pinctrl/sun4i-a10.h>
	50
	51	/ {
	52	interrupt-parent = <&gic>;
	53
	54	chosen {
	55	#address-cells = <1>;
	56	#size-cells = <1>;
	57	ranges;
	58
	59	framebuffer@0 {
	60	compatible = "allwinner,simple-framebuffer",
	61	"simple-framebuffer";
	62	allwinner,pipeline = "de_be0-lcd0";
	63	clocks = <&pll6 0>;
	64	status = "disabled";
65	};
66	};
67
68	timer {
69	compatible = "arm,armv7-timer";
70	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
71	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
72	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
73	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
74	clock-frequency = <24000000>;
75	arm,cpu-registers-not-fw-configured;
76	};
77
78	cpus {
79	enable-method = "allwinner,sun8i-a23";
80	#address-cells = <1>;
81	#size-cells = <0>;
82
83	cpu@0 {
84	compatible = "arm,cortex-a7";
85	device_type = "cpu";
86	reg = <0>;
87	};
88
89	cpu@1 {
90	compatible = "arm,cortex-a7";
91	device_type = "cpu";
92	reg = <1>;
93	};
94	};
95
96	clocks {
97	#address-cells = <1>;
98	#size-cells = <1>;
99	ranges;
100
101	osc24M: osc24M_clk {
102	#clock-cells = <0>;
103	compatible = "fixed-clock";
104	clock-frequency = <24000000>;
105	clock-output-names = "osc24M";
106	};
107
108	osc32k: osc32k_clk {
109	#clock-cells = <0>;
110	compatible = "fixed-clock";
111	clock-frequency = <32768>;
112	clock-output-names = "osc32k";
113	};
114
115	pll1: clk@01c20000 {
116	#clock-cells = <0>;
117	compatible = "allwinner,sun8i-a23-pll1-clk";
118	reg = <0x01c20000 0x4>;
119	clocks = <&osc24M>;
120	clock-output-names = "pll1";
121	};
122
123	/* dummy clock until actually implemented */
124	pll5: pll5_clk {
125	#clock-cells = <0>;
126	compatible = "fixed-clock";
127	clock-frequency = <0>;
128	clock-output-names = "pll5";
129	};
130
131	pll6: clk@01c20028 {
132	#clock-cells = <1>;
133	compatible = "allwinner,sun6i-a31-pll6-clk";
134	reg = <0x01c20028 0x4>;
135	clocks = <&osc24M>;
136	clock-output-names = "pll6", "pll6x2";
137	};
138
139	cpu: cpu_clk@01c20050 {
140	#clock-cells = <0>;
141	compatible = "allwinner,sun4i-a10-cpu-clk";
142	reg = <0x01c20050 0x4>;
143
144	/*
145	* PLL1 is listed twice here.
146	* While it looks suspicious, it's actually documented
147	* that way both in the datasheet and in the code from
148	* Allwinner.
149	*/
150	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
151	clock-output-names = "cpu";
152	};
153
154	axi: axi_clk@01c20050 {
155	#clock-cells = <0>;
156	compatible = "allwinner,sun8i-a23-axi-clk";
157	reg = <0x01c20050 0x4>;
158	clocks = <&cpu>;
159	clock-output-names = "axi";
160	};
161
162	ahb1: ahb1_clk@01c20054 {
163	#clock-cells = <0>;
164	compatible = "allwinner,sun6i-a31-ahb1-clk";
165	reg = <0x01c20054 0x4>;
166	clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
167	clock-output-names = "ahb1";
168	};
169
170	apb1: apb1_clk@01c20054 {
171	#clock-cells = <0>;
172	compatible = "allwinner,sun4i-a10-apb0-clk";
173	reg = <0x01c20054 0x4>;
174	clocks = <&ahb1>;
175	clock-output-names = "apb1";
176	};
177
178	ahb1_gates: clk@01c20060 {
179	#clock-cells = <1>;
180	compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
181	reg = <0x01c20060 0x8>;
182	clocks = <&ahb1>;
183	clock-output-names = "ahb1_mipidsi", "ahb1_dma",
184	"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
185	"ahb1_nand", "ahb1_sdram",
186	"ahb1_hstimer", "ahb1_spi0",
187	"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
188	"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
189	"ahb1_csi", "ahb1_be", "ahb1_fe",
190	"ahb1_gpu", "ahb1_spinlock",
191	"ahb1_drc";
192	};
193
194	apb1_gates: clk@01c20068 {
195	#clock-cells = <1>;
196	compatible = "allwinner,sun8i-a23-apb1-gates-clk";
197	reg = <0x01c20068 0x4>;
198	clocks = <&apb1>;
199	clock-output-names = "apb1_codec", "apb1_pio",
200	"apb1_daudio0", "apb1_daudio1";
201	};
202
203	apb2: clk@01c20058 {
204	#clock-cells = <0>;
205	compatible = "allwinner,sun4i-a10-apb1-clk";
206	reg = <0x01c20058 0x4>;
207	clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
208	clock-output-names = "apb2";
209	};
210
211	apb2_gates: clk@01c2006c {
212	#clock-cells = <1>;
213	compatible = "allwinner,sun8i-a23-apb2-gates-clk";
214	reg = <0x01c2006c 0x4>;
215	clocks = <&apb2>;
216	clock-output-names = "apb2_i2c0", "apb2_i2c1",
217	"apb2_i2c2", "apb2_uart0",
218	"apb2_uart1", "apb2_uart2",
219	"apb2_uart3", "apb2_uart4";
220	};
221
222	mmc0_clk: clk@01c20088 {
223	#clock-cells = <1>;
224	compatible = "allwinner,sun4i-a10-mmc-clk";
225	reg = <0x01c20088 0x4>;
226	clocks = <&osc24M>, <&pll6 0>;
227	clock-output-names = "mmc0",
228	"mmc0_output",
229	"mmc0_sample";
230	};
231
232	mmc1_clk: clk@01c2008c {
233	#clock-cells = <1>;
234	compatible = "allwinner,sun4i-a10-mmc-clk";
235	reg = <0x01c2008c 0x4>;
236	clocks = <&osc24M>, <&pll6 0>;
237	clock-output-names = "mmc1",
238	"mmc1_output",
239	"mmc1_sample";
240	};
241
242	mmc2_clk: clk@01c20090 {
243	#clock-cells = <1>;
244	compatible = "allwinner,sun4i-a10-mmc-clk";
245	reg = <0x01c20090 0x4>;
246	clocks = <&osc24M>, <&pll6 0>;
247	clock-output-names = "mmc2",
248	"mmc2_output",
249	"mmc2_sample";
250	};
251	};
252
253	soc@01c00000 {
254	compatible = "simple-bus";
255	#address-cells = <1>;
256	#size-cells = <1>;
257	ranges;
258
259	dma: dma-controller@01c02000 {
260	compatible = "allwinner,sun8i-a23-dma";
261	reg = <0x01c02000 0x1000>;
262	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
263	clocks = <&ahb1_gates 6>;
264	resets = <&ahb1_rst 6>;
265	#dma-cells = <1>;
266	};
267
268	mmc0: mmc@01c0f000 {
269	compatible = "allwinner,sun5i-a13-mmc";
270	reg = <0x01c0f000 0x1000>;
271	clocks = <&ahb1_gates 8>,
272	<&mmc0_clk 0>,
273	<&mmc0_clk 1>,
274	<&mmc0_clk 2>;
275	clock-names = "ahb",
276	"mmc",
277	"output",
278	"sample";
279	resets = <&ahb1_rst 8>;
280	reset-names = "ahb";
281	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
282	status = "disabled";
283	#address-cells = <1>;
284	#size-cells = <0>;
285	};
286
287	mmc1: mmc@01c10000 {
288	compatible = "allwinner,sun5i-a13-mmc";
289	reg = <0x01c10000 0x1000>;
290	clocks = <&ahb1_gates 9>,
291	<&mmc1_clk 0>,
292	<&mmc1_clk 1>,
293	<&mmc1_clk 2>;
294	clock-names = "ahb",
295	"mmc",
296	"output",
297	"sample";
298	resets = <&ahb1_rst 9>;
299	reset-names = "ahb";
300	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
301	status = "disabled";
302	#address-cells = <1>;
303	#size-cells = <0>;
304	};
305
306	mmc2: mmc@01c11000 {
307	compatible = "allwinner,sun5i-a13-mmc";
308	reg = <0x01c11000 0x1000>;
309	clocks = <&ahb1_gates 10>,
310	<&mmc2_clk 0>,
311	<&mmc2_clk 1>,
312	<&mmc2_clk 2>;
313	clock-names = "ahb",
314	"mmc",
315	"output",
316	"sample";
317	resets = <&ahb1_rst 10>;
318	reset-names = "ahb";
319	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
320	status = "disabled";
321	#address-cells = <1>;
322	#size-cells = <0>;
323	};
324
325	pio: pinctrl@01c20800 {
326	/* compatible gets set in SoC specific dtsi file */
327	reg = <0x01c20800 0x400>;
328	/* interrupts get set in SoC specific dtsi file */
329	clocks = <&apb1_gates 5>;
330	gpio-controller;
331	interrupt-controller;
332	#address-cells = <1>;
333	#size-cells = <0>;
334	#gpio-cells = <3>;
335
336	uart0_pins_a: uart0@0 {
337	allwinner,pins = "PF2", "PF4";
338	allwinner,function = "uart0";
339	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
340	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
341	};
342
343	mmc0_pins_a: mmc0@0 {
344	allwinner,pins = "PF0", "PF1", "PF2",
345	"PF3", "PF4", "PF5";
346	allwinner,function = "mmc0";
347	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
348	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
349	};
350
351	mmc1_pins_a: mmc1@0 {
352	allwinner,pins = "PG0", "PG1", "PG2",
353	"PG3", "PG4", "PG5";
354	allwinner,function = "mmc1";
355	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
356	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
357	};
358
359	i2c0_pins_a: i2c0@0 {
360	allwinner,pins = "PH2", "PH3";
361	allwinner,function = "i2c0";
362	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
363	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
364	};
365
366	i2c1_pins_a: i2c1@0 {
367	allwinner,pins = "PH4", "PH5";
368	allwinner,function = "i2c1";
369	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
370	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
371	};
372
373	i2c2_pins_a: i2c2@0 {
374	allwinner,pins = "PE12", "PE13";
375	allwinner,function = "i2c2";
376	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
377	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
378	};
379	};
380
381	ahb1_rst: reset@01c202c0 {
382	#reset-cells = <1>;
383	compatible = "allwinner,sun6i-a31-clock-reset";
384	reg = <0x01c202c0 0xc>;
385	};
386
387	apb1_rst: reset@01c202d0 {
388	#reset-cells = <1>;
389	compatible = "allwinner,sun6i-a31-clock-reset";
390	reg = <0x01c202d0 0x4>;
391	};
392
393	apb2_rst: reset@01c202d8 {
394	#reset-cells = <1>;
395	compatible = "allwinner,sun6i-a31-clock-reset";
396	reg = <0x01c202d8 0x4>;
397	};
398
399	timer@01c20c00 {
400	compatible = "allwinner,sun4i-a10-timer";
401	reg = <0x01c20c00 0xa0>;
402	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
403	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
404	clocks = <&osc24M>;
405	};
406
407	wdt0: watchdog@01c20ca0 {
408	compatible = "allwinner,sun6i-a31-wdt";
409	reg = <0x01c20ca0 0x20>;
410	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
411	};
412
413	lradc: lradc@01c22800 {
414	compatible = "allwinner,sun4i-a10-lradc-keys";
415	reg = <0x01c22800 0x100>;
416	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
417	status = "disabled";
418	};
419
420	uart0: serial@01c28000 {
421	compatible = "snps,dw-apb-uart";
422	reg = <0x01c28000 0x400>;
423	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
424	reg-shift = <2>;
425	reg-io-width = <4>;
426	clocks = <&apb2_gates 16>;
427	resets = <&apb2_rst 16>;
428	dmas = <&dma 6>, <&dma 6>;
429	dma-names = "rx", "tx";
430	status = "disabled";
431	};
432
433	uart1: serial@01c28400 {
434	compatible = "snps,dw-apb-uart";
435	reg = <0x01c28400 0x400>;
436	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
437	reg-shift = <2>;
438	reg-io-width = <4>;
439	clocks = <&apb2_gates 17>;
440	resets = <&apb2_rst 17>;
441	dmas = <&dma 7>, <&dma 7>;
442	dma-names = "rx", "tx";
443	status = "disabled";
444	};
445
446	uart2: serial@01c28800 {
447	compatible = "snps,dw-apb-uart";
448	reg = <0x01c28800 0x400>;
449	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
450	reg-shift = <2>;
451	reg-io-width = <4>;
452	clocks = <&apb2_gates 18>;
453	resets = <&apb2_rst 18>;
454	dmas = <&dma 8>, <&dma 8>;
455	dma-names = "rx", "tx";
456	status = "disabled";
457	};
458
459	uart3: serial@01c28c00 {
460	compatible = "snps,dw-apb-uart";
461	reg = <0x01c28c00 0x400>;
462	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
463	reg-shift = <2>;
464	reg-io-width = <4>;
465	clocks = <&apb2_gates 19>;
466	resets = <&apb2_rst 19>;
467	dmas = <&dma 9>, <&dma 9>;
468	dma-names = "rx", "tx";
469	status = "disabled";
470	};
471
472	uart4: serial@01c29000 {
473	compatible = "snps,dw-apb-uart";
474	reg = <0x01c29000 0x400>;
475	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
476	reg-shift = <2>;
477	reg-io-width = <4>;
478	clocks = <&apb2_gates 20>;
479	resets = <&apb2_rst 20>;
480	dmas = <&dma 10>, <&dma 10>;
481	dma-names = "rx", "tx";
482	status = "disabled";
483	};
484
485	i2c0: i2c@01c2ac00 {
486	compatible = "allwinner,sun6i-a31-i2c";
487	reg = <0x01c2ac00 0x400>;
488	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
489	clocks = <&apb2_gates 0>;
490	resets = <&apb2_rst 0>;
491	status = "disabled";
492	#address-cells = <1>;
493	#size-cells = <0>;
494	};
495
496	i2c1: i2c@01c2b000 {
497	compatible = "allwinner,sun6i-a31-i2c";
498	reg = <0x01c2b000 0x400>;
499	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
500	clocks = <&apb2_gates 1>;
501	resets = <&apb2_rst 1>;
502	status = "disabled";
503	#address-cells = <1>;
504	#size-cells = <0>;
505	};
506
507	i2c2: i2c@01c2b400 {
508	compatible = "allwinner,sun6i-a31-i2c";
509	reg = <0x01c2b400 0x400>;
510	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
511	clocks = <&apb2_gates 2>;
512	resets = <&apb2_rst 2>;
513	status = "disabled";
514	#address-cells = <1>;
515	#size-cells = <0>;
516	};
517
518	gic: interrupt-controller@01c81000 {
519	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
520	reg = <0x01c81000 0x1000>,
521	<0x01c82000 0x1000>,
522	<0x01c84000 0x2000>,
523	<0x01c86000 0x2000>;
524	interrupt-controller;
525	#interrupt-cells = <3>;
526	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
527	};
528
529	rtc: rtc@01f00000 {
530	compatible = "allwinner,sun6i-a31-rtc";
531	reg = <0x01f00000 0x54>;
532	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
533	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
534	};
535
536	prcm@01f01400 {
537	compatible = "allwinner,sun8i-a23-prcm";
538	reg = <0x01f01400 0x200>;
539
540	ar100: ar100_clk {
541	compatible = "fixed-factor-clock";
542	#clock-cells = <0>;
543	clock-div = <1>;
544	clock-mult = <1>;
545	clocks = <&osc24M>;
546	clock-output-names = "ar100";
547	};
548
549	ahb0: ahb0_clk {
550	compatible = "fixed-factor-clock";
551	#clock-cells = <0>;
552	clock-div = <1>;
553	clock-mult = <1>;
554	clocks = <&ar100>;
555	clock-output-names = "ahb0";
556	};
557
558	apb0: apb0_clk {
559	compatible = "allwinner,sun8i-a23-apb0-clk";
560	#clock-cells = <0>;
561	clocks = <&ahb0>;
562	clock-output-names = "apb0";
563	};
564
565	apb0_gates: apb0_gates_clk {
566	compatible = "allwinner,sun8i-a23-apb0-gates-clk";
567	#clock-cells = <1>;
568	clocks = <&apb0>;
569	clock-output-names = "apb0_pio", "apb0_timer",
570	"apb0_rsb", "apb0_uart",
571	"apb0_i2c";
572	};
573
574	apb0_rst: apb0_rst {
575	compatible = "allwinner,sun6i-a31-clock-reset";
576	#reset-cells = <1>;
577	};
578	};
579
580	cpucfg@01f01c00 {
581	compatible = "allwinner,sun8i-a23-cpuconfig";
582	reg = <0x01f01c00 0x300>;
583	};
584
585	r_uart: serial@01f02800 {
586	compatible = "snps,dw-apb-uart";
587	reg = <0x01f02800 0x400>;
588	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
589	reg-shift = <2>;
590	reg-io-width = <4>;
591	clocks = <&apb0_gates 4>;
592	resets = <&apb0_rst 4>;
593	status = "disabled";
594	};
595
596	r_pio: pinctrl@01f02c00 {
597	compatible = "allwinner,sun8i-a23-r-pinctrl";
598	reg = <0x01f02c00 0x400>;
599	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
600	clocks = <&apb0_gates 0>;
601	resets = <&apb0_rst 0>;
602	gpio-controller;
603	interrupt-controller;
604	#address-cells = <1>;
605	#size-cells = <0>;
606	#gpio-cells = <3>;
607
608	r_uart_pins_a: r_uart@0 {
609	allwinner,pins = "PL2", "PL3";
610	allwinner,function = "s_uart";
611	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
612	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
613	};
614	};
615	};
616	};