Commit | Line | Data |
---|---|---|
76af3467 SW |
1 | /* |
2 | * This dts file supports Dalmore A04. | |
3 | * Other board revisions are not supported | |
4 | */ | |
5 | ||
a71c03e7 HD |
6 | /dts-v1/; |
7 | ||
e6e646e6 | 8 | #include <dt-bindings/input/input.h> |
1bd0bd49 | 9 | #include "tegra114.dtsi" |
a71c03e7 HD |
10 | |
11 | / { | |
12 | model = "NVIDIA Tegra114 Dalmore evaluation board"; | |
13 | compatible = "nvidia,dalmore", "nvidia,tegra114"; | |
14 | ||
553c0a20 SW |
15 | aliases { |
16 | rtc0 = "/i2c@7000d000/tps65913@58"; | |
17 | rtc1 = "/rtc@7000e000"; | |
18 | }; | |
19 | ||
a71c03e7 HD |
20 | memory { |
21 | reg = <0x80000000 0x40000000>; | |
22 | }; | |
23 | ||
48b90117 | 24 | host1x@50000000 { |
f044d6fa MP |
25 | hdmi@54280000 { |
26 | status = "okay"; | |
27 | ||
4adb123d | 28 | hdmi-supply = <&vdd_5v0_hdmi>; |
f044d6fa MP |
29 | vdd-supply = <&vdd_hdmi_reg>; |
30 | pll-supply = <&palmas_smps3_reg>; | |
31 | ||
32 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
33 | nvidia,hpd-gpio = | |
34 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | |
35 | }; | |
36 | ||
48b90117 TR |
37 | dsi@54300000 { |
38 | status = "okay"; | |
39 | ||
87ab3533 TR |
40 | avdd-dsi-csi-supply = <&avdd_1v2_reg>; |
41 | ||
48b90117 TR |
42 | panel@0 { |
43 | compatible = "panasonic,vvx10f004b00", | |
44 | "simple-panel"; | |
45 | reg = <0>; | |
46 | ||
47 | power-supply = <&avdd_lcd_reg>; | |
48 | backlight = <&backlight>; | |
49 | }; | |
50 | }; | |
51 | }; | |
52 | ||
58ecb23f | 53 | pinmux@70000868 { |
2c314d5c PR |
54 | pinctrl-names = "default"; |
55 | pinctrl-0 = <&state_default>; | |
56 | ||
57 | state_default: pinmux { | |
58 | clk1_out_pw4 { | |
59 | nvidia,pins = "clk1_out_pw4"; | |
60 | nvidia,function = "extperiph1"; | |
5fc6b0dd LD |
61 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
62 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
63 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
64 | }; |
65 | dap1_din_pn1 { | |
66 | nvidia,pins = "dap1_din_pn1"; | |
67 | nvidia,function = "i2s0"; | |
5fc6b0dd LD |
68 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
69 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
70 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
71 | }; |
72 | dap1_dout_pn2 { | |
73 | nvidia,pins = "dap1_dout_pn2", | |
74 | "dap1_fs_pn0", | |
75 | "dap1_sclk_pn3"; | |
76 | nvidia,function = "i2s0"; | |
5fc6b0dd LD |
77 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
78 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
79 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
80 | }; |
81 | dap2_din_pa4 { | |
82 | nvidia,pins = "dap2_din_pa4"; | |
83 | nvidia,function = "i2s1"; | |
5fc6b0dd LD |
84 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
85 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
86 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
87 | }; |
88 | dap2_dout_pa5 { | |
89 | nvidia,pins = "dap2_dout_pa5", | |
90 | "dap2_fs_pa2", | |
91 | "dap2_sclk_pa3"; | |
92 | nvidia,function = "i2s1"; | |
5fc6b0dd LD |
93 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
94 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
95 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
96 | }; |
97 | dap4_din_pp5 { | |
98 | nvidia,pins = "dap4_din_pp5", | |
99 | "dap4_dout_pp6", | |
100 | "dap4_fs_pp4", | |
101 | "dap4_sclk_pp7"; | |
102 | nvidia,function = "i2s3"; | |
5fc6b0dd LD |
103 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
104 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
105 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
106 | }; |
107 | dvfs_pwm_px0 { | |
108 | nvidia,pins = "dvfs_pwm_px0", | |
109 | "dvfs_clk_px2"; | |
110 | nvidia,function = "cldvfs"; | |
5fc6b0dd LD |
111 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
112 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
113 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
114 | }; |
115 | ulpi_clk_py0 { | |
116 | nvidia,pins = "ulpi_clk_py0", | |
117 | "ulpi_data0_po1", | |
118 | "ulpi_data1_po2", | |
119 | "ulpi_data2_po3", | |
120 | "ulpi_data3_po4", | |
121 | "ulpi_data4_po5", | |
122 | "ulpi_data5_po6", | |
123 | "ulpi_data6_po7", | |
124 | "ulpi_data7_po0"; | |
125 | nvidia,function = "ulpi"; | |
5fc6b0dd LD |
126 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
127 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
128 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
129 | }; |
130 | ulpi_dir_py1 { | |
131 | nvidia,pins = "ulpi_dir_py1", | |
132 | "ulpi_nxt_py2"; | |
133 | nvidia,function = "ulpi"; | |
5fc6b0dd LD |
134 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
135 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
136 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
137 | }; |
138 | ulpi_stp_py3 { | |
139 | nvidia,pins = "ulpi_stp_py3"; | |
140 | nvidia,function = "ulpi"; | |
5fc6b0dd LD |
141 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
142 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
143 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
144 | }; |
145 | cam_i2c_scl_pbb1 { | |
146 | nvidia,pins = "cam_i2c_scl_pbb1", | |
147 | "cam_i2c_sda_pbb2"; | |
148 | nvidia,function = "i2c3"; | |
5fc6b0dd LD |
149 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
150 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
151 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
152 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
153 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
154 | }; |
155 | cam_mclk_pcc0 { | |
156 | nvidia,pins = "cam_mclk_pcc0", | |
157 | "pbb0"; | |
158 | nvidia,function = "vi_alt3"; | |
5fc6b0dd LD |
159 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
160 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
161 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
162 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
163 | }; |
164 | gen2_i2c_scl_pt5 { | |
165 | nvidia,pins = "gen2_i2c_scl_pt5", | |
166 | "gen2_i2c_sda_pt6"; | |
167 | nvidia,function = "i2c2"; | |
5fc6b0dd LD |
168 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
169 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
170 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
171 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
172 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
173 | }; |
174 | gmi_a16_pj7 { | |
175 | nvidia,pins = "gmi_a16_pj7"; | |
176 | nvidia,function = "uartd"; | |
5fc6b0dd LD |
177 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
178 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
179 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
180 | }; |
181 | gmi_a17_pb0 { | |
182 | nvidia,pins = "gmi_a17_pb0", | |
183 | "gmi_a18_pb1"; | |
184 | nvidia,function = "uartd"; | |
5fc6b0dd LD |
185 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
186 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
187 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
188 | }; |
189 | gmi_a19_pk7 { | |
190 | nvidia,pins = "gmi_a19_pk7"; | |
191 | nvidia,function = "uartd"; | |
5fc6b0dd LD |
192 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
193 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
194 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
195 | }; |
196 | gmi_ad5_pg5 { | |
197 | nvidia,pins = "gmi_ad5_pg5", | |
198 | "gmi_cs6_n_pi3", | |
199 | "gmi_wr_n_pi0"; | |
200 | nvidia,function = "spi4"; | |
5fc6b0dd LD |
201 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
202 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
203 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
204 | }; |
205 | gmi_ad6_pg6 { | |
206 | nvidia,pins = "gmi_ad6_pg6", | |
207 | "gmi_ad7_pg7"; | |
208 | nvidia,function = "spi4"; | |
5fc6b0dd LD |
209 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
210 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
211 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
212 | }; |
213 | gmi_ad12_ph4 { | |
214 | nvidia,pins = "gmi_ad12_ph4"; | |
215 | nvidia,function = "rsvd4"; | |
5fc6b0dd LD |
216 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
217 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
218 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
219 | }; |
220 | gmi_ad9_ph1 { | |
221 | nvidia,pins = "gmi_ad9_ph1"; | |
222 | nvidia,function = "pwm1"; | |
5fc6b0dd LD |
223 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
224 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
225 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
226 | }; |
227 | gmi_cs1_n_pj2 { | |
228 | nvidia,pins = "gmi_cs1_n_pj2", | |
229 | "gmi_oe_n_pi1"; | |
230 | nvidia,function = "soc"; | |
5fc6b0dd LD |
231 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
232 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
233 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
234 | }; |
235 | clk2_out_pw5 { | |
236 | nvidia,pins = "clk2_out_pw5"; | |
237 | nvidia,function = "extperiph2"; | |
5fc6b0dd LD |
238 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
239 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
240 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
241 | }; |
242 | sdmmc1_clk_pz0 { | |
243 | nvidia,pins = "sdmmc1_clk_pz0"; | |
244 | nvidia,function = "sdmmc1"; | |
5fc6b0dd LD |
245 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
246 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
247 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
248 | }; |
249 | sdmmc1_cmd_pz1 { | |
250 | nvidia,pins = "sdmmc1_cmd_pz1", | |
251 | "sdmmc1_dat0_py7", | |
252 | "sdmmc1_dat1_py6", | |
253 | "sdmmc1_dat2_py5", | |
254 | "sdmmc1_dat3_py4"; | |
255 | nvidia,function = "sdmmc1"; | |
5fc6b0dd LD |
256 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
257 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
258 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
259 | }; |
260 | sdmmc1_wp_n_pv3 { | |
261 | nvidia,pins = "sdmmc1_wp_n_pv3"; | |
262 | nvidia,function = "spi4"; | |
5fc6b0dd LD |
263 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
264 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
265 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
266 | }; |
267 | sdmmc3_clk_pa6 { | |
268 | nvidia,pins = "sdmmc3_clk_pa6"; | |
269 | nvidia,function = "sdmmc3"; | |
5fc6b0dd LD |
270 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
271 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
272 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
273 | }; |
274 | sdmmc3_cmd_pa7 { | |
275 | nvidia,pins = "sdmmc3_cmd_pa7", | |
276 | "sdmmc3_dat0_pb7", | |
277 | "sdmmc3_dat1_pb6", | |
278 | "sdmmc3_dat2_pb5", | |
279 | "sdmmc3_dat3_pb4", | |
280 | "kb_col4_pq4", | |
281 | "sdmmc3_clk_lb_out_pee4", | |
282 | "sdmmc3_clk_lb_in_pee5"; | |
283 | nvidia,function = "sdmmc3"; | |
5fc6b0dd LD |
284 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
285 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
286 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
287 | }; |
288 | sdmmc4_clk_pcc4 { | |
289 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
290 | nvidia,function = "sdmmc4"; | |
5fc6b0dd LD |
291 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
292 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
293 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
294 | }; |
295 | sdmmc4_cmd_pt7 { | |
296 | nvidia,pins = "sdmmc4_cmd_pt7", | |
297 | "sdmmc4_dat0_paa0", | |
298 | "sdmmc4_dat1_paa1", | |
299 | "sdmmc4_dat2_paa2", | |
300 | "sdmmc4_dat3_paa3", | |
301 | "sdmmc4_dat4_paa4", | |
302 | "sdmmc4_dat5_paa5", | |
303 | "sdmmc4_dat6_paa6", | |
304 | "sdmmc4_dat7_paa7"; | |
305 | nvidia,function = "sdmmc4"; | |
5fc6b0dd LD |
306 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
307 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
308 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
309 | }; |
310 | clk_32k_out_pa0 { | |
311 | nvidia,pins = "clk_32k_out_pa0"; | |
312 | nvidia,function = "blink"; | |
5fc6b0dd LD |
313 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
314 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
315 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
316 | }; |
317 | kb_col0_pq0 { | |
318 | nvidia,pins = "kb_col0_pq0", | |
319 | "kb_col1_pq1", | |
320 | "kb_col2_pq2", | |
321 | "kb_row0_pr0", | |
322 | "kb_row1_pr1", | |
323 | "kb_row2_pr2"; | |
324 | nvidia,function = "kbc"; | |
5fc6b0dd LD |
325 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
326 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
327 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
328 | }; |
329 | dap3_din_pp1 { | |
330 | nvidia,pins = "dap3_din_pp1", | |
331 | "dap3_sclk_pp3"; | |
332 | nvidia,function = "displayb"; | |
5fc6b0dd LD |
333 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
334 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
335 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
336 | }; |
337 | pv0 { | |
338 | nvidia,pins = "pv0"; | |
339 | nvidia,function = "rsvd4"; | |
5fc6b0dd LD |
340 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
341 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
342 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
343 | }; |
344 | kb_row7_pr7 { | |
345 | nvidia,pins = "kb_row7_pr7"; | |
346 | nvidia,function = "rsvd2"; | |
5fc6b0dd LD |
347 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
348 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
349 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
350 | }; |
351 | kb_row10_ps2 { | |
352 | nvidia,pins = "kb_row10_ps2"; | |
353 | nvidia,function = "uarta"; | |
5fc6b0dd LD |
354 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
355 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
356 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
357 | }; |
358 | kb_row9_ps1 { | |
359 | nvidia,pins = "kb_row9_ps1"; | |
360 | nvidia,function = "uarta"; | |
5fc6b0dd LD |
361 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
362 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
363 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
364 | }; |
365 | pwr_i2c_scl_pz6 { | |
366 | nvidia,pins = "pwr_i2c_scl_pz6", | |
367 | "pwr_i2c_sda_pz7"; | |
368 | nvidia,function = "i2cpwr"; | |
5fc6b0dd LD |
369 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
370 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
371 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
372 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
373 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
374 | }; |
375 | sys_clk_req_pz5 { | |
376 | nvidia,pins = "sys_clk_req_pz5"; | |
377 | nvidia,function = "sysclk"; | |
5fc6b0dd LD |
378 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
379 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
380 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
381 | }; |
382 | core_pwr_req { | |
383 | nvidia,pins = "core_pwr_req"; | |
384 | nvidia,function = "pwron"; | |
5fc6b0dd LD |
385 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
386 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
387 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
388 | }; |
389 | cpu_pwr_req { | |
390 | nvidia,pins = "cpu_pwr_req"; | |
391 | nvidia,function = "cpu"; | |
5fc6b0dd LD |
392 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
393 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
394 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
395 | }; |
396 | pwr_int_n { | |
397 | nvidia,pins = "pwr_int_n"; | |
398 | nvidia,function = "pmi"; | |
5fc6b0dd LD |
399 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
400 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
401 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
402 | }; |
403 | reset_out_n { | |
404 | nvidia,pins = "reset_out_n"; | |
405 | nvidia,function = "reset_out_n"; | |
5fc6b0dd LD |
406 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
407 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
408 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
409 | }; |
410 | clk3_out_pee0 { | |
411 | nvidia,pins = "clk3_out_pee0"; | |
412 | nvidia,function = "extperiph3"; | |
5fc6b0dd LD |
413 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
414 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
415 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
416 | }; |
417 | gen1_i2c_scl_pc4 { | |
418 | nvidia,pins = "gen1_i2c_scl_pc4", | |
419 | "gen1_i2c_sda_pc5"; | |
420 | nvidia,function = "i2c1"; | |
5fc6b0dd LD |
421 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
422 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
423 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
424 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
425 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
426 | }; |
427 | uart2_cts_n_pj5 { | |
428 | nvidia,pins = "uart2_cts_n_pj5"; | |
429 | nvidia,function = "uartb"; | |
5fc6b0dd LD |
430 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
431 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
432 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
433 | }; |
434 | uart2_rts_n_pj6 { | |
435 | nvidia,pins = "uart2_rts_n_pj6"; | |
436 | nvidia,function = "uartb"; | |
5fc6b0dd LD |
437 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
438 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
439 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
440 | }; |
441 | uart2_rxd_pc3 { | |
442 | nvidia,pins = "uart2_rxd_pc3"; | |
443 | nvidia,function = "irda"; | |
5fc6b0dd LD |
444 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
445 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
446 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
447 | }; |
448 | uart2_txd_pc2 { | |
449 | nvidia,pins = "uart2_txd_pc2"; | |
450 | nvidia,function = "irda"; | |
5fc6b0dd LD |
451 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
452 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
453 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
454 | }; |
455 | uart3_cts_n_pa1 { | |
456 | nvidia,pins = "uart3_cts_n_pa1", | |
457 | "uart3_rxd_pw7"; | |
458 | nvidia,function = "uartc"; | |
5fc6b0dd LD |
459 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
460 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
461 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
462 | }; |
463 | uart3_rts_n_pc0 { | |
464 | nvidia,pins = "uart3_rts_n_pc0", | |
465 | "uart3_txd_pw6"; | |
466 | nvidia,function = "uartc"; | |
5fc6b0dd LD |
467 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
468 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
469 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
470 | }; |
471 | owr { | |
472 | nvidia,pins = "owr"; | |
473 | nvidia,function = "owr"; | |
5fc6b0dd LD |
474 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
475 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
476 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
477 | }; |
478 | hdmi_cec_pee3 { | |
479 | nvidia,pins = "hdmi_cec_pee3"; | |
480 | nvidia,function = "cec"; | |
5fc6b0dd LD |
481 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
482 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
483 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
484 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
485 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
486 | }; |
487 | ddc_scl_pv4 { | |
488 | nvidia,pins = "ddc_scl_pv4", | |
489 | "ddc_sda_pv5"; | |
490 | nvidia,function = "i2c4"; | |
5fc6b0dd LD |
491 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
492 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
493 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
494 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
495 | nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
496 | }; |
497 | spdif_in_pk6 { | |
498 | nvidia,pins = "spdif_in_pk6"; | |
499 | nvidia,function = "usb"; | |
5fc6b0dd LD |
500 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
501 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
502 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
503 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
504 | }; |
505 | usb_vbus_en0_pn4 { | |
506 | nvidia,pins = "usb_vbus_en0_pn4"; | |
507 | nvidia,function = "usb"; | |
5fc6b0dd LD |
508 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
509 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
510 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
511 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
512 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
513 | }; |
514 | gpio_x6_aud_px6 { | |
515 | nvidia,pins = "gpio_x6_aud_px6"; | |
516 | nvidia,function = "spi6"; | |
5fc6b0dd LD |
517 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
518 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
519 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
520 | }; |
521 | gpio_x4_aud_px4 { | |
522 | nvidia,pins = "gpio_x4_aud_px4", | |
523 | "gpio_x7_aud_px7"; | |
524 | nvidia,function = "rsvd1"; | |
5fc6b0dd LD |
525 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
526 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
527 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
528 | }; |
529 | gpio_x5_aud_px5 { | |
530 | nvidia,pins = "gpio_x5_aud_px5"; | |
531 | nvidia,function = "rsvd1"; | |
5fc6b0dd LD |
532 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
533 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
534 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
535 | }; |
536 | gpio_w2_aud_pw2 { | |
537 | nvidia,pins = "gpio_w2_aud_pw2"; | |
538 | nvidia,function = "rsvd2"; | |
5fc6b0dd LD |
539 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
540 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
541 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
542 | }; |
543 | gpio_w3_aud_pw3 { | |
544 | nvidia,pins = "gpio_w3_aud_pw3"; | |
545 | nvidia,function = "spi6"; | |
5fc6b0dd LD |
546 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
547 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
548 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
549 | }; |
550 | gpio_x1_aud_px1 { | |
551 | nvidia,pins = "gpio_x1_aud_px1"; | |
552 | nvidia,function = "rsvd4"; | |
5fc6b0dd LD |
553 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
554 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
555 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
556 | }; |
557 | gpio_x3_aud_px3 { | |
558 | nvidia,pins = "gpio_x3_aud_px3"; | |
559 | nvidia,function = "rsvd4"; | |
5fc6b0dd LD |
560 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
561 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
562 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
563 | }; |
564 | dap3_fs_pp0 { | |
565 | nvidia,pins = "dap3_fs_pp0"; | |
566 | nvidia,function = "i2s2"; | |
5fc6b0dd LD |
567 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
568 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
569 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
570 | }; |
571 | dap3_dout_pp2 { | |
572 | nvidia,pins = "dap3_dout_pp2"; | |
573 | nvidia,function = "i2s2"; | |
5fc6b0dd LD |
574 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
575 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
576 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
577 | }; |
578 | pv1 { | |
579 | nvidia,pins = "pv1"; | |
580 | nvidia,function = "rsvd1"; | |
5fc6b0dd LD |
581 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
582 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
583 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
584 | }; |
585 | pbb3 { | |
586 | nvidia,pins = "pbb3", | |
587 | "pbb5", | |
588 | "pbb6", | |
589 | "pbb7"; | |
590 | nvidia,function = "rsvd4"; | |
5fc6b0dd LD |
591 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
592 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
593 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
594 | }; |
595 | pcc1 { | |
596 | nvidia,pins = "pcc1", | |
597 | "pcc2"; | |
598 | nvidia,function = "rsvd4"; | |
5fc6b0dd LD |
599 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
600 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
601 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
602 | }; |
603 | gmi_ad0_pg0 { | |
604 | nvidia,pins = "gmi_ad0_pg0", | |
605 | "gmi_ad1_pg1"; | |
606 | nvidia,function = "gmi"; | |
5fc6b0dd LD |
607 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
608 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
609 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
610 | }; |
611 | gmi_ad10_ph2 { | |
612 | nvidia,pins = "gmi_ad10_ph2", | |
613 | "gmi_ad11_ph3", | |
614 | "gmi_ad13_ph5", | |
615 | "gmi_ad8_ph0", | |
616 | "gmi_clk_pk1"; | |
617 | nvidia,function = "gmi"; | |
5fc6b0dd LD |
618 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
619 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
620 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
621 | }; |
622 | gmi_ad2_pg2 { | |
623 | nvidia,pins = "gmi_ad2_pg2", | |
624 | "gmi_ad3_pg3"; | |
625 | nvidia,function = "gmi"; | |
5fc6b0dd LD |
626 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
627 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
628 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
629 | }; |
630 | gmi_adv_n_pk0 { | |
631 | nvidia,pins = "gmi_adv_n_pk0", | |
632 | "gmi_cs0_n_pj0", | |
633 | "gmi_cs2_n_pk3", | |
634 | "gmi_cs4_n_pk2", | |
635 | "gmi_cs7_n_pi6", | |
636 | "gmi_dqs_p_pj3", | |
637 | "gmi_iordy_pi5", | |
638 | "gmi_wp_n_pc7"; | |
639 | nvidia,function = "gmi"; | |
5fc6b0dd LD |
640 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
641 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
642 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
643 | }; |
644 | gmi_cs3_n_pk4 { | |
645 | nvidia,pins = "gmi_cs3_n_pk4"; | |
646 | nvidia,function = "gmi"; | |
5fc6b0dd LD |
647 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
648 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
649 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
650 | }; |
651 | clk2_req_pcc5 { | |
652 | nvidia,pins = "clk2_req_pcc5"; | |
653 | nvidia,function = "rsvd4"; | |
5fc6b0dd LD |
654 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
655 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
656 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
657 | }; |
658 | kb_col3_pq3 { | |
659 | nvidia,pins = "kb_col3_pq3", | |
660 | "kb_col6_pq6", | |
661 | "kb_col7_pq7"; | |
662 | nvidia,function = "kbc"; | |
5fc6b0dd LD |
663 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
664 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
665 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
666 | }; |
667 | kb_col5_pq5 { | |
668 | nvidia,pins = "kb_col5_pq5"; | |
669 | nvidia,function = "kbc"; | |
5fc6b0dd LD |
670 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
671 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
672 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
673 | }; |
674 | kb_row3_pr3 { | |
675 | nvidia,pins = "kb_row3_pr3", | |
676 | "kb_row4_pr4", | |
677 | "kb_row6_pr6", | |
678 | "kb_row8_ps0"; | |
679 | nvidia,function = "kbc"; | |
5fc6b0dd LD |
680 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
681 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
682 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
683 | }; |
684 | clk3_req_pee1 { | |
685 | nvidia,pins = "clk3_req_pee1"; | |
686 | nvidia,function = "rsvd4"; | |
5fc6b0dd LD |
687 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
688 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
689 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
690 | }; |
691 | pu4 { | |
692 | nvidia,pins = "pu4"; | |
693 | nvidia,function = "displayb"; | |
5fc6b0dd LD |
694 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
695 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
696 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
697 | }; |
698 | pu5 { | |
699 | nvidia,pins = "pu5", | |
700 | "pu6"; | |
701 | nvidia,function = "displayb"; | |
5fc6b0dd LD |
702 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
703 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
704 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
705 | }; |
706 | hdmi_int_pn7 { | |
707 | nvidia,pins = "hdmi_int_pn7"; | |
708 | nvidia,function = "rsvd1"; | |
5fc6b0dd LD |
709 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
710 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
711 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
2c314d5c PR |
712 | }; |
713 | clk1_req_pee2 { | |
714 | nvidia,pins = "clk1_req_pee2", | |
715 | "usb_vbus_en1_pn5"; | |
716 | nvidia,function = "rsvd4"; | |
5fc6b0dd LD |
717 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
718 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
719 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
720 | }; |
721 | ||
722 | drive_sdio1 { | |
723 | nvidia,pins = "drive_sdio1"; | |
5fc6b0dd LD |
724 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
725 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
726 | nvidia,pull-down-strength = <36>; |
727 | nvidia,pull-up-strength = <20>; | |
5fc6b0dd LD |
728 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; |
729 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; | |
2c314d5c PR |
730 | }; |
731 | drive_sdio3 { | |
732 | nvidia,pins = "drive_sdio3"; | |
5fc6b0dd LD |
733 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
734 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
735 | nvidia,pull-down-strength = <22>; |
736 | nvidia,pull-up-strength = <36>; | |
5fc6b0dd LD |
737 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
738 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
2c314d5c PR |
739 | }; |
740 | drive_gma { | |
741 | nvidia,pins = "drive_gma"; | |
5fc6b0dd LD |
742 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
743 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
2c314d5c PR |
744 | nvidia,pull-down-strength = <2>; |
745 | nvidia,pull-up-strength = <1>; | |
5fc6b0dd LD |
746 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
747 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
2c314d5c PR |
748 | }; |
749 | }; | |
750 | }; | |
751 | ||
a71c03e7 HD |
752 | serial@70006300 { |
753 | status = "okay"; | |
a71c03e7 HD |
754 | }; |
755 | ||
48b90117 TR |
756 | pwm@7000a000 { |
757 | status = "okay"; | |
758 | }; | |
759 | ||
33eb271e RK |
760 | i2c@7000c000 { |
761 | status = "okay"; | |
762 | clock-frequency = <100000>; | |
763 | ||
58ecb23f | 764 | battery: smart-battery@b { |
33eb271e RK |
765 | compatible = "ti,bq20z45", "sbs,sbs-battery"; |
766 | reg = <0xb>; | |
767 | battery-name = "battery"; | |
768 | sbs,i2c-retry-count = <2>; | |
769 | sbs,poll-retry-count = <100>; | |
d5284a67 | 770 | power-supplies = <&charger>; |
33eb271e | 771 | }; |
aa5ae424 | 772 | |
58ecb23f | 773 | rt5640: rt5640@1c { |
aa5ae424 SW |
774 | compatible = "realtek,rt5640"; |
775 | reg = <0x1c>; | |
776 | interrupt-parent = <&gpio>; | |
777 | interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>; | |
778 | realtek,ldo1-en-gpios = | |
779 | <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; | |
780 | }; | |
99bda7b9 WN |
781 | |
782 | temperature-sensor@4c { | |
783 | compatible = "onnn,nct1008"; | |
784 | reg = <0x4c>; | |
785 | vcc-supply = <&palmas_ldo6_reg>; | |
786 | interrupt-parent = <&gpio>; | |
787 | interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>; | |
788 | }; | |
33eb271e RK |
789 | }; |
790 | ||
f044d6fa MP |
791 | hdmi_ddc: i2c@7000c700 { |
792 | status = "okay"; | |
793 | }; | |
794 | ||
da204ee2 LD |
795 | i2c@7000d000 { |
796 | status = "okay"; | |
797 | clock-frequency = <400000>; | |
798 | ||
58ecb23f | 799 | tps51632@43 { |
da204ee2 LD |
800 | compatible = "ti,tps51632"; |
801 | reg = <0x43>; | |
802 | regulator-name = "vdd-cpu"; | |
803 | regulator-min-microvolt = <500000>; | |
804 | regulator-max-microvolt = <1520000>; | |
805 | regulator-boot-on; | |
806 | regulator-always-on; | |
807 | }; | |
81c6c56c | 808 | |
58ecb23f | 809 | tps65090@48 { |
81c6c56c LD |
810 | compatible = "ti,tps65090"; |
811 | reg = <0x48>; | |
812 | interrupt-parent = <&gpio>; | |
6cecf916 | 813 | interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>; |
81c6c56c LD |
814 | |
815 | vsys1-supply = <&vdd_ac_bat_reg>; | |
816 | vsys2-supply = <&vdd_ac_bat_reg>; | |
817 | vsys3-supply = <&vdd_ac_bat_reg>; | |
818 | infet1-supply = <&vdd_ac_bat_reg>; | |
819 | infet2-supply = <&vdd_ac_bat_reg>; | |
820 | infet3-supply = <&tps65090_dcdc2_reg>; | |
821 | infet4-supply = <&tps65090_dcdc2_reg>; | |
822 | infet5-supply = <&tps65090_dcdc2_reg>; | |
823 | infet6-supply = <&tps65090_dcdc2_reg>; | |
824 | infet7-supply = <&tps65090_dcdc2_reg>; | |
825 | vsys-l1-supply = <&vdd_ac_bat_reg>; | |
826 | vsys-l2-supply = <&vdd_ac_bat_reg>; | |
827 | ||
d5284a67 | 828 | charger: charger { |
1a99ece9 RK |
829 | compatible = "ti,tps65090-charger"; |
830 | ti,enable-low-current-chrg; | |
831 | }; | |
832 | ||
81c6c56c | 833 | regulators { |
fcf0b3a6 | 834 | tps65090_dcdc1_reg: dcdc1 { |
81c6c56c LD |
835 | regulator-name = "vdd-sys-5v0"; |
836 | regulator-always-on; | |
837 | regulator-boot-on; | |
838 | }; | |
839 | ||
840 | tps65090_dcdc2_reg: dcdc2 { | |
841 | regulator-name = "vdd-sys-3v3"; | |
842 | regulator-always-on; | |
843 | regulator-boot-on; | |
844 | }; | |
845 | ||
c321d968 | 846 | tps65090_dcdc3_reg: dcdc3 { |
81c6c56c LD |
847 | regulator-name = "vdd-ao"; |
848 | regulator-always-on; | |
849 | regulator-boot-on; | |
850 | }; | |
851 | ||
48b90117 | 852 | vdd_bl_reg: fet1 { |
81c6c56c LD |
853 | regulator-name = "vdd-lcd-bl"; |
854 | }; | |
855 | ||
856 | fet3 { | |
857 | regulator-name = "vdd-modem-3v3"; | |
858 | }; | |
859 | ||
48b90117 | 860 | avdd_lcd_reg: fet4 { |
81c6c56c LD |
861 | regulator-name = "avdd-lcd"; |
862 | }; | |
863 | ||
864 | fet5 { | |
865 | regulator-name = "vdd-lvds"; | |
866 | }; | |
867 | ||
868 | fet6 { | |
869 | regulator-name = "vdd-sd-slot"; | |
15d5ef4d | 870 | regulator-always-on; |
81c6c56c LD |
871 | regulator-boot-on; |
872 | }; | |
873 | ||
874 | fet7 { | |
875 | regulator-name = "vdd-com-3v3"; | |
876 | }; | |
877 | ||
878 | ldo1 { | |
879 | regulator-name = "vdd-sby-5v0"; | |
880 | regulator-always-on; | |
881 | regulator-boot-on; | |
882 | }; | |
883 | ||
884 | ldo2 { | |
885 | regulator-name = "vdd-sby-3v3"; | |
886 | regulator-always-on; | |
887 | regulator-boot-on; | |
888 | }; | |
889 | }; | |
890 | }; | |
c321d968 | 891 | |
58ecb23f | 892 | palmas: tps65913@58 { |
c321d968 LD |
893 | compatible = "ti,palmas"; |
894 | reg = <0x58>; | |
eca8f98e | 895 | interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>; |
c321d968 LD |
896 | |
897 | #interrupt-cells = <2>; | |
898 | interrupt-controller; | |
899 | ||
27cf5d14 BH |
900 | ti,system-power-controller; |
901 | ||
c321d968 LD |
902 | palmas_gpio: gpio { |
903 | compatible = "ti,palmas-gpio"; | |
904 | gpio-controller; | |
905 | #gpio-cells = <2>; | |
906 | }; | |
907 | ||
908 | pmic { | |
909 | compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; | |
910 | smps1-in-supply = <&tps65090_dcdc3_reg>; | |
911 | smps3-in-supply = <&tps65090_dcdc3_reg>; | |
912 | smps4-in-supply = <&tps65090_dcdc2_reg>; | |
913 | smps7-in-supply = <&tps65090_dcdc2_reg>; | |
914 | smps8-in-supply = <&tps65090_dcdc2_reg>; | |
915 | smps9-in-supply = <&tps65090_dcdc2_reg>; | |
916 | ldo1-in-supply = <&tps65090_dcdc2_reg>; | |
917 | ldo2-in-supply = <&tps65090_dcdc2_reg>; | |
918 | ldo3-in-supply = <&palmas_smps3_reg>; | |
919 | ldo4-in-supply = <&tps65090_dcdc2_reg>; | |
920 | ldo5-in-supply = <&vdd_ac_bat_reg>; | |
921 | ldo6-in-supply = <&tps65090_dcdc2_reg>; | |
922 | ldo7-in-supply = <&tps65090_dcdc2_reg>; | |
923 | ldo8-in-supply = <&tps65090_dcdc3_reg>; | |
924 | ldo9-in-supply = <&palmas_smps9_reg>; | |
925 | ldoln-in-supply = <&tps65090_dcdc1_reg>; | |
926 | ldousb-in-supply = <&tps65090_dcdc1_reg>; | |
927 | ||
928 | regulators { | |
929 | smps12 { | |
930 | regulator-name = "vddio-ddr"; | |
931 | regulator-min-microvolt = <1350000>; | |
932 | regulator-max-microvolt = <1350000>; | |
933 | regulator-always-on; | |
934 | regulator-boot-on; | |
935 | }; | |
936 | ||
937 | palmas_smps3_reg: smps3 { | |
938 | regulator-name = "vddio-1v8"; | |
939 | regulator-min-microvolt = <1800000>; | |
940 | regulator-max-microvolt = <1800000>; | |
941 | regulator-always-on; | |
942 | regulator-boot-on; | |
943 | }; | |
944 | ||
945 | smps45 { | |
946 | regulator-name = "vdd-core"; | |
947 | regulator-min-microvolt = <900000>; | |
948 | regulator-max-microvolt = <1400000>; | |
949 | regulator-always-on; | |
950 | regulator-boot-on; | |
951 | }; | |
952 | ||
953 | smps457 { | |
954 | regulator-name = "vdd-core"; | |
955 | regulator-min-microvolt = <900000>; | |
956 | regulator-max-microvolt = <1400000>; | |
957 | regulator-always-on; | |
958 | regulator-boot-on; | |
959 | }; | |
960 | ||
961 | smps8 { | |
962 | regulator-name = "avdd-pll"; | |
963 | regulator-min-microvolt = <1050000>; | |
964 | regulator-max-microvolt = <1050000>; | |
965 | regulator-always-on; | |
966 | regulator-boot-on; | |
967 | }; | |
968 | ||
969 | palmas_smps9_reg: smps9 { | |
970 | regulator-name = "sdhci-vdd-sd-slot"; | |
971 | regulator-min-microvolt = <2800000>; | |
972 | regulator-max-microvolt = <2800000>; | |
973 | regulator-always-on; | |
974 | }; | |
975 | ||
976 | ldo1 { | |
977 | regulator-name = "avdd-cam1"; | |
978 | regulator-min-microvolt = <2800000>; | |
979 | regulator-max-microvolt = <2800000>; | |
980 | }; | |
981 | ||
982 | ldo2 { | |
983 | regulator-name = "avdd-cam2"; | |
984 | regulator-min-microvolt = <2800000>; | |
985 | regulator-max-microvolt = <2800000>; | |
986 | }; | |
987 | ||
87ab3533 | 988 | avdd_1v2_reg: ldo3 { |
c321d968 LD |
989 | regulator-name = "avdd-dsi-csi"; |
990 | regulator-min-microvolt = <1200000>; | |
991 | regulator-max-microvolt = <1200000>; | |
c321d968 LD |
992 | }; |
993 | ||
994 | ldo4 { | |
995 | regulator-name = "vpp-fuse"; | |
996 | regulator-min-microvolt = <1800000>; | |
997 | regulator-max-microvolt = <1800000>; | |
998 | }; | |
999 | ||
99bda7b9 | 1000 | palmas_ldo6_reg: ldo6 { |
c321d968 LD |
1001 | regulator-name = "vdd-sensor-2v85"; |
1002 | regulator-min-microvolt = <2850000>; | |
1003 | regulator-max-microvolt = <2850000>; | |
1004 | }; | |
1005 | ||
1006 | ldo7 { | |
1007 | regulator-name = "vdd-af-cam1"; | |
1008 | regulator-min-microvolt = <2800000>; | |
1009 | regulator-max-microvolt = <2800000>; | |
1010 | }; | |
1011 | ||
1012 | ldo8 { | |
1013 | regulator-name = "vdd-rtc"; | |
1014 | regulator-min-microvolt = <900000>; | |
1015 | regulator-max-microvolt = <900000>; | |
1016 | regulator-always-on; | |
1017 | regulator-boot-on; | |
1018 | ti,enable-ldo8-tracking; | |
1019 | }; | |
1020 | ||
1021 | ldo9 { | |
1022 | regulator-name = "vddio-sdmmc-2"; | |
1023 | regulator-min-microvolt = <1800000>; | |
1024 | regulator-max-microvolt = <3300000>; | |
1025 | regulator-always-on; | |
1026 | regulator-boot-on; | |
1027 | }; | |
1028 | ||
1029 | ldoln { | |
1030 | regulator-name = "hvdd-usb"; | |
1031 | regulator-min-microvolt = <3300000>; | |
1032 | regulator-max-microvolt = <3300000>; | |
1033 | }; | |
1034 | ||
1035 | ldousb { | |
1036 | regulator-name = "avdd-usb"; | |
1037 | regulator-min-microvolt = <3300000>; | |
1038 | regulator-max-microvolt = <3300000>; | |
1039 | regulator-always-on; | |
1040 | regulator-boot-on; | |
1041 | }; | |
1042 | ||
1043 | regen1 { | |
1044 | regulator-name = "rail-3v3"; | |
1045 | regulator-max-microvolt = <3300000>; | |
1046 | regulator-always-on; | |
1047 | regulator-boot-on; | |
1048 | }; | |
1049 | ||
1050 | regen2 { | |
1051 | regulator-name = "rail-5v0"; | |
1052 | regulator-max-microvolt = <5000000>; | |
1053 | regulator-always-on; | |
1054 | regulator-boot-on; | |
1055 | }; | |
1056 | }; | |
1057 | }; | |
1058 | ||
1059 | rtc { | |
1060 | compatible = "ti,palmas-rtc"; | |
1061 | interrupt-parent = <&palmas>; | |
1062 | interrupts = <8 0>; | |
1063 | }; | |
6be3cf72 LD |
1064 | |
1065 | pinmux { | |
1066 | compatible = "ti,tps65913-pinctrl"; | |
1067 | pinctrl-names = "default"; | |
1068 | pinctrl-0 = <&palmas_default>; | |
1069 | ||
1070 | palmas_default: pinmux { | |
1071 | pin_gpio6 { | |
1072 | pins = "gpio6"; | |
1073 | function = "gpio"; | |
1074 | }; | |
1075 | }; | |
1076 | }; | |
c321d968 | 1077 | }; |
da204ee2 LD |
1078 | }; |
1079 | ||
5cc75fca LD |
1080 | spi@7000da00 { |
1081 | status = "okay"; | |
1082 | spi-max-frequency = <25000000>; | |
1083 | spi-flash@0 { | |
1084 | compatible = "winbond,w25q32dw"; | |
1085 | reg = <0>; | |
1086 | spi-max-frequency = <20000000>; | |
1087 | }; | |
1088 | }; | |
1089 | ||
58ecb23f | 1090 | pmc@7000e400 { |
a71c03e7 | 1091 | nvidia,invert-interrupt; |
47d2d63b | 1092 | nvidia,suspend-mode = <1>; |
4a7658fe JL |
1093 | nvidia,cpu-pwr-good-time = <500>; |
1094 | nvidia,cpu-pwr-off-time = <300>; | |
1095 | nvidia,core-pwr-good-time = <641 3845>; | |
1096 | nvidia,core-pwr-off-time = <61036>; | |
1097 | nvidia,core-power-req-active-high; | |
1098 | nvidia,sys-clock-req-active-high; | |
a71c03e7 | 1099 | }; |
7021d122 | 1100 | |
58ecb23f | 1101 | ahub@70080000 { |
aa5ae424 SW |
1102 | i2s@70080400 { |
1103 | status = "okay"; | |
1104 | }; | |
1105 | }; | |
1106 | ||
8d3207ca | 1107 | sdhci@78000400 { |
3325f1bc | 1108 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
cffb57e6 | 1109 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; |
8d3207ca RK |
1110 | bus-width = <4>; |
1111 | status = "okay"; | |
1112 | }; | |
1113 | ||
1114 | sdhci@78000600 { | |
1115 | bus-width = <8>; | |
1116 | status = "okay"; | |
7a2617a6 | 1117 | non-removable; |
8d3207ca RK |
1118 | }; |
1119 | ||
328dc0ec MP |
1120 | usb@7d008000 { |
1121 | status = "okay"; | |
1122 | }; | |
1123 | ||
1124 | usb-phy@7d008000 { | |
1125 | status = "okay"; | |
1126 | vbus-supply = <&usb3_vbus_reg>; | |
1127 | }; | |
1128 | ||
48b90117 TR |
1129 | backlight: backlight { |
1130 | compatible = "pwm-backlight"; | |
1131 | ||
1132 | enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; | |
1133 | power-supply = <&vdd_bl_reg>; | |
1134 | pwms = <&pwm 1 1000000>; | |
1135 | ||
1136 | brightness-levels = <0 4 8 16 32 64 128 255>; | |
1137 | default-brightness-level = <6>; | |
1138 | }; | |
1139 | ||
7021d122 JL |
1140 | clocks { |
1141 | compatible = "simple-bus"; | |
1142 | #address-cells = <1>; | |
1143 | #size-cells = <0>; | |
1144 | ||
58ecb23f | 1145 | clk32k_in: clock@0 { |
7021d122 JL |
1146 | compatible = "fixed-clock"; |
1147 | reg=<0>; | |
1148 | #clock-cells = <0>; | |
1149 | clock-frequency = <32768>; | |
1150 | }; | |
1151 | }; | |
81c6c56c | 1152 | |
21b341ca LD |
1153 | gpio-keys { |
1154 | compatible = "gpio-keys"; | |
1155 | ||
1156 | home { | |
1157 | label = "Home"; | |
1158 | gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; | |
e6e646e6 | 1159 | linux,code = <KEY_HOME>; |
21b341ca LD |
1160 | }; |
1161 | ||
1162 | power { | |
1163 | label = "Power"; | |
1164 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; | |
e6e646e6 | 1165 | linux,code = <KEY_POWER>; |
21b341ca LD |
1166 | gpio-key,wakeup; |
1167 | }; | |
1168 | ||
1169 | volume_down { | |
1170 | label = "Volume Down"; | |
1171 | gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; | |
e6e646e6 | 1172 | linux,code = <KEY_VOLUMEDOWN>; |
21b341ca LD |
1173 | }; |
1174 | ||
1175 | volume_up { | |
1176 | label = "Volume Up"; | |
1177 | gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; | |
e6e646e6 | 1178 | linux,code = <KEY_VOLUMEUP>; |
21b341ca LD |
1179 | }; |
1180 | }; | |
1181 | ||
81c6c56c LD |
1182 | regulators { |
1183 | compatible = "simple-bus"; | |
1184 | #address-cells = <1>; | |
1185 | #size-cells = <0>; | |
1186 | ||
1187 | vdd_ac_bat_reg: regulator@0 { | |
1188 | compatible = "regulator-fixed"; | |
1189 | reg = <0>; | |
1190 | regulator-name = "vdd_ac_bat"; | |
1191 | regulator-min-microvolt = <5000000>; | |
1192 | regulator-max-microvolt = <5000000>; | |
1193 | regulator-always-on; | |
1194 | }; | |
fcf0b3a6 LD |
1195 | |
1196 | dvdd_ts_reg: regulator@1 { | |
1197 | compatible = "regulator-fixed"; | |
1198 | reg = <1>; | |
1199 | regulator-name = "dvdd_ts"; | |
1200 | regulator-min-microvolt = <1800000>; | |
1201 | regulator-max-microvolt = <1800000>; | |
1202 | enable-active-high; | |
3325f1bc | 1203 | gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; |
fcf0b3a6 LD |
1204 | }; |
1205 | ||
fcf0b3a6 LD |
1206 | usb1_vbus_reg: regulator@3 { |
1207 | compatible = "regulator-fixed"; | |
1208 | reg = <3>; | |
1209 | regulator-name = "usb1_vbus"; | |
1210 | regulator-min-microvolt = <5000000>; | |
1211 | regulator-max-microvolt = <5000000>; | |
1212 | enable-active-high; | |
3325f1bc | 1213 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; |
fcf0b3a6 LD |
1214 | gpio-open-drain; |
1215 | vin-supply = <&tps65090_dcdc1_reg>; | |
1216 | }; | |
1217 | ||
1218 | usb3_vbus_reg: regulator@4 { | |
1219 | compatible = "regulator-fixed"; | |
1220 | reg = <4>; | |
1221 | regulator-name = "usb2_vbus"; | |
1222 | regulator-min-microvolt = <5000000>; | |
1223 | regulator-max-microvolt = <5000000>; | |
1224 | enable-active-high; | |
3325f1bc | 1225 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; |
fcf0b3a6 LD |
1226 | gpio-open-drain; |
1227 | vin-supply = <&tps65090_dcdc1_reg>; | |
1228 | }; | |
1229 | ||
1230 | vdd_hdmi_reg: regulator@5 { | |
1231 | compatible = "regulator-fixed"; | |
1232 | reg = <5>; | |
1233 | regulator-name = "vdd_hdmi_5v0"; | |
1234 | regulator-min-microvolt = <5000000>; | |
1235 | regulator-max-microvolt = <5000000>; | |
fcf0b3a6 LD |
1236 | vin-supply = <&tps65090_dcdc1_reg>; |
1237 | }; | |
c321d968 LD |
1238 | |
1239 | vdd_cam_1v8_reg: regulator@6 { | |
1240 | compatible = "regulator-fixed"; | |
1241 | reg = <6>; | |
1242 | regulator-name = "vdd_cam_1v8_reg"; | |
1243 | regulator-min-microvolt = <1800000>; | |
1244 | regulator-max-microvolt = <1800000>; | |
1245 | enable-active-high; | |
1246 | gpio = <&palmas_gpio 6 0>; | |
1247 | }; | |
4adb123d TR |
1248 | |
1249 | vdd_5v0_hdmi: regulator@7 { | |
1250 | compatible = "regulator-fixed"; | |
1251 | reg = <7>; | |
1252 | regulator-name = "VDD_5V0_HDMI_CON"; | |
1253 | regulator-min-microvolt = <5000000>; | |
1254 | regulator-max-microvolt = <5000000>; | |
1255 | gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; | |
1256 | enable-active-high; | |
1257 | vin-supply = <&tps65090_dcdc1_reg>; | |
1258 | }; | |
81c6c56c | 1259 | }; |
aa5ae424 SW |
1260 | |
1261 | sound { | |
1262 | compatible = "nvidia,tegra-audio-rt5640-dalmore", | |
1263 | "nvidia,tegra-audio-rt5640"; | |
1264 | nvidia,model = "NVIDIA Tegra Dalmore"; | |
1265 | ||
1266 | nvidia,audio-routing = | |
1267 | "Headphones", "HPOR", | |
1268 | "Headphones", "HPOL", | |
1269 | "Speakers", "SPORP", | |
1270 | "Speakers", "SPORN", | |
1271 | "Speakers", "SPOLP", | |
8af3bbec SW |
1272 | "Speakers", "SPOLN", |
1273 | "Mic Jack", "MICBIAS1", | |
1274 | "IN2P", "Mic Jack"; | |
aa5ae424 SW |
1275 | |
1276 | nvidia,i2s-controller = <&tegra_i2s1>; | |
1277 | nvidia,audio-codec = <&rt5640>; | |
1278 | ||
1279 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; | |
1280 | ||
1281 | clocks = <&tegra_car TEGRA114_CLK_PLL_A>, | |
1282 | <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, | |
1283 | <&tegra_car TEGRA114_CLK_EXTERN1>; | |
1284 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
1285 | }; | |
a71c03e7 | 1286 | }; |