projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| a71c03e7 HD |
1 | /dts-v1/; |
| 2 | ||
| e6e646e6 | 3 | #include <dt-bindings/input/input.h> |
| 1bd0bd49 | 4 | #include "tegra114.dtsi" |
| a71c03e7 HD |
5 | |
| 6 | / { | |
| 7 | model = "NVIDIA Tegra114 Dalmore evaluation board"; | |
| 8 | compatible = "nvidia,dalmore", "nvidia,tegra114"; | |
| 9 | ||
| 10 | memory { | |
| 11 | reg = <0x80000000 0x40000000>; | |
| 12 | }; | |
| 13 | ||
| 2c314d5c PR |
14 | pinmux { |
| 15 | pinctrl-names = "default"; | |
| 16 | pinctrl-0 = <&state_default>; | |
| 17 | ||
| 18 | state_default: pinmux { | |
| 19 | clk1_out_pw4 { | |
| 20 | nvidia,pins = "clk1_out_pw4"; | |
| 21 | nvidia,function = "extperiph1"; | |
| 22 | nvidia,pull = <0>; | |
| 23 | nvidia,tristate = <0>; | |
| 24 | nvidia,enable-input = <0>; | |
| 25 | }; | |
| 26 | dap1_din_pn1 { | |
| 27 | nvidia,pins = "dap1_din_pn1"; | |
| 28 | nvidia,function = "i2s0"; | |
| 29 | nvidia,pull = <0>; | |
| 30 | nvidia,tristate = <1>; | |
| 31 | nvidia,enable-input = <1>; | |
| 32 | }; | |
| 33 | dap1_dout_pn2 { | |
| 34 | nvidia,pins = "dap1_dout_pn2", | |
| 35 | "dap1_fs_pn0", | |
| 36 | "dap1_sclk_pn3"; | |
| 37 | nvidia,function = "i2s0"; | |
| 38 | nvidia,pull = <0>; | |
| 39 | nvidia,tristate = <0>; | |
| 40 | nvidia,enable-input = <1>; | |
| 41 | }; | |
| 42 | dap2_din_pa4 { | |
| 43 | nvidia,pins = "dap2_din_pa4"; | |
| 44 | nvidia,function = "i2s1"; | |
| 45 | nvidia,pull = <0>; | |
| 46 | nvidia,tristate = <1>; | |
| 47 | nvidia,enable-input = <1>; | |
| 48 | }; | |
| 49 | dap2_dout_pa5 { | |
| 50 | nvidia,pins = "dap2_dout_pa5", | |
| 51 | "dap2_fs_pa2", | |
| 52 | "dap2_sclk_pa3"; | |
| 53 | nvidia,function = "i2s1"; | |
| 54 | nvidia,pull = <0>; | |
| 55 | nvidia,tristate = <0>; | |
| 56 | nvidia,enable-input = <1>; | |
| 57 | }; | |
| 58 | dap4_din_pp5 { | |
| 59 | nvidia,pins = "dap4_din_pp5", | |
| 60 | "dap4_dout_pp6", | |
| 61 | "dap4_fs_pp4", | |
| 62 | "dap4_sclk_pp7"; | |
| 63 | nvidia,function = "i2s3"; | |
| 64 | nvidia,pull = <0>; | |
| 65 | nvidia,tristate = <0>; | |
| 66 | nvidia,enable-input = <1>; | |
| 67 | }; | |
| 68 | dvfs_pwm_px0 { | |
| 69 | nvidia,pins = "dvfs_pwm_px0", | |
| 70 | "dvfs_clk_px2"; | |
| 71 | nvidia,function = "cldvfs"; | |
| 72 | nvidia,pull = <0>; | |
| 73 | nvidia,tristate = <0>; | |
| 74 | nvidia,enable-input = <0>; | |
| 75 | }; | |
| 76 | ulpi_clk_py0 { | |
| 77 | nvidia,pins = "ulpi_clk_py0", | |
| 78 | "ulpi_data0_po1", | |
| 79 | "ulpi_data1_po2", | |
| 80 | "ulpi_data2_po3", | |
| 81 | "ulpi_data3_po4", | |
| 82 | "ulpi_data4_po5", | |
| 83 | "ulpi_data5_po6", | |
| 84 | "ulpi_data6_po7", | |
| 85 | "ulpi_data7_po0"; | |
| 86 | nvidia,function = "ulpi"; | |
| 87 | nvidia,pull = <0>; | |
| 88 | nvidia,tristate = <0>; | |
| 89 | nvidia,enable-input = <1>; | |
| 90 | }; | |
| 91 | ulpi_dir_py1 { | |
| 92 | nvidia,pins = "ulpi_dir_py1", | |
| 93 | "ulpi_nxt_py2"; | |
| 94 | nvidia,function = "ulpi"; | |
| 95 | nvidia,pull = <0>; | |
| 96 | nvidia,tristate = <1>; | |
| 97 | nvidia,enable-input = <1>; | |
| 98 | }; | |
| 99 | ulpi_stp_py3 { | |
| 100 | nvidia,pins = "ulpi_stp_py3"; | |
| 101 | nvidia,function = "ulpi"; | |
| 102 | nvidia,pull = <0>; | |
| 103 | nvidia,tristate = <0>; | |
| 104 | nvidia,enable-input = <0>; | |
| 105 | }; | |
| 106 | cam_i2c_scl_pbb1 { | |
| 107 | nvidia,pins = "cam_i2c_scl_pbb1", | |
| 108 | "cam_i2c_sda_pbb2"; | |
| 109 | nvidia,function = "i2c3"; | |
| 110 | nvidia,pull = <0>; | |
| 111 | nvidia,tristate = <0>; | |
| 112 | nvidia,enable-input = <1>; | |
| 113 | nvidia,lock = <0>; | |
| 114 | nvidia,open-drain = <0>; | |
| 115 | }; | |
| 116 | cam_mclk_pcc0 { | |
| 117 | nvidia,pins = "cam_mclk_pcc0", | |
| 118 | "pbb0"; | |
| 119 | nvidia,function = "vi_alt3"; | |
| 120 | nvidia,pull = <0>; | |
| 121 | nvidia,tristate = <0>; | |
| 122 | nvidia,enable-input = <0>; | |
| 123 | nvidia,lock = <0>; | |
| 124 | }; | |
| 125 | gen2_i2c_scl_pt5 { | |
| 126 | nvidia,pins = "gen2_i2c_scl_pt5", | |
| 127 | "gen2_i2c_sda_pt6"; | |
| 128 | nvidia,function = "i2c2"; | |
| 129 | nvidia,pull = <0>; | |
| 130 | nvidia,tristate = <0>; | |
| 131 | nvidia,enable-input = <1>; | |
| 132 | nvidia,lock = <0>; | |
| 133 | nvidia,open-drain = <0>; | |
| 134 | }; | |
| 135 | gmi_a16_pj7 { | |
| 136 | nvidia,pins = "gmi_a16_pj7"; | |
| 137 | nvidia,function = "uartd"; | |
| 138 | nvidia,pull = <0>; | |
| 139 | nvidia,tristate = <0>; | |
| 140 | nvidia,enable-input = <0>; | |
| 141 | }; | |
| 142 | gmi_a17_pb0 { | |
| 143 | nvidia,pins = "gmi_a17_pb0", | |
| 144 | "gmi_a18_pb1"; | |
| 145 | nvidia,function = "uartd"; | |
| 146 | nvidia,pull = <0>; | |
| 147 | nvidia,tristate = <1>; | |
| 148 | nvidia,enable-input = <1>; | |
| 149 | }; | |
| 150 | gmi_a19_pk7 { | |
| 151 | nvidia,pins = "gmi_a19_pk7"; | |
| 152 | nvidia,function = "uartd"; | |
| 153 | nvidia,pull = <0>; | |
| 154 | nvidia,tristate = <0>; | |
| 155 | nvidia,enable-input = <0>; | |
| 156 | }; | |
| 157 | gmi_ad5_pg5 { | |
| 158 | nvidia,pins = "gmi_ad5_pg5", | |
| 159 | "gmi_cs6_n_pi3", | |
| 160 | "gmi_wr_n_pi0"; | |
| 161 | nvidia,function = "spi4"; | |
| 162 | nvidia,pull = <0>; | |
| 163 | nvidia,tristate = <0>; | |
| 164 | nvidia,enable-input = <1>; | |
| 165 | }; | |
| 166 | gmi_ad6_pg6 { | |
| 167 | nvidia,pins = "gmi_ad6_pg6", | |
| 168 | "gmi_ad7_pg7"; | |
| 169 | nvidia,function = "spi4"; | |
| 170 | nvidia,pull = <2>; | |
| 171 | nvidia,tristate = <0>; | |
| 172 | nvidia,enable-input = <1>; | |
| 173 | }; | |
| 174 | gmi_ad12_ph4 { | |
| 175 | nvidia,pins = "gmi_ad12_ph4"; | |
| 176 | nvidia,function = "rsvd4"; | |
| 177 | nvidia,pull = <0>; | |
| 178 | nvidia,tristate = <0>; | |
| 179 | nvidia,enable-input = <0>; | |
| 180 | }; | |
| 181 | gmi_ad9_ph1 { | |
| 182 | nvidia,pins = "gmi_ad9_ph1"; | |
| 183 | nvidia,function = "pwm1"; | |
| 184 | nvidia,pull = <0>; | |
| 185 | nvidia,tristate = <0>; | |
| 186 | nvidia,enable-input = <0>; | |
| 187 | }; | |
| 188 | gmi_cs1_n_pj2 { | |
| 189 | nvidia,pins = "gmi_cs1_n_pj2", | |
| 190 | "gmi_oe_n_pi1"; | |
| 191 | nvidia,function = "soc"; | |
| 192 | nvidia,pull = <0>; | |
| 193 | nvidia,tristate = <1>; | |
| 194 | nvidia,enable-input = <1>; | |
| 195 | }; | |
| 196 | clk2_out_pw5 { | |
| 197 | nvidia,pins = "clk2_out_pw5"; | |
| 198 | nvidia,function = "extperiph2"; | |
| 199 | nvidia,pull = <0>; | |
| 200 | nvidia,tristate = <0>; | |
| 201 | nvidia,enable-input = <0>; | |
| 202 | }; | |
| 203 | sdmmc1_clk_pz0 { | |
| 204 | nvidia,pins = "sdmmc1_clk_pz0"; | |
| 205 | nvidia,function = "sdmmc1"; | |
| 206 | nvidia,pull = <0>; | |
| 207 | nvidia,tristate = <0>; | |
| 208 | nvidia,enable-input = <1>; | |
| 209 | }; | |
| 210 | sdmmc1_cmd_pz1 { | |
| 211 | nvidia,pins = "sdmmc1_cmd_pz1", | |
| 212 | "sdmmc1_dat0_py7", | |
| 213 | "sdmmc1_dat1_py6", | |
| 214 | "sdmmc1_dat2_py5", | |
| 215 | "sdmmc1_dat3_py4"; | |
| 216 | nvidia,function = "sdmmc1"; | |
| 217 | nvidia,pull = <2>; | |
| 218 | nvidia,tristate = <0>; | |
| 219 | nvidia,enable-input = <1>; | |
| 220 | }; | |
| 221 | sdmmc1_wp_n_pv3 { | |
| 222 | nvidia,pins = "sdmmc1_wp_n_pv3"; | |
| 223 | nvidia,function = "spi4"; | |
| 224 | nvidia,pull = <2>; | |
| 225 | nvidia,tristate = <0>; | |
| 226 | nvidia,enable-input = <0>; | |
| 227 | }; | |
| 228 | sdmmc3_clk_pa6 { | |
| 229 | nvidia,pins = "sdmmc3_clk_pa6"; | |
| 230 | nvidia,function = "sdmmc3"; | |
| 231 | nvidia,pull = <0>; | |
| 232 | nvidia,tristate = <0>; | |
| 233 | nvidia,enable-input = <1>; | |
| 234 | }; | |
| 235 | sdmmc3_cmd_pa7 { | |
| 236 | nvidia,pins = "sdmmc3_cmd_pa7", | |
| 237 | "sdmmc3_dat0_pb7", | |
| 238 | "sdmmc3_dat1_pb6", | |
| 239 | "sdmmc3_dat2_pb5", | |
| 240 | "sdmmc3_dat3_pb4", | |
| 241 | "kb_col4_pq4", | |
| 242 | "sdmmc3_clk_lb_out_pee4", | |
| 243 | "sdmmc3_clk_lb_in_pee5"; | |
| 244 | nvidia,function = "sdmmc3"; | |
| 245 | nvidia,pull = <2>; | |
| 246 | nvidia,tristate = <0>; | |
| 247 | nvidia,enable-input = <1>; | |
| 248 | }; | |
| 249 | sdmmc4_clk_pcc4 { | |
| 250 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
| 251 | nvidia,function = "sdmmc4"; | |
| 252 | nvidia,pull = <0>; | |
| 253 | nvidia,tristate = <0>; | |
| 254 | nvidia,enable-input = <1>; | |
| 255 | }; | |
| 256 | sdmmc4_cmd_pt7 { | |
| 257 | nvidia,pins = "sdmmc4_cmd_pt7", | |
| 258 | "sdmmc4_dat0_paa0", | |
| 259 | "sdmmc4_dat1_paa1", | |
| 260 | "sdmmc4_dat2_paa2", | |
| 261 | "sdmmc4_dat3_paa3", | |
| 262 | "sdmmc4_dat4_paa4", | |
| 263 | "sdmmc4_dat5_paa5", | |
| 264 | "sdmmc4_dat6_paa6", | |
| 265 | "sdmmc4_dat7_paa7"; | |
| 266 | nvidia,function = "sdmmc4"; | |
| 267 | nvidia,pull = <2>; | |
| 268 | nvidia,tristate = <0>; | |
| 269 | nvidia,enable-input = <1>; | |
| 270 | }; | |
| 271 | clk_32k_out_pa0 { | |
| 272 | nvidia,pins = "clk_32k_out_pa0"; | |
| 273 | nvidia,function = "blink"; | |
| 274 | nvidia,pull = <0>; | |
| 275 | nvidia,tristate = <0>; | |
| 276 | nvidia,enable-input = <0>; | |
| 277 | }; | |
| 278 | kb_col0_pq0 { | |
| 279 | nvidia,pins = "kb_col0_pq0", | |
| 280 | "kb_col1_pq1", | |
| 281 | "kb_col2_pq2", | |
| 282 | "kb_row0_pr0", | |
| 283 | "kb_row1_pr1", | |
| 284 | "kb_row2_pr2"; | |
| 285 | nvidia,function = "kbc"; | |
| 286 | nvidia,pull = <2>; | |
| 287 | nvidia,tristate = <0>; | |
| 288 | nvidia,enable-input = <1>; | |
| 289 | }; | |
| 290 | dap3_din_pp1 { | |
| 291 | nvidia,pins = "dap3_din_pp1", | |
| 292 | "dap3_sclk_pp3"; | |
| 293 | nvidia,function = "displayb"; | |
| 294 | nvidia,pull = <0>; | |
| 295 | nvidia,tristate = <1>; | |
| 296 | nvidia,enable-input = <0>; | |
| 297 | }; | |
| 298 | pv0 { | |
| 299 | nvidia,pins = "pv0"; | |
| 300 | nvidia,function = "rsvd4"; | |
| 301 | nvidia,pull = <0>; | |
| 302 | nvidia,tristate = <1>; | |
| 303 | nvidia,enable-input = <0>; | |
| 304 | }; | |
| 305 | kb_row7_pr7 { | |
| 306 | nvidia,pins = "kb_row7_pr7"; | |
| 307 | nvidia,function = "rsvd2"; | |
| 308 | nvidia,pull = <2>; | |
| 309 | nvidia,tristate = <0>; | |
| 310 | nvidia,enable-input = <1>; | |
| 311 | }; | |
| 312 | kb_row10_ps2 { | |
| 313 | nvidia,pins = "kb_row10_ps2"; | |
| 314 | nvidia,function = "uarta"; | |
| 315 | nvidia,pull = <0>; | |
| 316 | nvidia,tristate = <1>; | |
| 317 | nvidia,enable-input = <1>; | |
| 318 | }; | |
| 319 | kb_row9_ps1 { | |
| 320 | nvidia,pins = "kb_row9_ps1"; | |
| 321 | nvidia,function = "uarta"; | |
| 322 | nvidia,pull = <0>; | |
| 323 | nvidia,tristate = <0>; | |
| 324 | nvidia,enable-input = <0>; | |
| 325 | }; | |
| 326 | pwr_i2c_scl_pz6 { | |
| 327 | nvidia,pins = "pwr_i2c_scl_pz6", | |
| 328 | "pwr_i2c_sda_pz7"; | |
| 329 | nvidia,function = "i2cpwr"; | |
| 330 | nvidia,pull = <0>; | |
| 331 | nvidia,tristate = <0>; | |
| 332 | nvidia,enable-input = <1>; | |
| 333 | nvidia,lock = <0>; | |
| 334 | nvidia,open-drain = <0>; | |
| 335 | }; | |
| 336 | sys_clk_req_pz5 { | |
| 337 | nvidia,pins = "sys_clk_req_pz5"; | |
| 338 | nvidia,function = "sysclk"; | |
| 339 | nvidia,pull = <0>; | |
| 340 | nvidia,tristate = <0>; | |
| 341 | nvidia,enable-input = <0>; | |
| 342 | }; | |
| 343 | core_pwr_req { | |
| 344 | nvidia,pins = "core_pwr_req"; | |
| 345 | nvidia,function = "pwron"; | |
| 346 | nvidia,pull = <0>; | |
| 347 | nvidia,tristate = <0>; | |
| 348 | nvidia,enable-input = <0>; | |
| 349 | }; | |
| 350 | cpu_pwr_req { | |
| 351 | nvidia,pins = "cpu_pwr_req"; | |
| 352 | nvidia,function = "cpu"; | |
| 353 | nvidia,pull = <0>; | |
| 354 | nvidia,tristate = <0>; | |
| 355 | nvidia,enable-input = <0>; | |
| 356 | }; | |
| 357 | pwr_int_n { | |
| 358 | nvidia,pins = "pwr_int_n"; | |
| 359 | nvidia,function = "pmi"; | |
| 360 | nvidia,pull = <0>; | |
| 361 | nvidia,tristate = <1>; | |
| 362 | nvidia,enable-input = <1>; | |
| 363 | }; | |
| 364 | reset_out_n { | |
| 365 | nvidia,pins = "reset_out_n"; | |
| 366 | nvidia,function = "reset_out_n"; | |
| 367 | nvidia,pull = <0>; | |
| 368 | nvidia,tristate = <0>; | |
| 369 | nvidia,enable-input = <0>; | |
| 370 | }; | |
| 371 | clk3_out_pee0 { | |
| 372 | nvidia,pins = "clk3_out_pee0"; | |
| 373 | nvidia,function = "extperiph3"; | |
| 374 | nvidia,pull = <0>; | |
| 375 | nvidia,tristate = <0>; | |
| 376 | nvidia,enable-input = <0>; | |
| 377 | }; | |
| 378 | gen1_i2c_scl_pc4 { | |
| 379 | nvidia,pins = "gen1_i2c_scl_pc4", | |
| 380 | "gen1_i2c_sda_pc5"; | |
| 381 | nvidia,function = "i2c1"; | |
| 382 | nvidia,pull = <0>; | |
| 383 | nvidia,tristate = <0>; | |
| 384 | nvidia,enable-input = <1>; | |
| 385 | nvidia,lock = <0>; | |
| 386 | nvidia,open-drain = <0>; | |
| 387 | }; | |
| 388 | uart2_cts_n_pj5 { | |
| 389 | nvidia,pins = "uart2_cts_n_pj5"; | |
| 390 | nvidia,function = "uartb"; | |
| 391 | nvidia,pull = <0>; | |
| 392 | nvidia,tristate = <1>; | |
| 393 | nvidia,enable-input = <1>; | |
| 394 | }; | |
| 395 | uart2_rts_n_pj6 { | |
| 396 | nvidia,pins = "uart2_rts_n_pj6"; | |
| 397 | nvidia,function = "uartb"; | |
| 398 | nvidia,pull = <0>; | |
| 399 | nvidia,tristate = <0>; | |
| 400 | nvidia,enable-input = <0>; | |
| 401 | }; | |
| 402 | uart2_rxd_pc3 { | |
| 403 | nvidia,pins = "uart2_rxd_pc3"; | |
| 404 | nvidia,function = "irda"; | |
| 405 | nvidia,pull = <0>; | |
| 406 | nvidia,tristate = <1>; | |
| 407 | nvidia,enable-input = <1>; | |
| 408 | }; | |
| 409 | uart2_txd_pc2 { | |
| 410 | nvidia,pins = "uart2_txd_pc2"; | |
| 411 | nvidia,function = "irda"; | |
| 412 | nvidia,pull = <0>; | |
| 413 | nvidia,tristate = <0>; | |
| 414 | nvidia,enable-input = <0>; | |
| 415 | }; | |
| 416 | uart3_cts_n_pa1 { | |
| 417 | nvidia,pins = "uart3_cts_n_pa1", | |
| 418 | "uart3_rxd_pw7"; | |
| 419 | nvidia,function = "uartc"; | |
| 420 | nvidia,pull = <0>; | |
| 421 | nvidia,tristate = <1>; | |
| 422 | nvidia,enable-input = <1>; | |
| 423 | }; | |
| 424 | uart3_rts_n_pc0 { | |
| 425 | nvidia,pins = "uart3_rts_n_pc0", | |
| 426 | "uart3_txd_pw6"; | |
| 427 | nvidia,function = "uartc"; | |
| 428 | nvidia,pull = <0>; | |
| 429 | nvidia,tristate = <0>; | |
| 430 | nvidia,enable-input = <0>; | |
| 431 | }; | |
| 432 | owr { | |
| 433 | nvidia,pins = "owr"; | |
| 434 | nvidia,function = "owr"; | |
| 435 | nvidia,pull = <0>; | |
| 436 | nvidia,tristate = <0>; | |
| 437 | nvidia,enable-input = <1>; | |
| 438 | }; | |
| 439 | hdmi_cec_pee3 { | |
| 440 | nvidia,pins = "hdmi_cec_pee3"; | |
| 441 | nvidia,function = "cec"; | |
| 442 | nvidia,pull = <0>; | |
| 443 | nvidia,tristate = <0>; | |
| 444 | nvidia,enable-input = <1>; | |
| 445 | nvidia,lock = <0>; | |
| 446 | nvidia,open-drain = <0>; | |
| 447 | }; | |
| 448 | ddc_scl_pv4 { | |
| 449 | nvidia,pins = "ddc_scl_pv4", | |
| 450 | "ddc_sda_pv5"; | |
| 451 | nvidia,function = "i2c4"; | |
| 452 | nvidia,pull = <0>; | |
| 453 | nvidia,tristate = <0>; | |
| 454 | nvidia,enable-input = <1>; | |
| 455 | nvidia,lock = <0>; | |
| 456 | nvidia,rcv-sel = <1>; | |
| 457 | }; | |
| 458 | spdif_in_pk6 { | |
| 459 | nvidia,pins = "spdif_in_pk6"; | |
| 460 | nvidia,function = "usb"; | |
| 461 | nvidia,pull = <2>; | |
| 462 | nvidia,tristate = <0>; | |
| 463 | nvidia,enable-input = <1>; | |
| 464 | nvidia,lock = <0>; | |
| 465 | }; | |
| 466 | usb_vbus_en0_pn4 { | |
| 467 | nvidia,pins = "usb_vbus_en0_pn4"; | |
| 468 | nvidia,function = "usb"; | |
| 469 | nvidia,pull = <2>; | |
| 470 | nvidia,tristate = <0>; | |
| 471 | nvidia,enable-input = <1>; | |
| 472 | nvidia,lock = <0>; | |
| 473 | nvidia,open-drain = <1>; | |
| 474 | }; | |
| 475 | gpio_x6_aud_px6 { | |
| 476 | nvidia,pins = "gpio_x6_aud_px6"; | |
| 477 | nvidia,function = "spi6"; | |
| 478 | nvidia,pull = <2>; | |
| 479 | nvidia,tristate = <1>; | |
| 480 | nvidia,enable-input = <1>; | |
| 481 | }; | |
| 482 | gpio_x4_aud_px4 { | |
| 483 | nvidia,pins = "gpio_x4_aud_px4", | |
| 484 | "gpio_x7_aud_px7"; | |
| 485 | nvidia,function = "rsvd1"; | |
| 486 | nvidia,pull = <1>; | |
| 487 | nvidia,tristate = <0>; | |
| 488 | nvidia,enable-input = <0>; | |
| 489 | }; | |
| 490 | gpio_x5_aud_px5 { | |
| 491 | nvidia,pins = "gpio_x5_aud_px5"; | |
| 492 | nvidia,function = "rsvd1"; | |
| 493 | nvidia,pull = <2>; | |
| 494 | nvidia,tristate = <0>; | |
| 495 | nvidia,enable-input = <1>; | |
| 496 | }; | |
| 497 | gpio_w2_aud_pw2 { | |
| 498 | nvidia,pins = "gpio_w2_aud_pw2"; | |
| 499 | nvidia,function = "rsvd2"; | |
| 500 | nvidia,pull = <2>; | |
| 501 | nvidia,tristate = <0>; | |
| 502 | nvidia,enable-input = <1>; | |
| 503 | }; | |
| 504 | gpio_w3_aud_pw3 { | |
| 505 | nvidia,pins = "gpio_w3_aud_pw3"; | |
| 506 | nvidia,function = "spi6"; | |
| 507 | nvidia,pull = <2>; | |
| 508 | nvidia,tristate = <0>; | |
| 509 | nvidia,enable-input = <1>; | |
| 510 | }; | |
| 511 | gpio_x1_aud_px1 { | |
| 512 | nvidia,pins = "gpio_x1_aud_px1"; | |
| 513 | nvidia,function = "rsvd4"; | |
| 514 | nvidia,pull = <1>; | |
| 515 | nvidia,tristate = <0>; | |
| 516 | nvidia,enable-input = <1>; | |
| 517 | }; | |
| 518 | gpio_x3_aud_px3 { | |
| 519 | nvidia,pins = "gpio_x3_aud_px3"; | |
| 520 | nvidia,function = "rsvd4"; | |
| 521 | nvidia,pull = <2>; | |
| 522 | nvidia,tristate = <0>; | |
| 523 | nvidia,enable-input = <1>; | |
| 524 | }; | |
| 525 | dap3_fs_pp0 { | |
| 526 | nvidia,pins = "dap3_fs_pp0"; | |
| 527 | nvidia,function = "i2s2"; | |
| 528 | nvidia,pull = <1>; | |
| 529 | nvidia,tristate = <0>; | |
| 530 | nvidia,enable-input = <0>; | |
| 531 | }; | |
| 532 | dap3_dout_pp2 { | |
| 533 | nvidia,pins = "dap3_dout_pp2"; | |
| 534 | nvidia,function = "i2s2"; | |
| 535 | nvidia,pull = <1>; | |
| 536 | nvidia,tristate = <0>; | |
| 537 | nvidia,enable-input = <0>; | |
| 538 | }; | |
| 539 | pv1 { | |
| 540 | nvidia,pins = "pv1"; | |
| 541 | nvidia,function = "rsvd1"; | |
| 542 | nvidia,pull = <0>; | |
| 543 | nvidia,tristate = <0>; | |
| 544 | nvidia,enable-input = <1>; | |
| 545 | }; | |
| 546 | pbb3 { | |
| 547 | nvidia,pins = "pbb3", | |
| 548 | "pbb5", | |
| 549 | "pbb6", | |
| 550 | "pbb7"; | |
| 551 | nvidia,function = "rsvd4"; | |
| 552 | nvidia,pull = <1>; | |
| 553 | nvidia,tristate = <0>; | |
| 554 | nvidia,enable-input = <0>; | |
| 555 | }; | |
| 556 | pcc1 { | |
| 557 | nvidia,pins = "pcc1", | |
| 558 | "pcc2"; | |
| 559 | nvidia,function = "rsvd4"; | |
| 560 | nvidia,pull = <1>; | |
| 561 | nvidia,tristate = <0>; | |
| 562 | nvidia,enable-input = <1>; | |
| 563 | }; | |
| 564 | gmi_ad0_pg0 { | |
| 565 | nvidia,pins = "gmi_ad0_pg0", | |
| 566 | "gmi_ad1_pg1"; | |
| 567 | nvidia,function = "gmi"; | |
| 568 | nvidia,pull = <0>; | |
| 569 | nvidia,tristate = <0>; | |
| 570 | nvidia,enable-input = <0>; | |
| 571 | }; | |
| 572 | gmi_ad10_ph2 { | |
| 573 | nvidia,pins = "gmi_ad10_ph2", | |
| 574 | "gmi_ad11_ph3", | |
| 575 | "gmi_ad13_ph5", | |
| 576 | "gmi_ad8_ph0", | |
| 577 | "gmi_clk_pk1"; | |
| 578 | nvidia,function = "gmi"; | |
| 579 | nvidia,pull = <1>; | |
| 580 | nvidia,tristate = <0>; | |
| 581 | nvidia,enable-input = <0>; | |
| 582 | }; | |
| 583 | gmi_ad2_pg2 { | |
| 584 | nvidia,pins = "gmi_ad2_pg2", | |
| 585 | "gmi_ad3_pg3"; | |
| 586 | nvidia,function = "gmi"; | |
| 587 | nvidia,pull = <0>; | |
| 588 | nvidia,tristate = <0>; | |
| 589 | nvidia,enable-input = <1>; | |
| 590 | }; | |
| 591 | gmi_adv_n_pk0 { | |
| 592 | nvidia,pins = "gmi_adv_n_pk0", | |
| 593 | "gmi_cs0_n_pj0", | |
| 594 | "gmi_cs2_n_pk3", | |
| 595 | "gmi_cs4_n_pk2", | |
| 596 | "gmi_cs7_n_pi6", | |
| 597 | "gmi_dqs_p_pj3", | |
| 598 | "gmi_iordy_pi5", | |
| 599 | "gmi_wp_n_pc7"; | |
| 600 | nvidia,function = "gmi"; | |
| 601 | nvidia,pull = <2>; | |
| 602 | nvidia,tristate = <0>; | |
| 603 | nvidia,enable-input = <1>; | |
| 604 | }; | |
| 605 | gmi_cs3_n_pk4 { | |
| 606 | nvidia,pins = "gmi_cs3_n_pk4"; | |
| 607 | nvidia,function = "gmi"; | |
| 608 | nvidia,pull = <2>; | |
| 609 | nvidia,tristate = <0>; | |
| 610 | nvidia,enable-input = <0>; | |
| 611 | }; | |
| 612 | clk2_req_pcc5 { | |
| 613 | nvidia,pins = "clk2_req_pcc5"; | |
| 614 | nvidia,function = "rsvd4"; | |
| 615 | nvidia,pull = <0>; | |
| 616 | nvidia,tristate = <0>; | |
| 617 | nvidia,enable-input = <0>; | |
| 618 | }; | |
| 619 | kb_col3_pq3 { | |
| 620 | nvidia,pins = "kb_col3_pq3", | |
| 621 | "kb_col6_pq6", | |
| 622 | "kb_col7_pq7"; | |
| 623 | nvidia,function = "kbc"; | |
| 624 | nvidia,pull = <2>; | |
| 625 | nvidia,tristate = <0>; | |
| 626 | nvidia,enable-input = <0>; | |
| 627 | }; | |
| 628 | kb_col5_pq5 { | |
| 629 | nvidia,pins = "kb_col5_pq5"; | |
| 630 | nvidia,function = "kbc"; | |
| 631 | nvidia,pull = <2>; | |
| 632 | nvidia,tristate = <0>; | |
| 633 | nvidia,enable-input = <1>; | |
| 634 | }; | |
| 635 | kb_row3_pr3 { | |
| 636 | nvidia,pins = "kb_row3_pr3", | |
| 637 | "kb_row4_pr4", | |
| 638 | "kb_row6_pr6", | |
| 639 | "kb_row8_ps0"; | |
| 640 | nvidia,function = "kbc"; | |
| 641 | nvidia,pull = <1>; | |
| 642 | nvidia,tristate = <0>; | |
| 643 | nvidia,enable-input = <1>; | |
| 644 | }; | |
| 645 | clk3_req_pee1 { | |
| 646 | nvidia,pins = "clk3_req_pee1"; | |
| 647 | nvidia,function = "rsvd4"; | |
| 648 | nvidia,pull = <0>; | |
| 649 | nvidia,tristate = <0>; | |
| 650 | nvidia,enable-input = <0>; | |
| 651 | }; | |
| 652 | pu4 { | |
| 653 | nvidia,pins = "pu4"; | |
| 654 | nvidia,function = "displayb"; | |
| 655 | nvidia,pull = <0>; | |
| 656 | nvidia,tristate = <0>; | |
| 657 | nvidia,enable-input = <0>; | |
| 658 | }; | |
| 659 | pu5 { | |
| 660 | nvidia,pins = "pu5", | |
| 661 | "pu6"; | |
| 662 | nvidia,function = "displayb"; | |
| 663 | nvidia,pull = <0>; | |
| 664 | nvidia,tristate = <0>; | |
| 665 | nvidia,enable-input = <1>; | |
| 666 | }; | |
| 667 | hdmi_int_pn7 { | |
| 668 | nvidia,pins = "hdmi_int_pn7"; | |
| 669 | nvidia,function = "rsvd1"; | |
| 670 | nvidia,pull = <1>; | |
| 671 | nvidia,tristate = <0>; | |
| 672 | nvidia,enable-input = <1>; | |
| 673 | }; | |
| 674 | clk1_req_pee2 { | |
| 675 | nvidia,pins = "clk1_req_pee2", | |
| 676 | "usb_vbus_en1_pn5"; | |
| 677 | nvidia,function = "rsvd4"; | |
| 678 | nvidia,pull = <1>; | |
| 679 | nvidia,tristate = <1>; | |
| 680 | nvidia,enable-input = <0>; | |
| 681 | }; | |
| 682 | ||
| 683 | drive_sdio1 { | |
| 684 | nvidia,pins = "drive_sdio1"; | |
| 685 | nvidia,high-speed-mode = <1>; | |
| 686 | nvidia,schmitt = <0>; | |
| 687 | nvidia,low-power-mode = <3>; | |
| 688 | nvidia,pull-down-strength = <36>; | |
| 689 | nvidia,pull-up-strength = <20>; | |
| 690 | nvidia,slew-rate-rising = <2>; | |
| 691 | nvidia,slew-rate-falling = <2>; | |
| 692 | }; | |
| 693 | drive_sdio3 { | |
| 694 | nvidia,pins = "drive_sdio3"; | |
| 695 | nvidia,high-speed-mode = <1>; | |
| 696 | nvidia,schmitt = <0>; | |
| 697 | nvidia,low-power-mode = <3>; | |
| 698 | nvidia,pull-down-strength = <22>; | |
| 699 | nvidia,pull-up-strength = <36>; | |
| 700 | nvidia,slew-rate-rising = <0>; | |
| 701 | nvidia,slew-rate-falling = <0>; | |
| 702 | }; | |
| 703 | drive_gma { | |
| 704 | nvidia,pins = "drive_gma"; | |
| 705 | nvidia,high-speed-mode = <1>; | |
| 706 | nvidia,schmitt = <0>; | |
| 707 | nvidia,low-power-mode = <3>; | |
| 708 | nvidia,pull-down-strength = <2>; | |
| 709 | nvidia,pull-up-strength = <1>; | |
| 710 | nvidia,slew-rate-rising = <0>; | |
| 711 | nvidia,slew-rate-falling = <0>; | |
| 712 | nvidia,drive-type = <1>; | |
| 713 | }; | |
| 714 | }; | |
| 715 | }; | |
| 716 | ||
| a71c03e7 HD |
717 | serial@70006300 { |
| 718 | status = "okay"; | |
| a71c03e7 HD |
719 | }; |
| 720 | ||
| 33eb271e RK |
721 | i2c@7000c000 { |
| 722 | status = "okay"; | |
| 723 | clock-frequency = <100000>; | |
| 724 | ||
| 725 | battery: smart-battery { | |
| 726 | compatible = "ti,bq20z45", "sbs,sbs-battery"; | |
| 727 | reg = <0xb>; | |
| 728 | battery-name = "battery"; | |
| 729 | sbs,i2c-retry-count = <2>; | |
| 730 | sbs,poll-retry-count = <100>; | |
| d5284a67 | 731 | power-supplies = <&charger>; |
| 33eb271e | 732 | }; |
| aa5ae424 SW |
733 | |
| 734 | rt5640: rt5640 { | |
| 735 | compatible = "realtek,rt5640"; | |
| 736 | reg = <0x1c>; | |
| 737 | interrupt-parent = <&gpio>; | |
| 738 | interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>; | |
| 739 | realtek,ldo1-en-gpios = | |
| 740 | <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; | |
| 741 | }; | |
| 99bda7b9 WN |
742 | |
| 743 | temperature-sensor@4c { | |
| 744 | compatible = "onnn,nct1008"; | |
| 745 | reg = <0x4c>; | |
| 746 | vcc-supply = <&palmas_ldo6_reg>; | |
| 747 | interrupt-parent = <&gpio>; | |
| 748 | interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>; | |
| 749 | }; | |
| 33eb271e RK |
750 | }; |
| 751 | ||
| da204ee2 LD |
752 | i2c@7000d000 { |
| 753 | status = "okay"; | |
| 754 | clock-frequency = <400000>; | |
| 755 | ||
| 756 | tps51632 { | |
| 757 | compatible = "ti,tps51632"; | |
| 758 | reg = <0x43>; | |
| 759 | regulator-name = "vdd-cpu"; | |
| 760 | regulator-min-microvolt = <500000>; | |
| 761 | regulator-max-microvolt = <1520000>; | |
| 762 | regulator-boot-on; | |
| 763 | regulator-always-on; | |
| 764 | }; | |
| 81c6c56c LD |
765 | |
| 766 | tps65090 { | |
| 767 | compatible = "ti,tps65090"; | |
| 768 | reg = <0x48>; | |
| 769 | interrupt-parent = <&gpio>; | |
| 6cecf916 | 770 | interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>; |
| 81c6c56c LD |
771 | |
| 772 | vsys1-supply = <&vdd_ac_bat_reg>; | |
| 773 | vsys2-supply = <&vdd_ac_bat_reg>; | |
| 774 | vsys3-supply = <&vdd_ac_bat_reg>; | |
| 775 | infet1-supply = <&vdd_ac_bat_reg>; | |
| 776 | infet2-supply = <&vdd_ac_bat_reg>; | |
| 777 | infet3-supply = <&tps65090_dcdc2_reg>; | |
| 778 | infet4-supply = <&tps65090_dcdc2_reg>; | |
| 779 | infet5-supply = <&tps65090_dcdc2_reg>; | |
| 780 | infet6-supply = <&tps65090_dcdc2_reg>; | |
| 781 | infet7-supply = <&tps65090_dcdc2_reg>; | |
| 782 | vsys-l1-supply = <&vdd_ac_bat_reg>; | |
| 783 | vsys-l2-supply = <&vdd_ac_bat_reg>; | |
| 784 | ||
| d5284a67 | 785 | charger: charger { |
| 1a99ece9 RK |
786 | compatible = "ti,tps65090-charger"; |
| 787 | ti,enable-low-current-chrg; | |
| 788 | }; | |
| 789 | ||
| 81c6c56c | 790 | regulators { |
| fcf0b3a6 | 791 | tps65090_dcdc1_reg: dcdc1 { |
| 81c6c56c LD |
792 | regulator-name = "vdd-sys-5v0"; |
| 793 | regulator-always-on; | |
| 794 | regulator-boot-on; | |
| 795 | }; | |
| 796 | ||
| 797 | tps65090_dcdc2_reg: dcdc2 { | |
| 798 | regulator-name = "vdd-sys-3v3"; | |
| 799 | regulator-always-on; | |
| 800 | regulator-boot-on; | |
| 801 | }; | |
| 802 | ||
| c321d968 | 803 | tps65090_dcdc3_reg: dcdc3 { |
| 81c6c56c LD |
804 | regulator-name = "vdd-ao"; |
| 805 | regulator-always-on; | |
| 806 | regulator-boot-on; | |
| 807 | }; | |
| 808 | ||
| 809 | fet1 { | |
| 810 | regulator-name = "vdd-lcd-bl"; | |
| 811 | }; | |
| 812 | ||
| 813 | fet3 { | |
| 814 | regulator-name = "vdd-modem-3v3"; | |
| 815 | }; | |
| 816 | ||
| 817 | fet4 { | |
| 818 | regulator-name = "avdd-lcd"; | |
| 819 | }; | |
| 820 | ||
| 821 | fet5 { | |
| 822 | regulator-name = "vdd-lvds"; | |
| 823 | }; | |
| 824 | ||
| 825 | fet6 { | |
| 826 | regulator-name = "vdd-sd-slot"; | |
| 15d5ef4d | 827 | regulator-always-on; |
| 81c6c56c LD |
828 | regulator-boot-on; |
| 829 | }; | |
| 830 | ||
| 831 | fet7 { | |
| 832 | regulator-name = "vdd-com-3v3"; | |
| 833 | }; | |
| 834 | ||
| 835 | ldo1 { | |
| 836 | regulator-name = "vdd-sby-5v0"; | |
| 837 | regulator-always-on; | |
| 838 | regulator-boot-on; | |
| 839 | }; | |
| 840 | ||
| 841 | ldo2 { | |
| 842 | regulator-name = "vdd-sby-3v3"; | |
| 843 | regulator-always-on; | |
| 844 | regulator-boot-on; | |
| 845 | }; | |
| 846 | }; | |
| 847 | }; | |
| c321d968 LD |
848 | |
| 849 | palmas: tps65913 { | |
| 850 | compatible = "ti,palmas"; | |
| 851 | reg = <0x58>; | |
| eca8f98e | 852 | interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>; |
| c321d968 LD |
853 | |
| 854 | #interrupt-cells = <2>; | |
| 855 | interrupt-controller; | |
| 856 | ||
| 27cf5d14 BH |
857 | ti,system-power-controller; |
| 858 | ||
| c321d968 LD |
859 | palmas_gpio: gpio { |
| 860 | compatible = "ti,palmas-gpio"; | |
| 861 | gpio-controller; | |
| 862 | #gpio-cells = <2>; | |
| 863 | }; | |
| 864 | ||
| 865 | pmic { | |
| 866 | compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; | |
| 867 | smps1-in-supply = <&tps65090_dcdc3_reg>; | |
| 868 | smps3-in-supply = <&tps65090_dcdc3_reg>; | |
| 869 | smps4-in-supply = <&tps65090_dcdc2_reg>; | |
| 870 | smps7-in-supply = <&tps65090_dcdc2_reg>; | |
| 871 | smps8-in-supply = <&tps65090_dcdc2_reg>; | |
| 872 | smps9-in-supply = <&tps65090_dcdc2_reg>; | |
| 873 | ldo1-in-supply = <&tps65090_dcdc2_reg>; | |
| 874 | ldo2-in-supply = <&tps65090_dcdc2_reg>; | |
| 875 | ldo3-in-supply = <&palmas_smps3_reg>; | |
| 876 | ldo4-in-supply = <&tps65090_dcdc2_reg>; | |
| 877 | ldo5-in-supply = <&vdd_ac_bat_reg>; | |
| 878 | ldo6-in-supply = <&tps65090_dcdc2_reg>; | |
| 879 | ldo7-in-supply = <&tps65090_dcdc2_reg>; | |
| 880 | ldo8-in-supply = <&tps65090_dcdc3_reg>; | |
| 881 | ldo9-in-supply = <&palmas_smps9_reg>; | |
| 882 | ldoln-in-supply = <&tps65090_dcdc1_reg>; | |
| 883 | ldousb-in-supply = <&tps65090_dcdc1_reg>; | |
| 884 | ||
| 885 | regulators { | |
| 886 | smps12 { | |
| 887 | regulator-name = "vddio-ddr"; | |
| 888 | regulator-min-microvolt = <1350000>; | |
| 889 | regulator-max-microvolt = <1350000>; | |
| 890 | regulator-always-on; | |
| 891 | regulator-boot-on; | |
| 892 | }; | |
| 893 | ||
| 894 | palmas_smps3_reg: smps3 { | |
| 895 | regulator-name = "vddio-1v8"; | |
| 896 | regulator-min-microvolt = <1800000>; | |
| 897 | regulator-max-microvolt = <1800000>; | |
| 898 | regulator-always-on; | |
| 899 | regulator-boot-on; | |
| 900 | }; | |
| 901 | ||
| 902 | smps45 { | |
| 903 | regulator-name = "vdd-core"; | |
| 904 | regulator-min-microvolt = <900000>; | |
| 905 | regulator-max-microvolt = <1400000>; | |
| 906 | regulator-always-on; | |
| 907 | regulator-boot-on; | |
| 908 | }; | |
| 909 | ||
| 910 | smps457 { | |
| 911 | regulator-name = "vdd-core"; | |
| 912 | regulator-min-microvolt = <900000>; | |
| 913 | regulator-max-microvolt = <1400000>; | |
| 914 | regulator-always-on; | |
| 915 | regulator-boot-on; | |
| 916 | }; | |
| 917 | ||
| 918 | smps8 { | |
| 919 | regulator-name = "avdd-pll"; | |
| 920 | regulator-min-microvolt = <1050000>; | |
| 921 | regulator-max-microvolt = <1050000>; | |
| 922 | regulator-always-on; | |
| 923 | regulator-boot-on; | |
| 924 | }; | |
| 925 | ||
| 926 | palmas_smps9_reg: smps9 { | |
| 927 | regulator-name = "sdhci-vdd-sd-slot"; | |
| 928 | regulator-min-microvolt = <2800000>; | |
| 929 | regulator-max-microvolt = <2800000>; | |
| 930 | regulator-always-on; | |
| 931 | }; | |
| 932 | ||
| 933 | ldo1 { | |
| 934 | regulator-name = "avdd-cam1"; | |
| 935 | regulator-min-microvolt = <2800000>; | |
| 936 | regulator-max-microvolt = <2800000>; | |
| 937 | }; | |
| 938 | ||
| 939 | ldo2 { | |
| 940 | regulator-name = "avdd-cam2"; | |
| 941 | regulator-min-microvolt = <2800000>; | |
| 942 | regulator-max-microvolt = <2800000>; | |
| 943 | }; | |
| 944 | ||
| 945 | ldo3 { | |
| 946 | regulator-name = "avdd-dsi-csi"; | |
| 947 | regulator-min-microvolt = <1200000>; | |
| 948 | regulator-max-microvolt = <1200000>; | |
| 949 | regulator-always-on; | |
| 950 | regulator-boot-on; | |
| 951 | }; | |
| 952 | ||
| 953 | ldo4 { | |
| 954 | regulator-name = "vpp-fuse"; | |
| 955 | regulator-min-microvolt = <1800000>; | |
| 956 | regulator-max-microvolt = <1800000>; | |
| 957 | }; | |
| 958 | ||
| 99bda7b9 | 959 | palmas_ldo6_reg: ldo6 { |
| c321d968 LD |
960 | regulator-name = "vdd-sensor-2v85"; |
| 961 | regulator-min-microvolt = <2850000>; | |
| 962 | regulator-max-microvolt = <2850000>; | |
| 963 | }; | |
| 964 | ||
| 965 | ldo7 { | |
| 966 | regulator-name = "vdd-af-cam1"; | |
| 967 | regulator-min-microvolt = <2800000>; | |
| 968 | regulator-max-microvolt = <2800000>; | |
| 969 | }; | |
| 970 | ||
| 971 | ldo8 { | |
| 972 | regulator-name = "vdd-rtc"; | |
| 973 | regulator-min-microvolt = <900000>; | |
| 974 | regulator-max-microvolt = <900000>; | |
| 975 | regulator-always-on; | |
| 976 | regulator-boot-on; | |
| 977 | ti,enable-ldo8-tracking; | |
| 978 | }; | |
| 979 | ||
| 980 | ldo9 { | |
| 981 | regulator-name = "vddio-sdmmc-2"; | |
| 982 | regulator-min-microvolt = <1800000>; | |
| 983 | regulator-max-microvolt = <3300000>; | |
| 984 | regulator-always-on; | |
| 985 | regulator-boot-on; | |
| 986 | }; | |
| 987 | ||
| 988 | ldoln { | |
| 989 | regulator-name = "hvdd-usb"; | |
| 990 | regulator-min-microvolt = <3300000>; | |
| 991 | regulator-max-microvolt = <3300000>; | |
| 992 | }; | |
| 993 | ||
| 994 | ldousb { | |
| 995 | regulator-name = "avdd-usb"; | |
| 996 | regulator-min-microvolt = <3300000>; | |
| 997 | regulator-max-microvolt = <3300000>; | |
| 998 | regulator-always-on; | |
| 999 | regulator-boot-on; | |
| 1000 | }; | |
| 1001 | ||
| 1002 | regen1 { | |
| 1003 | regulator-name = "rail-3v3"; | |
| 1004 | regulator-max-microvolt = <3300000>; | |
| 1005 | regulator-always-on; | |
| 1006 | regulator-boot-on; | |
| 1007 | }; | |
| 1008 | ||
| 1009 | regen2 { | |
| 1010 | regulator-name = "rail-5v0"; | |
| 1011 | regulator-max-microvolt = <5000000>; | |
| 1012 | regulator-always-on; | |
| 1013 | regulator-boot-on; | |
| 1014 | }; | |
| 1015 | }; | |
| 1016 | }; | |
| 1017 | ||
| 1018 | rtc { | |
| 1019 | compatible = "ti,palmas-rtc"; | |
| 1020 | interrupt-parent = <&palmas>; | |
| 1021 | interrupts = <8 0>; | |
| 1022 | }; | |
| 6be3cf72 LD |
1023 | |
| 1024 | pinmux { | |
| 1025 | compatible = "ti,tps65913-pinctrl"; | |
| 1026 | pinctrl-names = "default"; | |
| 1027 | pinctrl-0 = <&palmas_default>; | |
| 1028 | ||
| 1029 | palmas_default: pinmux { | |
| 1030 | pin_gpio6 { | |
| 1031 | pins = "gpio6"; | |
| 1032 | function = "gpio"; | |
| 1033 | }; | |
| 1034 | }; | |
| 1035 | }; | |
| c321d968 | 1036 | }; |
| da204ee2 LD |
1037 | }; |
| 1038 | ||
| 5cc75fca LD |
1039 | spi@7000da00 { |
| 1040 | status = "okay"; | |
| 1041 | spi-max-frequency = <25000000>; | |
| 1042 | spi-flash@0 { | |
| 1043 | compatible = "winbond,w25q32dw"; | |
| 1044 | reg = <0>; | |
| 1045 | spi-max-frequency = <20000000>; | |
| 1046 | }; | |
| 1047 | }; | |
| 1048 | ||
| a71c03e7 HD |
1049 | pmc { |
| 1050 | nvidia,invert-interrupt; | |
| 47d2d63b | 1051 | nvidia,suspend-mode = <1>; |
| 4a7658fe JL |
1052 | nvidia,cpu-pwr-good-time = <500>; |
| 1053 | nvidia,cpu-pwr-off-time = <300>; | |
| 1054 | nvidia,core-pwr-good-time = <641 3845>; | |
| 1055 | nvidia,core-pwr-off-time = <61036>; | |
| 1056 | nvidia,core-power-req-active-high; | |
| 1057 | nvidia,sys-clock-req-active-high; | |
| a71c03e7 | 1058 | }; |
| 7021d122 | 1059 | |
| aa5ae424 SW |
1060 | ahub { |
| 1061 | i2s@70080400 { | |
| 1062 | status = "okay"; | |
| 1063 | }; | |
| 1064 | }; | |
| 1065 | ||
| 8d3207ca | 1066 | sdhci@78000400 { |
| 3325f1bc | 1067 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
| 8d3207ca RK |
1068 | bus-width = <4>; |
| 1069 | status = "okay"; | |
| 1070 | }; | |
| 1071 | ||
| 1072 | sdhci@78000600 { | |
| 1073 | bus-width = <8>; | |
| 1074 | status = "okay"; | |
| 7a2617a6 | 1075 | non-removable; |
| 8d3207ca RK |
1076 | }; |
| 1077 | ||
| 328dc0ec MP |
1078 | usb@7d008000 { |
| 1079 | status = "okay"; | |
| 1080 | }; | |
| 1081 | ||
| 1082 | usb-phy@7d008000 { | |
| 1083 | status = "okay"; | |
| 1084 | vbus-supply = <&usb3_vbus_reg>; | |
| 1085 | }; | |
| 1086 | ||
| 7021d122 JL |
1087 | clocks { |
| 1088 | compatible = "simple-bus"; | |
| 1089 | #address-cells = <1>; | |
| 1090 | #size-cells = <0>; | |
| 1091 | ||
| 1092 | clk32k_in: clock { | |
| 1093 | compatible = "fixed-clock"; | |
| 1094 | reg=<0>; | |
| 1095 | #clock-cells = <0>; | |
| 1096 | clock-frequency = <32768>; | |
| 1097 | }; | |
| 1098 | }; | |
| 81c6c56c | 1099 | |
| 21b341ca LD |
1100 | gpio-keys { |
| 1101 | compatible = "gpio-keys"; | |
| 1102 | ||
| 1103 | home { | |
| 1104 | label = "Home"; | |
| 1105 | gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; | |
| e6e646e6 | 1106 | linux,code = <KEY_HOME>; |
| 21b341ca LD |
1107 | }; |
| 1108 | ||
| 1109 | power { | |
| 1110 | label = "Power"; | |
| 1111 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; | |
| e6e646e6 | 1112 | linux,code = <KEY_POWER>; |
| 21b341ca LD |
1113 | gpio-key,wakeup; |
| 1114 | }; | |
| 1115 | ||
| 1116 | volume_down { | |
| 1117 | label = "Volume Down"; | |
| 1118 | gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; | |
| e6e646e6 | 1119 | linux,code = <KEY_VOLUMEDOWN>; |
| 21b341ca LD |
1120 | }; |
| 1121 | ||
| 1122 | volume_up { | |
| 1123 | label = "Volume Up"; | |
| 1124 | gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; | |
| e6e646e6 | 1125 | linux,code = <KEY_VOLUMEUP>; |
| 21b341ca LD |
1126 | }; |
| 1127 | }; | |
| 1128 | ||
| 81c6c56c LD |
1129 | regulators { |
| 1130 | compatible = "simple-bus"; | |
| 1131 | #address-cells = <1>; | |
| 1132 | #size-cells = <0>; | |
| 1133 | ||
| 1134 | vdd_ac_bat_reg: regulator@0 { | |
| 1135 | compatible = "regulator-fixed"; | |
| 1136 | reg = <0>; | |
| 1137 | regulator-name = "vdd_ac_bat"; | |
| 1138 | regulator-min-microvolt = <5000000>; | |
| 1139 | regulator-max-microvolt = <5000000>; | |
| 1140 | regulator-always-on; | |
| 1141 | }; | |
| fcf0b3a6 LD |
1142 | |
| 1143 | dvdd_ts_reg: regulator@1 { | |
| 1144 | compatible = "regulator-fixed"; | |
| 1145 | reg = <1>; | |
| 1146 | regulator-name = "dvdd_ts"; | |
| 1147 | regulator-min-microvolt = <1800000>; | |
| 1148 | regulator-max-microvolt = <1800000>; | |
| 1149 | enable-active-high; | |
| 3325f1bc | 1150 | gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; |
| fcf0b3a6 LD |
1151 | }; |
| 1152 | ||
| 1153 | lcd_bl_en_reg: regulator@2 { | |
| 1154 | compatible = "regulator-fixed"; | |
| 1155 | reg = <2>; | |
| 1156 | regulator-name = "lcd_bl_en"; | |
| 1157 | regulator-min-microvolt = <5000000>; | |
| 1158 | regulator-max-microvolt = <5000000>; | |
| 1159 | enable-active-high; | |
| 3325f1bc | 1160 | gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; |
| fcf0b3a6 LD |
1161 | }; |
| 1162 | ||
| 1163 | usb1_vbus_reg: regulator@3 { | |
| 1164 | compatible = "regulator-fixed"; | |
| 1165 | reg = <3>; | |
| 1166 | regulator-name = "usb1_vbus"; | |
| 1167 | regulator-min-microvolt = <5000000>; | |
| 1168 | regulator-max-microvolt = <5000000>; | |
| 1169 | enable-active-high; | |
| 3325f1bc | 1170 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; |
| fcf0b3a6 LD |
1171 | gpio-open-drain; |
| 1172 | vin-supply = <&tps65090_dcdc1_reg>; | |
| 1173 | }; | |
| 1174 | ||
| 1175 | usb3_vbus_reg: regulator@4 { | |
| 1176 | compatible = "regulator-fixed"; | |
| 1177 | reg = <4>; | |
| 1178 | regulator-name = "usb2_vbus"; | |
| 1179 | regulator-min-microvolt = <5000000>; | |
| 1180 | regulator-max-microvolt = <5000000>; | |
| 1181 | enable-active-high; | |
| 3325f1bc | 1182 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; |
| fcf0b3a6 LD |
1183 | gpio-open-drain; |
| 1184 | vin-supply = <&tps65090_dcdc1_reg>; | |
| 1185 | }; | |
| 1186 | ||
| 1187 | vdd_hdmi_reg: regulator@5 { | |
| 1188 | compatible = "regulator-fixed"; | |
| 1189 | reg = <5>; | |
| 1190 | regulator-name = "vdd_hdmi_5v0"; | |
| 1191 | regulator-min-microvolt = <5000000>; | |
| 1192 | regulator-max-microvolt = <5000000>; | |
| 1193 | enable-active-high; | |
| 3325f1bc | 1194 | gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; |
| fcf0b3a6 LD |
1195 | vin-supply = <&tps65090_dcdc1_reg>; |
| 1196 | }; | |
| c321d968 LD |
1197 | |
| 1198 | vdd_cam_1v8_reg: regulator@6 { | |
| 1199 | compatible = "regulator-fixed"; | |
| 1200 | reg = <6>; | |
| 1201 | regulator-name = "vdd_cam_1v8_reg"; | |
| 1202 | regulator-min-microvolt = <1800000>; | |
| 1203 | regulator-max-microvolt = <1800000>; | |
| 1204 | enable-active-high; | |
| 1205 | gpio = <&palmas_gpio 6 0>; | |
| 1206 | }; | |
| 81c6c56c | 1207 | }; |
| aa5ae424 SW |
1208 | |
| 1209 | sound { | |
| 1210 | compatible = "nvidia,tegra-audio-rt5640-dalmore", | |
| 1211 | "nvidia,tegra-audio-rt5640"; | |
| 1212 | nvidia,model = "NVIDIA Tegra Dalmore"; | |
| 1213 | ||
| 1214 | nvidia,audio-routing = | |
| 1215 | "Headphones", "HPOR", | |
| 1216 | "Headphones", "HPOL", | |
| 1217 | "Speakers", "SPORP", | |
| 1218 | "Speakers", "SPORN", | |
| 1219 | "Speakers", "SPOLP", | |
| 8af3bbec SW |
1220 | "Speakers", "SPOLN", |
| 1221 | "Mic Jack", "MICBIAS1", | |
| 1222 | "IN2P", "Mic Jack"; | |
| aa5ae424 SW |
1223 | |
| 1224 | nvidia,i2s-controller = <&tegra_i2s1>; | |
| 1225 | nvidia,audio-codec = <&rt5640>; | |
| 1226 | ||
| 1227 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; | |
| 1228 | ||
| 1229 | clocks = <&tegra_car TEGRA114_CLK_PLL_A>, | |
| 1230 | <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, | |
| 1231 | <&tegra_car TEGRA114_CLK_EXTERN1>; | |
| 1232 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
| 1233 | }; | |
| a71c03e7 | 1234 | }; |