Commit | Line | Data |
---|---|---|
59fe02cb TV |
1 | /dts-v1/; |
2 | ||
3 | #include "tegra124-nyan.dtsi" | |
4 | ||
03650bd2 TV |
5 | #include "tegra124-nyan-blaze-emc.dtsi" |
6 | ||
59fe02cb TV |
7 | / { |
8 | model = "HP Chromebook 14"; | |
9 | compatible = "google,nyan-blaze", "google,nyan", "nvidia,tegra124"; | |
10 | ||
11 | panel: panel { | |
12 | compatible = "samsung,ltn140at29-301"; | |
13 | ||
14 | backlight = <&backlight>; | |
15 | ddc-i2c-bus = <&dpaux>; | |
16 | }; | |
17 | ||
18 | sound { | |
19 | compatible = "nvidia,tegra-audio-max98090-nyan-blaze", | |
20 | "nvidia,tegra-audio-max98090-nyan", | |
21 | "nvidia,tegra-audio-max98090"; | |
22 | nvidia,model = "GoogleNyanBlaze"; | |
23 | }; | |
24 | ||
25 | pinmux@0,70000868 { | |
26 | pinctrl-names = "default"; | |
27 | pinctrl-0 = <&pinmux_default>; | |
28 | ||
29 | pinmux_default: common { | |
30 | clk_32k_out_pa0 { | |
31 | nvidia,pins = "clk_32k_out_pa0"; | |
32 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
33 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
34 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
35 | }; | |
36 | uart3_cts_n_pa1 { | |
37 | nvidia,pins = "uart3_cts_n_pa1"; | |
38 | nvidia,function = "gmi"; | |
39 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
40 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
41 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
42 | }; | |
43 | dap2_fs_pa2 { | |
44 | nvidia,pins = "dap2_fs_pa2"; | |
45 | nvidia,function = "i2s1"; | |
46 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
47 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
48 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
49 | }; | |
50 | dap2_sclk_pa3 { | |
51 | nvidia,pins = "dap2_sclk_pa3"; | |
52 | nvidia,function = "i2s1"; | |
53 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
54 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
55 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
56 | }; | |
57 | dap2_din_pa4 { | |
58 | nvidia,pins = "dap2_din_pa4"; | |
59 | nvidia,function = "i2s1"; | |
60 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
61 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
62 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
63 | }; | |
64 | dap2_dout_pa5 { | |
65 | nvidia,pins = "dap2_dout_pa5"; | |
66 | nvidia,function = "i2s1"; | |
67 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
68 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
69 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
70 | }; | |
71 | sdmmc3_clk_pa6 { | |
72 | nvidia,pins = "sdmmc3_clk_pa6"; | |
73 | nvidia,function = "sdmmc3"; | |
74 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
75 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
76 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
77 | }; | |
78 | sdmmc3_cmd_pa7 { | |
79 | nvidia,pins = "sdmmc3_cmd_pa7"; | |
80 | nvidia,function = "sdmmc3"; | |
81 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
82 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
83 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
84 | }; | |
85 | pb0 { | |
86 | nvidia,pins = "pb0"; | |
87 | nvidia,function = "rsvd2"; | |
88 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
89 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
90 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
91 | }; | |
92 | pb1 { | |
93 | nvidia,pins = "pb1"; | |
94 | nvidia,function = "rsvd2"; | |
95 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
96 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
97 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
98 | }; | |
99 | sdmmc3_dat3_pb4 { | |
100 | nvidia,pins = "sdmmc3_dat3_pb4"; | |
101 | nvidia,function = "sdmmc3"; | |
102 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
103 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
104 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
105 | }; | |
106 | sdmmc3_dat2_pb5 { | |
107 | nvidia,pins = "sdmmc3_dat2_pb5"; | |
108 | nvidia,function = "sdmmc3"; | |
109 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
110 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
111 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
112 | }; | |
113 | sdmmc3_dat1_pb6 { | |
114 | nvidia,pins = "sdmmc3_dat1_pb6"; | |
115 | nvidia,function = "sdmmc3"; | |
116 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
117 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
118 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
119 | }; | |
120 | sdmmc3_dat0_pb7 { | |
121 | nvidia,pins = "sdmmc3_dat0_pb7"; | |
122 | nvidia,function = "sdmmc3"; | |
123 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
124 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
125 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
126 | }; | |
127 | uart3_rts_n_pc0 { | |
128 | nvidia,pins = "uart3_rts_n_pc0"; | |
129 | nvidia,function = "gmi"; | |
130 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
131 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
132 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
133 | }; | |
134 | uart2_txd_pc2 { | |
135 | nvidia,pins = "uart2_txd_pc2"; | |
136 | nvidia,function = "irda"; | |
137 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
138 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
139 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
140 | }; | |
141 | uart2_rxd_pc3 { | |
142 | nvidia,pins = "uart2_rxd_pc3"; | |
143 | nvidia,function = "irda"; | |
144 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
145 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
146 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
147 | }; | |
148 | gen1_i2c_scl_pc4 { | |
149 | nvidia,pins = "gen1_i2c_scl_pc4"; | |
150 | nvidia,function = "i2c1"; | |
151 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
152 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
153 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
154 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
155 | }; | |
156 | gen1_i2c_sda_pc5 { | |
157 | nvidia,pins = "gen1_i2c_sda_pc5"; | |
158 | nvidia,function = "i2c1"; | |
159 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
160 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
161 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
162 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
163 | }; | |
164 | pc7 { | |
165 | nvidia,pins = "pc7"; | |
166 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
167 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
168 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
169 | }; | |
170 | pg0 { | |
171 | nvidia,pins = "pg0"; | |
172 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
173 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
174 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
175 | }; | |
176 | pg1 { | |
177 | nvidia,pins = "pg1"; | |
178 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
179 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
180 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
181 | }; | |
182 | pg2 { | |
183 | nvidia,pins = "pg2"; | |
184 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
185 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
186 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
187 | }; | |
188 | pg3 { | |
189 | nvidia,pins = "pg3"; | |
190 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
191 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
192 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
193 | }; | |
194 | pg4 { | |
195 | nvidia,pins = "pg4"; | |
196 | nvidia,function = "spi4"; | |
197 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
198 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
199 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
200 | }; | |
201 | pg5 { | |
202 | nvidia,pins = "pg5"; | |
203 | nvidia,function = "spi4"; | |
204 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
205 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
206 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
207 | }; | |
208 | pg6 { | |
209 | nvidia,pins = "pg6"; | |
210 | nvidia,function = "spi4"; | |
211 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
212 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
213 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
214 | }; | |
215 | pg7 { | |
216 | nvidia,pins = "pg7"; | |
217 | nvidia,function = "spi4"; | |
218 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
219 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
220 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
221 | }; | |
222 | ph0 { | |
223 | nvidia,pins = "ph0"; | |
224 | nvidia,function = "gmi"; | |
225 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
226 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
227 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
228 | }; | |
229 | ph1 { | |
230 | nvidia,pins = "ph1"; | |
231 | nvidia,function = "pwm1"; | |
232 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
233 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
234 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
235 | }; | |
236 | ph2 { | |
237 | nvidia,pins = "ph2"; | |
238 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
239 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
240 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
241 | }; | |
242 | ph3 { | |
243 | nvidia,pins = "ph3"; | |
244 | nvidia,function = "gmi"; | |
245 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
246 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
247 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
248 | }; | |
249 | ph4 { | |
250 | nvidia,pins = "ph4"; | |
251 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
252 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
253 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
254 | }; | |
255 | ph5 { | |
256 | nvidia,pins = "ph5"; | |
257 | nvidia,function = "rsvd2"; | |
258 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
259 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
260 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
261 | }; | |
262 | ph6 { | |
263 | nvidia,pins = "ph6"; | |
264 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
265 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
266 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
267 | }; | |
268 | ph7 { | |
269 | nvidia,pins = "ph7"; | |
270 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
271 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
272 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
273 | }; | |
274 | pi0 { | |
275 | nvidia,pins = "pi0"; | |
276 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
277 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
278 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
279 | }; | |
280 | pi1 { | |
281 | nvidia,pins = "pi1"; | |
282 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
283 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
284 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
285 | }; | |
286 | pi2 { | |
287 | nvidia,pins = "pi2"; | |
288 | nvidia,function = "rsvd4"; | |
289 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
290 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
291 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
292 | }; | |
293 | pi3 { | |
294 | nvidia,pins = "pi3"; | |
295 | nvidia,function = "spi4"; | |
296 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
297 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
298 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
299 | }; | |
300 | pi4 { | |
301 | nvidia,pins = "pi4"; | |
302 | nvidia,function = "gmi"; | |
303 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
304 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
305 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
306 | }; | |
307 | pi5 { | |
308 | nvidia,pins = "pi5"; | |
309 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
310 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
311 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
312 | }; | |
313 | pi6 { | |
314 | nvidia,pins = "pi6"; | |
315 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
316 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
317 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
318 | }; | |
319 | pi7 { | |
320 | nvidia,pins = "pi7"; | |
321 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
322 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
323 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
324 | }; | |
325 | pj0 { | |
326 | nvidia,pins = "pj0"; | |
327 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
328 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
329 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
330 | }; | |
331 | pj2 { | |
332 | nvidia,pins = "pj2"; | |
333 | nvidia,function = "rsvd1"; | |
334 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
335 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
336 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
337 | }; | |
338 | uart2_cts_n_pj5 { | |
339 | nvidia,pins = "uart2_cts_n_pj5"; | |
340 | nvidia,function = "gmi"; | |
341 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
342 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
343 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
344 | }; | |
345 | uart2_rts_n_pj6 { | |
346 | nvidia,pins = "uart2_rts_n_pj6"; | |
347 | nvidia,function = "gmi"; | |
348 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
349 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
350 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
351 | }; | |
352 | pj7 { | |
353 | nvidia,pins = "pj7"; | |
354 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
355 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
356 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
357 | }; | |
358 | pk0 { | |
359 | nvidia,pins = "pk0"; | |
360 | nvidia,function = "rsvd1"; | |
361 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
362 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
363 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
364 | }; | |
365 | pk1 { | |
366 | nvidia,pins = "pk1"; | |
367 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
368 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
369 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
370 | }; | |
371 | pk2 { | |
372 | nvidia,pins = "pk2"; | |
373 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
374 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
375 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
376 | }; | |
377 | pk3 { | |
378 | nvidia,pins = "pk3"; | |
379 | nvidia,function = "gmi"; | |
380 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
381 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
382 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
383 | }; | |
384 | pk4 { | |
385 | nvidia,pins = "pk4"; | |
386 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
387 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
388 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
389 | }; | |
390 | spdif_out_pk5 { | |
391 | nvidia,pins = "spdif_out_pk5"; | |
392 | nvidia,function = "rsvd2"; | |
393 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
394 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
395 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
396 | }; | |
397 | spdif_in_pk6 { | |
398 | nvidia,pins = "spdif_in_pk6"; | |
399 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
400 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
401 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
402 | }; | |
403 | pk7 { | |
404 | nvidia,pins = "pk7"; | |
405 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
406 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
407 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
408 | }; | |
409 | dap1_fs_pn0 { | |
410 | nvidia,pins = "dap1_fs_pn0"; | |
411 | nvidia,function = "rsvd4"; | |
412 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
413 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
414 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
415 | }; | |
416 | dap1_din_pn1 { | |
417 | nvidia,pins = "dap1_din_pn1"; | |
418 | nvidia,function = "rsvd4"; | |
419 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
420 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
421 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
422 | }; | |
423 | dap1_dout_pn2 { | |
424 | nvidia,pins = "dap1_dout_pn2"; | |
425 | nvidia,function = "i2s0"; | |
426 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
427 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
428 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
429 | }; | |
430 | dap1_sclk_pn3 { | |
431 | nvidia,pins = "dap1_sclk_pn3"; | |
432 | nvidia,function = "rsvd4"; | |
433 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
434 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
435 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
436 | }; | |
437 | usb_vbus_en0_pn4 { | |
438 | nvidia,pins = "usb_vbus_en0_pn4"; | |
439 | nvidia,function = "usb"; | |
440 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
441 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
442 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
443 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
444 | }; | |
445 | usb_vbus_en1_pn5 { | |
446 | nvidia,pins = "usb_vbus_en1_pn5"; | |
447 | nvidia,function = "usb"; | |
448 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
449 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
450 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
451 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
452 | }; | |
453 | hdmi_int_pn7 { | |
454 | nvidia,pins = "hdmi_int_pn7"; | |
455 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
456 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
457 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
458 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
459 | }; | |
460 | ulpi_data7_po0 { | |
461 | nvidia,pins = "ulpi_data7_po0"; | |
462 | nvidia,function = "ulpi"; | |
463 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
464 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
465 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
466 | }; | |
467 | ulpi_data0_po1 { | |
468 | nvidia,pins = "ulpi_data0_po1"; | |
469 | nvidia,function = "ulpi"; | |
470 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
471 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
472 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
473 | }; | |
474 | ulpi_data1_po2 { | |
475 | nvidia,pins = "ulpi_data1_po2"; | |
476 | nvidia,function = "ulpi"; | |
477 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
478 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
479 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
480 | }; | |
481 | ulpi_data2_po3 { | |
482 | nvidia,pins = "ulpi_data2_po3"; | |
483 | nvidia,function = "ulpi"; | |
484 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
485 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
486 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
487 | }; | |
488 | ulpi_data3_po4 { | |
489 | nvidia,pins = "ulpi_data3_po4"; | |
490 | nvidia,function = "ulpi"; | |
491 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
492 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
493 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
494 | }; | |
495 | ulpi_data4_po5 { | |
496 | nvidia,pins = "ulpi_data4_po5"; | |
497 | nvidia,function = "ulpi"; | |
498 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
499 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
500 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
501 | }; | |
502 | ulpi_data5_po6 { | |
503 | nvidia,pins = "ulpi_data5_po6"; | |
504 | nvidia,function = "ulpi"; | |
505 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
506 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
507 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
508 | }; | |
509 | ulpi_data6_po7 { | |
510 | nvidia,pins = "ulpi_data6_po7"; | |
511 | nvidia,function = "ulpi"; | |
512 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
513 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
514 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
515 | }; | |
516 | dap3_fs_pp0 { | |
517 | nvidia,pins = "dap3_fs_pp0"; | |
518 | nvidia,function = "i2s2"; | |
519 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
520 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
521 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
522 | }; | |
523 | dap3_din_pp1 { | |
524 | nvidia,pins = "dap3_din_pp1"; | |
525 | nvidia,function = "i2s2"; | |
526 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
527 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
528 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
529 | }; | |
530 | dap3_dout_pp2 { | |
531 | nvidia,pins = "dap3_dout_pp2"; | |
532 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
533 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
534 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
535 | }; | |
536 | dap3_sclk_pp3 { | |
537 | nvidia,pins = "dap3_sclk_pp3"; | |
538 | nvidia,function = "rsvd3"; | |
539 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
540 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
541 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
542 | }; | |
543 | dap4_fs_pp4 { | |
544 | nvidia,pins = "dap4_fs_pp4"; | |
545 | nvidia,function = "rsvd4"; | |
546 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
547 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
548 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
549 | }; | |
550 | dap4_din_pp5 { | |
551 | nvidia,pins = "dap4_din_pp5"; | |
552 | nvidia,function = "rsvd3"; | |
553 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
554 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
555 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
556 | }; | |
557 | dap4_dout_pp6 { | |
558 | nvidia,pins = "dap4_dout_pp6"; | |
559 | nvidia,function = "rsvd4"; | |
560 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
561 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
562 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
563 | }; | |
564 | dap4_sclk_pp7 { | |
565 | nvidia,pins = "dap4_sclk_pp7"; | |
566 | nvidia,function = "rsvd3"; | |
567 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
568 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
569 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
570 | }; | |
571 | kb_col0_pq0 { | |
572 | nvidia,pins = "kb_col0_pq0"; | |
573 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
574 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
575 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
576 | }; | |
577 | kb_col1_pq1 { | |
578 | nvidia,pins = "kb_col1_pq1"; | |
579 | nvidia,function = "rsvd2"; | |
580 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
581 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
582 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
583 | }; | |
584 | kb_col2_pq2 { | |
585 | nvidia,pins = "kb_col2_pq2"; | |
586 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
587 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
588 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
589 | }; | |
590 | kb_col3_pq3 { | |
591 | nvidia,pins = "kb_col3_pq3"; | |
592 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
593 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
594 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
595 | }; | |
596 | kb_col4_pq4 { | |
597 | nvidia,pins = "kb_col4_pq4"; | |
598 | nvidia,function = "sdmmc3"; | |
599 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
600 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
601 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
602 | }; | |
603 | kb_col5_pq5 { | |
604 | nvidia,pins = "kb_col5_pq5"; | |
605 | nvidia,function = "rsvd2"; | |
606 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
607 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
608 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
609 | }; | |
610 | kb_col6_pq6 { | |
611 | nvidia,pins = "kb_col6_pq6"; | |
612 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
613 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
614 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
615 | }; | |
616 | kb_col7_pq7 { | |
617 | nvidia,pins = "kb_col7_pq7"; | |
618 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
619 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
620 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
621 | }; | |
622 | kb_row0_pr0 { | |
623 | nvidia,pins = "kb_row0_pr0"; | |
624 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
625 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
626 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
627 | }; | |
628 | kb_row1_pr1 { | |
629 | nvidia,pins = "kb_row1_pr1"; | |
630 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
631 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
632 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
633 | }; | |
634 | kb_row2_pr2 { | |
635 | nvidia,pins = "kb_row2_pr2"; | |
636 | nvidia,function = "rsvd2"; | |
637 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
638 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
639 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
640 | }; | |
641 | kb_row3_pr3 { | |
642 | nvidia,pins = "kb_row3_pr3"; | |
643 | nvidia,function = "kbc"; | |
644 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
645 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
646 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
647 | }; | |
648 | kb_row4_pr4 { | |
649 | nvidia,pins = "kb_row4_pr4"; | |
650 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
651 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
652 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
653 | }; | |
654 | kb_row5_pr5 { | |
655 | nvidia,pins = "kb_row5_pr5"; | |
656 | nvidia,function = "rsvd3"; | |
657 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
658 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
659 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
660 | }; | |
661 | kb_row6_pr6 { | |
662 | nvidia,pins = "kb_row6_pr6"; | |
663 | nvidia,function = "kbc"; | |
664 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
665 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
666 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
667 | }; | |
668 | kb_row7_pr7 { | |
669 | nvidia,pins = "kb_row7_pr7"; | |
670 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
671 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
672 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
673 | }; | |
674 | kb_row8_ps0 { | |
675 | nvidia,pins = "kb_row8_ps0"; | |
676 | nvidia,function = "rsvd2"; | |
677 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
678 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
679 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
680 | }; | |
681 | kb_row9_ps1 { | |
682 | nvidia,pins = "kb_row9_ps1"; | |
683 | nvidia,function = "uarta"; | |
684 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
685 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
686 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
687 | }; | |
688 | kb_row10_ps2 { | |
689 | nvidia,pins = "kb_row10_ps2"; | |
690 | nvidia,function = "uarta"; | |
691 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
692 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
693 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
694 | }; | |
695 | kb_row11_ps3 { | |
696 | nvidia,pins = "kb_row11_ps3"; | |
697 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
698 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
699 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
700 | }; | |
701 | kb_row12_ps4 { | |
702 | nvidia,pins = "kb_row12_ps4"; | |
703 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
704 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
705 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
706 | }; | |
707 | kb_row13_ps5 { | |
708 | nvidia,pins = "kb_row13_ps5"; | |
709 | nvidia,function = "rsvd2"; | |
710 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
711 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
712 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
713 | }; | |
714 | kb_row14_ps6 { | |
715 | nvidia,pins = "kb_row14_ps6"; | |
716 | nvidia,function = "rsvd2"; | |
717 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
718 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
719 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
720 | }; | |
721 | kb_row15_ps7 { | |
722 | nvidia,pins = "kb_row15_ps7"; | |
723 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
724 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
725 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
726 | }; | |
727 | kb_row16_pt0 { | |
728 | nvidia,pins = "kb_row16_pt0"; | |
729 | nvidia,function = "rsvd2"; | |
730 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
731 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
732 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
733 | }; | |
734 | kb_row17_pt1 { | |
735 | nvidia,pins = "kb_row17_pt1"; | |
736 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
737 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
738 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
739 | }; | |
740 | gen2_i2c_scl_pt5 { | |
741 | nvidia,pins = "gen2_i2c_scl_pt5"; | |
742 | nvidia,function = "i2c2"; | |
743 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
744 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
745 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
746 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
747 | }; | |
748 | gen2_i2c_sda_pt6 { | |
749 | nvidia,pins = "gen2_i2c_sda_pt6"; | |
750 | nvidia,function = "i2c2"; | |
751 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
752 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
753 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
754 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
755 | }; | |
756 | sdmmc4_cmd_pt7 { | |
757 | nvidia,pins = "sdmmc4_cmd_pt7"; | |
758 | nvidia,function = "sdmmc4"; | |
759 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
760 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
761 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
762 | }; | |
763 | pu0 { | |
764 | nvidia,pins = "pu0"; | |
765 | nvidia,function = "rsvd4"; | |
766 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
767 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
768 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
769 | }; | |
770 | pu1 { | |
771 | nvidia,pins = "pu1"; | |
772 | nvidia,function = "rsvd1"; | |
773 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
774 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
775 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
776 | }; | |
777 | pu2 { | |
778 | nvidia,pins = "pu2"; | |
779 | nvidia,function = "rsvd1"; | |
780 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
781 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
782 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
783 | }; | |
784 | pu3 { | |
785 | nvidia,pins = "pu3"; | |
786 | nvidia,function = "gmi"; | |
787 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
788 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
789 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
790 | }; | |
791 | pu4 { | |
792 | nvidia,pins = "pu4"; | |
793 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
794 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
795 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
796 | }; | |
797 | pu5 { | |
798 | nvidia,pins = "pu5"; | |
799 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
800 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
801 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
802 | }; | |
803 | pu6 { | |
804 | nvidia,pins = "pu6"; | |
805 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
806 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
807 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
808 | }; | |
809 | pv0 { | |
810 | nvidia,pins = "pv0"; | |
811 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
812 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
813 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
814 | }; | |
815 | pv1 { | |
816 | nvidia,pins = "pv1"; | |
817 | nvidia,function = "rsvd1"; | |
818 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
819 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
820 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
821 | }; | |
822 | sdmmc3_cd_n_pv2 { | |
823 | nvidia,pins = "sdmmc3_cd_n_pv2"; | |
824 | nvidia,function = "sdmmc3"; | |
825 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
826 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
827 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
828 | }; | |
829 | sdmmc1_wp_n_pv3 { | |
830 | nvidia,pins = "sdmmc1_wp_n_pv3"; | |
831 | nvidia,function = "sdmmc1"; | |
832 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
833 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
834 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
835 | }; | |
836 | ddc_scl_pv4 { | |
837 | nvidia,pins = "ddc_scl_pv4"; | |
838 | nvidia,function = "i2c4"; | |
839 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
840 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
841 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
842 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
843 | }; | |
844 | ddc_sda_pv5 { | |
845 | nvidia,pins = "ddc_sda_pv5"; | |
846 | nvidia,function = "i2c4"; | |
847 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
848 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
849 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
850 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
851 | }; | |
852 | gpio_w2_aud_pw2 { | |
853 | nvidia,pins = "gpio_w2_aud_pw2"; | |
854 | nvidia,function = "rsvd2"; | |
855 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
856 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
857 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
858 | }; | |
859 | gpio_w3_aud_pw3 { | |
860 | nvidia,pins = "gpio_w3_aud_pw3"; | |
861 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
862 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
863 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
864 | }; | |
865 | dap_mclk1_pw4 { | |
866 | nvidia,pins = "dap_mclk1_pw4"; | |
867 | nvidia,function = "extperiph1"; | |
868 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
869 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
870 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
871 | }; | |
872 | clk2_out_pw5 { | |
873 | nvidia,pins = "clk2_out_pw5"; | |
874 | nvidia,function = "rsvd2"; | |
875 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
876 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
877 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
878 | }; | |
879 | uart3_txd_pw6 { | |
880 | nvidia,pins = "uart3_txd_pw6"; | |
881 | nvidia,function = "rsvd2"; | |
882 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
883 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
884 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
885 | }; | |
886 | uart3_rxd_pw7 { | |
887 | nvidia,pins = "uart3_rxd_pw7"; | |
888 | nvidia,function = "rsvd2"; | |
889 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
890 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
891 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
892 | }; | |
893 | dvfs_pwm_px0 { | |
894 | nvidia,pins = "dvfs_pwm_px0"; | |
895 | nvidia,function = "cldvfs"; | |
896 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
897 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
898 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
899 | }; | |
900 | gpio_x1_aud_px1 { | |
901 | nvidia,pins = "gpio_x1_aud_px1"; | |
902 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
903 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
904 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
905 | }; | |
906 | dvfs_clk_px2 { | |
907 | nvidia,pins = "dvfs_clk_px2"; | |
908 | nvidia,function = "cldvfs"; | |
909 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
910 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
911 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
912 | }; | |
913 | gpio_x3_aud_px3 { | |
914 | nvidia,pins = "gpio_x3_aud_px3"; | |
915 | nvidia,function = "rsvd4"; | |
916 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
917 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
918 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
919 | }; | |
920 | gpio_x4_aud_px4 { | |
921 | nvidia,pins = "gpio_x4_aud_px4"; | |
922 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
923 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
924 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
925 | }; | |
926 | gpio_x5_aud_px5 { | |
927 | nvidia,pins = "gpio_x5_aud_px5"; | |
928 | nvidia,function = "rsvd4"; | |
929 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
930 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
931 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
932 | }; | |
933 | gpio_x6_aud_px6 { | |
934 | nvidia,pins = "gpio_x6_aud_px6"; | |
935 | nvidia,function = "gmi"; | |
936 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
937 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
938 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
939 | }; | |
940 | gpio_x7_aud_px7 { | |
941 | nvidia,pins = "gpio_x7_aud_px7"; | |
942 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
943 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
944 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
945 | }; | |
946 | ulpi_clk_py0 { | |
947 | nvidia,pins = "ulpi_clk_py0"; | |
948 | nvidia,function = "spi1"; | |
949 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
950 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
951 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
952 | }; | |
953 | ulpi_dir_py1 { | |
954 | nvidia,pins = "ulpi_dir_py1"; | |
955 | nvidia,function = "spi1"; | |
956 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
957 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
958 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
959 | }; | |
960 | ulpi_nxt_py2 { | |
961 | nvidia,pins = "ulpi_nxt_py2"; | |
962 | nvidia,function = "spi1"; | |
963 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
964 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
965 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
966 | }; | |
967 | ulpi_stp_py3 { | |
968 | nvidia,pins = "ulpi_stp_py3"; | |
969 | nvidia,function = "spi1"; | |
970 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
971 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
972 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
973 | }; | |
974 | sdmmc1_dat3_py4 { | |
975 | nvidia,pins = "sdmmc1_dat3_py4"; | |
976 | nvidia,function = "sdmmc1"; | |
977 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
978 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
979 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
980 | }; | |
981 | sdmmc1_dat2_py5 { | |
982 | nvidia,pins = "sdmmc1_dat2_py5"; | |
983 | nvidia,function = "sdmmc1"; | |
984 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
985 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
986 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
987 | }; | |
988 | sdmmc1_dat1_py6 { | |
989 | nvidia,pins = "sdmmc1_dat1_py6"; | |
990 | nvidia,function = "sdmmc1"; | |
991 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
992 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
993 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
994 | }; | |
995 | sdmmc1_dat0_py7 { | |
996 | nvidia,pins = "sdmmc1_dat0_py7"; | |
997 | nvidia,function = "sdmmc1"; | |
998 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
999 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1000 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1001 | }; | |
1002 | sdmmc1_clk_pz0 { | |
1003 | nvidia,pins = "sdmmc1_clk_pz0"; | |
1004 | nvidia,function = "sdmmc1"; | |
1005 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1006 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1007 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1008 | }; | |
1009 | sdmmc1_cmd_pz1 { | |
1010 | nvidia,pins = "sdmmc1_cmd_pz1"; | |
1011 | nvidia,function = "sdmmc1"; | |
1012 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1013 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1014 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1015 | }; | |
1016 | pwr_i2c_scl_pz6 { | |
1017 | nvidia,pins = "pwr_i2c_scl_pz6"; | |
1018 | nvidia,function = "i2cpwr"; | |
1019 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1020 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1021 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1022 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1023 | }; | |
1024 | pwr_i2c_sda_pz7 { | |
1025 | nvidia,pins = "pwr_i2c_sda_pz7"; | |
1026 | nvidia,function = "i2cpwr"; | |
1027 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1028 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1029 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1030 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1031 | }; | |
1032 | sdmmc4_dat0_paa0 { | |
1033 | nvidia,pins = "sdmmc4_dat0_paa0"; | |
1034 | nvidia,function = "sdmmc4"; | |
1035 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1036 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1037 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1038 | }; | |
1039 | sdmmc4_dat1_paa1 { | |
1040 | nvidia,pins = "sdmmc4_dat1_paa1"; | |
1041 | nvidia,function = "sdmmc4"; | |
1042 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1043 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1044 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1045 | }; | |
1046 | sdmmc4_dat2_paa2 { | |
1047 | nvidia,pins = "sdmmc4_dat2_paa2"; | |
1048 | nvidia,function = "sdmmc4"; | |
1049 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1050 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1051 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1052 | }; | |
1053 | sdmmc4_dat3_paa3 { | |
1054 | nvidia,pins = "sdmmc4_dat3_paa3"; | |
1055 | nvidia,function = "sdmmc4"; | |
1056 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1057 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1058 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1059 | }; | |
1060 | sdmmc4_dat4_paa4 { | |
1061 | nvidia,pins = "sdmmc4_dat4_paa4"; | |
1062 | nvidia,function = "sdmmc4"; | |
1063 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1064 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1065 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1066 | }; | |
1067 | sdmmc4_dat5_paa5 { | |
1068 | nvidia,pins = "sdmmc4_dat5_paa5"; | |
1069 | nvidia,function = "sdmmc4"; | |
1070 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1071 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1072 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1073 | }; | |
1074 | sdmmc4_dat6_paa6 { | |
1075 | nvidia,pins = "sdmmc4_dat6_paa6"; | |
1076 | nvidia,function = "sdmmc4"; | |
1077 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1078 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1079 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1080 | }; | |
1081 | sdmmc4_dat7_paa7 { | |
1082 | nvidia,pins = "sdmmc4_dat7_paa7"; | |
1083 | nvidia,function = "sdmmc4"; | |
1084 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1085 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1086 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1087 | }; | |
1088 | pbb0 { | |
1089 | nvidia,pins = "pbb0"; | |
1090 | nvidia,function = "vgp6"; | |
1091 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1092 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1093 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1094 | }; | |
1095 | cam_i2c_scl_pbb1 { | |
1096 | nvidia,pins = "cam_i2c_scl_pbb1"; | |
1097 | nvidia,function = "rsvd3"; | |
1098 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1099 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1100 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1101 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1102 | }; | |
1103 | cam_i2c_sda_pbb2 { | |
1104 | nvidia,pins = "cam_i2c_sda_pbb2"; | |
1105 | nvidia,function = "rsvd3"; | |
1106 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1107 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1108 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1109 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1110 | }; | |
1111 | pbb3 { | |
1112 | nvidia,pins = "pbb3"; | |
1113 | nvidia,function = "vgp3"; | |
1114 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1115 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1116 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1117 | }; | |
1118 | pbb4 { | |
1119 | nvidia,pins = "pbb4"; | |
1120 | nvidia,function = "vgp4"; | |
1121 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1122 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1123 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1124 | }; | |
1125 | pbb5 { | |
1126 | nvidia,pins = "pbb5"; | |
1127 | nvidia,function = "rsvd3"; | |
1128 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1129 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1130 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1131 | }; | |
1132 | pbb6 { | |
1133 | nvidia,pins = "pbb6"; | |
1134 | nvidia,function = "rsvd2"; | |
1135 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1136 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1137 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1138 | }; | |
1139 | pbb7 { | |
1140 | nvidia,pins = "pbb7"; | |
1141 | nvidia,function = "rsvd2"; | |
1142 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1143 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1144 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1145 | }; | |
1146 | cam_mclk_pcc0 { | |
1147 | nvidia,pins = "cam_mclk_pcc0"; | |
1148 | nvidia,function = "vi"; | |
1149 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1150 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1151 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1152 | }; | |
1153 | pcc1 { | |
1154 | nvidia,pins = "pcc1"; | |
1155 | nvidia,function = "rsvd2"; | |
1156 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1157 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1158 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1159 | }; | |
1160 | pcc2 { | |
1161 | nvidia,pins = "pcc2"; | |
1162 | nvidia,function = "rsvd2"; | |
1163 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1164 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1165 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1166 | }; | |
1167 | sdmmc4_clk_pcc4 { | |
1168 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
1169 | nvidia,function = "sdmmc4"; | |
1170 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1171 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1172 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1173 | }; | |
1174 | clk2_req_pcc5 { | |
1175 | nvidia,pins = "clk2_req_pcc5"; | |
1176 | nvidia,function = "rsvd2"; | |
1177 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1178 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1179 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1180 | }; | |
1181 | pex_l0_rst_n_pdd1 { | |
1182 | nvidia,pins = "pex_l0_rst_n_pdd1"; | |
1183 | nvidia,function = "rsvd2"; | |
1184 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1185 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1186 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1187 | }; | |
1188 | pex_l0_clkreq_n_pdd2 { | |
1189 | nvidia,pins = "pex_l0_clkreq_n_pdd2"; | |
1190 | nvidia,function = "rsvd2"; | |
1191 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1192 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1193 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1194 | }; | |
1195 | pex_wake_n_pdd3 { | |
1196 | nvidia,pins = "pex_wake_n_pdd3"; | |
1197 | nvidia,function = "rsvd2"; | |
1198 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1199 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1200 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1201 | }; | |
1202 | pex_l1_rst_n_pdd5 { | |
1203 | nvidia,pins = "pex_l1_rst_n_pdd5"; | |
1204 | nvidia,function = "rsvd2"; | |
1205 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1206 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1207 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1208 | }; | |
1209 | pex_l1_clkreq_n_pdd6 { | |
1210 | nvidia,pins = "pex_l1_clkreq_n_pdd6"; | |
1211 | nvidia,function = "rsvd2"; | |
1212 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1213 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1214 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1215 | }; | |
1216 | clk3_out_pee0 { | |
1217 | nvidia,pins = "clk3_out_pee0"; | |
1218 | nvidia,function = "rsvd2"; | |
1219 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1220 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1221 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1222 | }; | |
1223 | clk3_req_pee1 { | |
1224 | nvidia,pins = "clk3_req_pee1"; | |
1225 | nvidia,function = "rsvd2"; | |
1226 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1227 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1228 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1229 | }; | |
1230 | dap_mclk1_req_pee2 { | |
1231 | nvidia,pins = "dap_mclk1_req_pee2"; | |
1232 | nvidia,function = "rsvd4"; | |
1233 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1234 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1235 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1236 | }; | |
1237 | hdmi_cec_pee3 { | |
1238 | nvidia,pins = "hdmi_cec_pee3"; | |
1239 | nvidia,function = "cec"; | |
1240 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1241 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1242 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1243 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1244 | }; | |
1245 | sdmmc3_clk_lb_out_pee4 { | |
1246 | nvidia,pins = "sdmmc3_clk_lb_out_pee4"; | |
1247 | nvidia,function = "sdmmc3"; | |
1248 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1249 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1250 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1251 | }; | |
1252 | sdmmc3_clk_lb_in_pee5 { | |
1253 | nvidia,pins = "sdmmc3_clk_lb_in_pee5"; | |
1254 | nvidia,function = "sdmmc3"; | |
1255 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1256 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1257 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1258 | }; | |
1259 | dp_hpd_pff0 { | |
1260 | nvidia,pins = "dp_hpd_pff0"; | |
1261 | nvidia,function = "dp"; | |
1262 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1263 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1264 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1265 | }; | |
1266 | usb_vbus_en2_pff1 { | |
1267 | nvidia,pins = "usb_vbus_en2_pff1"; | |
1268 | nvidia,function = "rsvd2"; | |
1269 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1270 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1271 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1272 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1273 | }; | |
1274 | pff2 { | |
1275 | nvidia,pins = "pff2"; | |
1276 | nvidia,function = "rsvd2"; | |
1277 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1278 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1279 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1280 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1281 | }; | |
1282 | core_pwr_req { | |
1283 | nvidia,pins = "core_pwr_req"; | |
1284 | nvidia,function = "pwron"; | |
1285 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1286 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1287 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1288 | }; | |
1289 | cpu_pwr_req { | |
1290 | nvidia,pins = "cpu_pwr_req"; | |
1291 | nvidia,function = "cpu"; | |
1292 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1293 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1294 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1295 | }; | |
1296 | pwr_int_n { | |
1297 | nvidia,pins = "pwr_int_n"; | |
1298 | nvidia,function = "pmi"; | |
1299 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1300 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1301 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1302 | }; | |
1303 | reset_out_n { | |
1304 | nvidia,pins = "reset_out_n"; | |
1305 | nvidia,function = "reset_out_n"; | |
1306 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1307 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1308 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1309 | }; | |
1310 | owr { | |
1311 | nvidia,pins = "owr"; | |
1312 | nvidia,function = "rsvd2"; | |
1313 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1314 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1315 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1316 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
1317 | }; | |
1318 | clk_32k_in { | |
1319 | nvidia,pins = "clk_32k_in"; | |
1320 | nvidia,function = "clk"; | |
1321 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1322 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1323 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1324 | }; | |
1325 | jtag_rtck { | |
1326 | nvidia,pins = "jtag_rtck"; | |
1327 | nvidia,function = "rtck"; | |
1328 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1329 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1330 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1331 | }; | |
1332 | }; | |
1333 | }; | |
1334 | }; |