Commit | Line | Data |
---|---|---|
a1425d42 JL |
1 | /dts-v1/; |
2 | ||
3 | #include "tegra124.dtsi" | |
4 | ||
5 | / { | |
6 | model = "NVIDIA Tegra124 Venice2"; | |
7 | compatible = "nvidia,venice2", "nvidia,tegra124"; | |
8 | ||
9 | memory { | |
10 | reg = <0x80000000 0x80000000>; | |
11 | }; | |
12 | ||
4b20bcbe LD |
13 | pinmux: pinmux@70000868 { |
14 | pinctrl-names = "default"; | |
15 | pinctrl-0 = <&pinmux_default>; | |
16 | ||
17 | pinmux_default: common { | |
18 | dap_mclk1_pw4 { | |
19 | nvidia,pins = "dap_mclk1_pw4"; | |
20 | nvidia,function = "extperiph1"; | |
21 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
22 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
23 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
24 | }; | |
25 | dap1_din_pn1 { | |
26 | nvidia,pins = "dap1_din_pn1", | |
27 | "dap1_dout_pn2", | |
28 | "dap1_fs_pn0", | |
29 | "dap1_sclk_pn3"; | |
30 | nvidia,function = "i2s0"; | |
31 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
32 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
33 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
34 | }; | |
35 | dap2_din_pa4 { | |
36 | nvidia,pins = "dap2_din_pa4", | |
37 | "dap2_dout_pa5", | |
38 | "dap2_fs_pa2", | |
39 | "dap2_sclk_pa3"; | |
40 | nvidia,function = "i2s1"; | |
41 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
42 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
43 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
44 | }; | |
45 | dvfs_pwm_px0 { | |
46 | nvidia,pins = "dvfs_pwm_px0"; | |
47 | nvidia,function = "cldvfs"; | |
48 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
49 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
50 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
51 | }; | |
52 | dvfs_clk_px2 { | |
53 | nvidia,pins = "dvfs_clk_px2"; | |
54 | nvidia,function = "cldvfs"; | |
55 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
56 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
57 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
58 | }; | |
59 | ulpi_clk_py0 { | |
60 | nvidia,pins = "ulpi_clk_py0", | |
61 | "ulpi_dir_py1", | |
62 | "ulpi_nxt_py2", | |
63 | "ulpi_stp_py3"; | |
64 | nvidia,function = "spi1"; | |
65 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
66 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
67 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
68 | }; | |
69 | cam_i2c_scl_pbb1 { | |
70 | nvidia,pins = "cam_i2c_scl_pbb1", | |
71 | "cam_i2c_sda_pbb2"; | |
72 | nvidia,function = "i2c3"; | |
73 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
74 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
75 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
76 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
77 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
78 | }; | |
79 | gen2_i2c_scl_pt5 { | |
80 | nvidia,pins = "gen2_i2c_scl_pt5", | |
81 | "gen2_i2c_sda_pt6"; | |
82 | nvidia,function = "i2c2"; | |
83 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
84 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
85 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
86 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
87 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
88 | }; | |
89 | pg4 { | |
90 | nvidia,pins = "pg4", | |
91 | "pg5", | |
92 | "pg6", | |
93 | "pg7", | |
94 | "pi3"; | |
95 | nvidia,function = "spi4"; | |
96 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
97 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
98 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
99 | }; | |
100 | ph0 { | |
101 | nvidia,pins = "ph0"; | |
102 | nvidia,function = "pwm0"; | |
103 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
104 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
105 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
106 | }; | |
107 | ph1 { | |
108 | nvidia,pins = "ph1"; | |
109 | nvidia,function = "pwm1"; | |
110 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
111 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
112 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
113 | }; | |
114 | sdmmc1_clk_pz0 { | |
115 | nvidia,pins = "sdmmc1_clk_pz0", | |
116 | "sdmmc1_cmd_pz1", | |
117 | "sdmmc1_dat0_py7", | |
118 | "sdmmc1_dat1_py6", | |
119 | "sdmmc1_dat2_py5", | |
120 | "sdmmc1_dat3_py4"; | |
121 | nvidia,function = "sdmmc1"; | |
122 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
123 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
124 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
125 | }; | |
126 | sdmmc3_clk_pa6 { | |
127 | nvidia,pins = "sdmmc3_clk_pa6"; | |
128 | nvidia,function = "sdmmc3"; | |
129 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
130 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
131 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
132 | }; | |
133 | sdmmc3_cmd_pa7 { | |
134 | nvidia,pins = "sdmmc3_cmd_pa7", | |
135 | "sdmmc3_dat0_pb7", | |
136 | "sdmmc3_dat1_pb6", | |
137 | "sdmmc3_dat2_pb5", | |
138 | "sdmmc3_dat3_pb4", | |
139 | "sdmmc3_clk_lb_out_pee4", | |
140 | "sdmmc3_clk_lb_in_pee5"; | |
141 | nvidia,function = "sdmmc3"; | |
142 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
143 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
144 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
145 | }; | |
146 | sdmmc4_clk_pcc4 { | |
147 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
148 | nvidia,function = "sdmmc4"; | |
149 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
150 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
151 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
152 | }; | |
153 | sdmmc4_cmd_pt7 { | |
154 | nvidia,pins = "sdmmc4_cmd_pt7", | |
155 | "sdmmc4_dat0_paa0", | |
156 | "sdmmc4_dat1_paa1", | |
157 | "sdmmc4_dat2_paa2", | |
158 | "sdmmc4_dat3_paa3", | |
159 | "sdmmc4_dat4_paa4", | |
160 | "sdmmc4_dat5_paa5", | |
161 | "sdmmc4_dat6_paa6", | |
162 | "sdmmc4_dat7_paa7"; | |
163 | nvidia,function = "sdmmc4"; | |
164 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
165 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
166 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
167 | }; | |
168 | pwr_i2c_scl_pz6 { | |
169 | nvidia,pins = "pwr_i2c_scl_pz6", | |
170 | "pwr_i2c_sda_pz7"; | |
171 | nvidia,function = "i2cpwr"; | |
172 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
173 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
174 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
175 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
176 | }; | |
177 | jtag_rtck { | |
178 | nvidia,pins = "jtag_rtck"; | |
179 | nvidia,function = "rtck"; | |
180 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
181 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
182 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
183 | }; | |
184 | clk_32k_in { | |
185 | nvidia,pins = "clk_32k_in"; | |
186 | nvidia,function = "clk"; | |
187 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
188 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
189 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
190 | }; | |
191 | core_pwr_req { | |
192 | nvidia,pins = "core_pwr_req"; | |
193 | nvidia,function = "pwron"; | |
194 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
195 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
196 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
197 | }; | |
198 | cpu_pwr_req { | |
199 | nvidia,pins = "cpu_pwr_req"; | |
200 | nvidia,function = "cpu"; | |
201 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
202 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
203 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
204 | }; | |
205 | pwr_int_n { | |
206 | nvidia,pins = "pwr_int_n"; | |
207 | nvidia,function = "pmi"; | |
208 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
209 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
210 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
211 | }; | |
212 | reset_out_n { | |
213 | nvidia,pins = "reset_out_n"; | |
214 | nvidia,function = "reset_out_n"; | |
215 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
216 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
217 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
218 | }; | |
219 | clk3_out_pee0 { | |
220 | nvidia,pins = "clk3_out_pee0"; | |
221 | nvidia,function = "extperiph3"; | |
222 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
223 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
224 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
225 | }; | |
226 | dap4_din_pp5 { | |
227 | nvidia,pins = "dap4_din_pp5", | |
228 | "dap4_dout_pp6", | |
229 | "dap4_fs_pp4", | |
230 | "dap4_sclk_pp7"; | |
231 | nvidia,function = "i2s3"; | |
232 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
233 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
234 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
235 | }; | |
236 | gen1_i2c_sda_pc5 { | |
237 | nvidia,pins = "gen1_i2c_sda_pc5", | |
238 | "gen1_i2c_scl_pc4"; | |
239 | nvidia,function = "i2c1"; | |
240 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
241 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
242 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
243 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
244 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
245 | }; | |
246 | pu0 { | |
247 | nvidia,pins = "pu0", | |
248 | "pu1", | |
249 | "pu2", | |
250 | "pu3"; | |
251 | nvidia,function = "uarta"; | |
252 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
253 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
254 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
255 | }; | |
256 | uart2_cts_n_pj5 { | |
257 | nvidia,pins = "uart2_cts_n_pj5", | |
258 | "uart2_rts_n_pj6"; | |
259 | nvidia,function = "uartb"; | |
260 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
261 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
262 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
263 | }; | |
264 | uart2_rxd_pc3 { | |
265 | nvidia,pins = "uart2_rxd_pc3", | |
266 | "uart2_txd_pc2"; | |
267 | nvidia,function = "irda"; | |
268 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
269 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
270 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
271 | }; | |
272 | uart3_cts_n_pa1 { | |
273 | nvidia,pins = "uart3_cts_n_pa1", | |
274 | "uart3_rts_n_pc0", | |
275 | "uart3_rxd_pw7", | |
276 | "uart3_txd_pw6"; | |
277 | nvidia,function = "uartc"; | |
278 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
279 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
280 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
281 | }; | |
282 | hdmi_cec_pee3 { | |
283 | nvidia,pins = "hdmi_cec_pee3"; | |
284 | nvidia,function = "cec"; | |
285 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
286 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
287 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
288 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
289 | }; | |
290 | ddc_scl_pv4 { | |
291 | nvidia,pins = "ddc_scl_pv4", | |
292 | "ddc_sda_pv5"; | |
293 | nvidia,function = "i2c4"; | |
294 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
295 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
296 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
297 | }; | |
298 | usb_vbus_en0_pn4 { | |
299 | nvidia,pins = "usb_vbus_en0_pn4"; | |
300 | nvidia,function = "usb"; | |
301 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
302 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
303 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
304 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
305 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
306 | }; | |
307 | usb_vbus_en1_pn5 { | |
308 | nvidia,pins = "usb_vbus_en1_pn5"; | |
309 | nvidia,function = "usb"; | |
310 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
311 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
312 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
313 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
314 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
315 | }; | |
316 | drive_sdio1 { | |
317 | nvidia,pins = "drive_sdio1"; | |
318 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
319 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
320 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | |
321 | nvidia,pull-down-strength = <32>; | |
322 | nvidia,pull-up-strength = <42>; | |
323 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
324 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
325 | }; | |
326 | drive_sdio3 { | |
327 | nvidia,pins = "drive_sdio3"; | |
328 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
329 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
330 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | |
331 | nvidia,pull-down-strength = <20>; | |
332 | nvidia,pull-up-strength = <36>; | |
333 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
334 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
335 | }; | |
336 | drive_gma { | |
337 | nvidia,pins = "drive_gma"; | |
338 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
339 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
340 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | |
341 | nvidia,pull-down-strength = <1>; | |
342 | nvidia,pull-up-strength = <2>; | |
343 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
344 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
345 | nvidia,drive-type = <1>; | |
346 | }; | |
347 | }; | |
348 | }; | |
349 | ||
a1425d42 JL |
350 | serial@70006000 { |
351 | status = "okay"; | |
352 | }; | |
353 | ||
e013485d TR |
354 | pwm: pwm@7000a000 { |
355 | status = "okay"; | |
356 | }; | |
357 | ||
9d5b2505 SW |
358 | i2c@7000c000 { |
359 | status = "okay"; | |
360 | clock-frequency = <100000>; | |
b0e1caee SW |
361 | |
362 | acodec: audio-codec@10 { | |
363 | compatible = "maxim,max98090"; | |
364 | reg = <0x10>; | |
365 | interrupt-parent = <&gpio>; | |
366 | interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; | |
367 | }; | |
9d5b2505 SW |
368 | }; |
369 | ||
370 | i2c@7000c400 { | |
371 | status = "okay"; | |
372 | clock-frequency = <100000>; | |
373 | }; | |
374 | ||
375 | i2c@7000c500 { | |
376 | status = "okay"; | |
377 | clock-frequency = <100000>; | |
378 | }; | |
379 | ||
380 | i2c@7000c700 { | |
381 | status = "okay"; | |
382 | clock-frequency = <100000>; | |
383 | }; | |
384 | ||
385 | i2c@7000d000 { | |
386 | status = "okay"; | |
387 | clock-frequency = <100000>; | |
388 | }; | |
389 | ||
a1425d42 JL |
390 | pmc@7000e400 { |
391 | nvidia,invert-interrupt; | |
6ec1d127 JL |
392 | nvidia,suspend-mode = <1>; |
393 | nvidia,cpu-pwr-good-time = <500>; | |
394 | nvidia,cpu-pwr-off-time = <300>; | |
395 | nvidia,core-pwr-good-time = <641 3845>; | |
396 | nvidia,core-pwr-off-time = <61036>; | |
397 | nvidia,core-power-req-active-high; | |
398 | nvidia,sys-clock-req-active-high; | |
a1425d42 | 399 | }; |
3b86baf2 | 400 | |
784c7444 SW |
401 | sdhci@700b0400 { |
402 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; | |
403 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; | |
404 | status = "okay"; | |
405 | bus-width = <4>; | |
406 | }; | |
407 | ||
408 | sdhci@700b0600 { | |
409 | status = "okay"; | |
410 | bus-width = <8>; | |
411 | }; | |
412 | ||
b0e1caee SW |
413 | ahub@70300000 { |
414 | i2s@70301100 { | |
415 | status = "okay"; | |
416 | }; | |
417 | }; | |
418 | ||
3b86baf2 JL |
419 | clocks { |
420 | compatible = "simple-bus"; | |
421 | #address-cells = <1>; | |
422 | #size-cells = <0>; | |
423 | ||
424 | clk32k_in: clock@0 { | |
425 | compatible = "fixed-clock"; | |
426 | reg=<0>; | |
427 | #clock-cells = <0>; | |
428 | clock-frequency = <32768>; | |
429 | }; | |
430 | }; | |
b0e1caee SW |
431 | |
432 | sound { | |
433 | compatible = "nvidia,tegra-audio-max98090-venice2", | |
434 | "nvidia,tegra-audio-max98090"; | |
435 | nvidia,model = "NVIDIA Tegra Venice2"; | |
436 | ||
437 | nvidia,audio-routing = | |
438 | "Headphones", "HPR", | |
439 | "Headphones", "HPL", | |
440 | "Speakers", "SPKR", | |
441 | "Speakers", "SPKL", | |
442 | "Mic Jack", "MICBIAS", | |
443 | "IN34", "Mic Jack"; | |
444 | ||
445 | nvidia,i2s-controller = <&tegra_i2s1>; | |
446 | nvidia,audio-codec = <&acodec>; | |
447 | ||
448 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, | |
449 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, | |
450 | <&tegra_car TEGRA124_CLK_EXTERN1>; | |
451 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
452 | }; | |
a1425d42 | 453 | }; |