Commit | Line | Data |
---|---|---|
a1425d42 JL |
1 | /dts-v1/; |
2 | ||
146db0ea | 3 | #include <dt-bindings/input/input.h> |
a1425d42 JL |
4 | #include "tegra124.dtsi" |
5 | ||
6 | / { | |
7 | model = "NVIDIA Tegra124 Venice2"; | |
8 | compatible = "nvidia,venice2", "nvidia,tegra124"; | |
9 | ||
b1afa782 | 10 | aliases { |
e30cb238 SW |
11 | rtc0 = "/i2c@0,7000d000/pmic@40"; |
12 | rtc1 = "/rtc@0,7000e000"; | |
b1afa782 SW |
13 | }; |
14 | ||
a1425d42 | 15 | memory { |
e30cb238 | 16 | reg = <0x0 0x80000000 0x0 0x80000000>; |
a1425d42 JL |
17 | }; |
18 | ||
e30cb238 | 19 | host1x@0,50000000 { |
329c39f8 TR |
20 | hdmi@0,54280000 { |
21 | status = "okay"; | |
22 | ||
23 | vdd-supply = <&vdd_3v3_hdmi>; | |
24 | pll-supply = <&vdd_hdmi_pll>; | |
25 | hdmi-supply = <&vdd_5v0_hdmi>; | |
26 | ||
27 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
28 | nvidia,hpd-gpio = | |
29 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | |
30 | }; | |
31 | ||
e30cb238 | 32 | sor@0,54540000 { |
40e231c7 TR |
33 | status = "okay"; |
34 | ||
35 | nvidia,dpaux = <&dpaux>; | |
36 | nvidia,panel = <&panel>; | |
37 | }; | |
38 | ||
e30cb238 | 39 | dpaux: dpaux@0,545c0000 { |
40e231c7 TR |
40 | vdd-supply = <&vdd_3v3_panel>; |
41 | status = "okay"; | |
42 | }; | |
43 | }; | |
44 | ||
e30cb238 | 45 | pinmux: pinmux@0,70000868 { |
4b20bcbe LD |
46 | pinctrl-names = "default"; |
47 | pinctrl-0 = <&pinmux_default>; | |
48 | ||
49 | pinmux_default: common { | |
50 | dap_mclk1_pw4 { | |
51 | nvidia,pins = "dap_mclk1_pw4"; | |
52 | nvidia,function = "extperiph1"; | |
53 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
54 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
55 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
56 | }; | |
57 | dap1_din_pn1 { | |
365c483f LD |
58 | nvidia,pins = "dap1_din_pn1"; |
59 | nvidia,function = "i2s0"; | |
60 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
61 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
62 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
63 | }; | |
64 | dap1_dout_pn2 { | |
65 | nvidia,pins = "dap1_dout_pn2", | |
4b20bcbe LD |
66 | "dap1_fs_pn0", |
67 | "dap1_sclk_pn3"; | |
68 | nvidia,function = "i2s0"; | |
365c483f | 69 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
4b20bcbe LD |
70 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
71 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
72 | }; | |
73 | dap2_din_pa4 { | |
365c483f | 74 | nvidia,pins = "dap2_din_pa4"; |
4b20bcbe LD |
75 | nvidia,function = "i2s1"; |
76 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
77 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
4ffb9385 | 78 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
4b20bcbe | 79 | }; |
365c483f LD |
80 | dap2_dout_pa5 { |
81 | nvidia,pins = "dap2_dout_pa5", | |
82 | "dap2_fs_pa2", | |
83 | "dap2_sclk_pa3"; | |
84 | nvidia,function = "i2s1"; | |
4b20bcbe LD |
85 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
86 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
365c483f | 87 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
4b20bcbe | 88 | }; |
365c483f LD |
89 | dvfs_pwm_px0 { |
90 | nvidia,pins = "dvfs_pwm_px0", | |
91 | "dvfs_clk_px2"; | |
4b20bcbe LD |
92 | nvidia,function = "cldvfs"; |
93 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
94 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
95 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
96 | }; | |
97 | ulpi_clk_py0 { | |
98 | nvidia,pins = "ulpi_clk_py0", | |
4b20bcbe LD |
99 | "ulpi_nxt_py2", |
100 | "ulpi_stp_py3"; | |
101 | nvidia,function = "spi1"; | |
365c483f LD |
102 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
103 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
104 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
105 | }; | |
106 | ulpi_dir_py1 { | |
107 | nvidia,pins = "ulpi_dir_py1"; | |
108 | nvidia,function = "spi1"; | |
4b20bcbe | 109 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
365c483f | 110 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
4b20bcbe LD |
111 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
112 | }; | |
113 | cam_i2c_scl_pbb1 { | |
114 | nvidia,pins = "cam_i2c_scl_pbb1", | |
115 | "cam_i2c_sda_pbb2"; | |
116 | nvidia,function = "i2c3"; | |
117 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
118 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
119 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
120 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
121 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
122 | }; | |
123 | gen2_i2c_scl_pt5 { | |
124 | nvidia,pins = "gen2_i2c_scl_pt5", | |
125 | "gen2_i2c_sda_pt6"; | |
126 | nvidia,function = "i2c2"; | |
127 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
128 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
129 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
130 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
131 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
132 | }; | |
133 | pg4 { | |
134 | nvidia,pins = "pg4", | |
135 | "pg5", | |
136 | "pg6", | |
4b20bcbe LD |
137 | "pi3"; |
138 | nvidia,function = "spi4"; | |
139 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
140 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
141 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
142 | }; | |
365c483f LD |
143 | pg7 { |
144 | nvidia,pins = "pg7"; | |
145 | nvidia,function = "spi4"; | |
4b20bcbe | 146 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
365c483f LD |
147 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
148 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
4b20bcbe LD |
149 | }; |
150 | ph1 { | |
151 | nvidia,pins = "ph1"; | |
152 | nvidia,function = "pwm1"; | |
153 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
154 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
155 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
156 | }; | |
365c483f LD |
157 | pk0 { |
158 | nvidia,pins = "pk0", | |
159 | "kb_row15_ps7", | |
160 | "clk_32k_out_pa0"; | |
161 | nvidia,function = "soc"; | |
162 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
f5cb19b4 | 163 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
365c483f | 164 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
f5cb19b4 | 165 | }; |
4b20bcbe | 166 | sdmmc1_clk_pz0 { |
bf5fd5bf | 167 | nvidia,pins = "sdmmc1_clk_pz0"; |
4b20bcbe | 168 | nvidia,function = "sdmmc1"; |
bf5fd5bf | 169 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
4b20bcbe LD |
170 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
171 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
172 | }; | |
365c483f LD |
173 | sdmmc1_cmd_pz1 { |
174 | nvidia,pins = "sdmmc1_cmd_pz1", | |
175 | "sdmmc1_dat0_py7", | |
176 | "sdmmc1_dat1_py6", | |
177 | "sdmmc1_dat2_py5", | |
178 | "sdmmc1_dat3_py4"; | |
179 | nvidia,function = "sdmmc1"; | |
180 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
181 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
182 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
183 | }; | |
4b20bcbe LD |
184 | sdmmc3_clk_pa6 { |
185 | nvidia,pins = "sdmmc3_clk_pa6"; | |
186 | nvidia,function = "sdmmc3"; | |
187 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
188 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
189 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
190 | }; | |
191 | sdmmc3_cmd_pa7 { | |
192 | nvidia,pins = "sdmmc3_cmd_pa7", | |
193 | "sdmmc3_dat0_pb7", | |
194 | "sdmmc3_dat1_pb6", | |
195 | "sdmmc3_dat2_pb5", | |
196 | "sdmmc3_dat3_pb4", | |
197 | "sdmmc3_clk_lb_out_pee4", | |
198 | "sdmmc3_clk_lb_in_pee5"; | |
199 | nvidia,function = "sdmmc3"; | |
200 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
201 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
202 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
203 | }; | |
204 | sdmmc4_clk_pcc4 { | |
205 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
206 | nvidia,function = "sdmmc4"; | |
207 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
208 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
209 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
210 | }; | |
211 | sdmmc4_cmd_pt7 { | |
212 | nvidia,pins = "sdmmc4_cmd_pt7", | |
213 | "sdmmc4_dat0_paa0", | |
214 | "sdmmc4_dat1_paa1", | |
215 | "sdmmc4_dat2_paa2", | |
216 | "sdmmc4_dat3_paa3", | |
217 | "sdmmc4_dat4_paa4", | |
218 | "sdmmc4_dat5_paa5", | |
219 | "sdmmc4_dat6_paa6", | |
220 | "sdmmc4_dat7_paa7"; | |
221 | nvidia,function = "sdmmc4"; | |
222 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
223 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
224 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
225 | }; | |
226 | pwr_i2c_scl_pz6 { | |
227 | nvidia,pins = "pwr_i2c_scl_pz6", | |
228 | "pwr_i2c_sda_pz7"; | |
229 | nvidia,function = "i2cpwr"; | |
230 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
231 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
232 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
365c483f | 233 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
4b20bcbe LD |
234 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
235 | }; | |
236 | jtag_rtck { | |
237 | nvidia,pins = "jtag_rtck"; | |
238 | nvidia,function = "rtck"; | |
239 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
240 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
241 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
242 | }; | |
243 | clk_32k_in { | |
244 | nvidia,pins = "clk_32k_in"; | |
245 | nvidia,function = "clk"; | |
246 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
247 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
248 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
249 | }; | |
250 | core_pwr_req { | |
251 | nvidia,pins = "core_pwr_req"; | |
252 | nvidia,function = "pwron"; | |
253 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
254 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
255 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
256 | }; | |
257 | cpu_pwr_req { | |
258 | nvidia,pins = "cpu_pwr_req"; | |
259 | nvidia,function = "cpu"; | |
260 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
261 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
262 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
263 | }; | |
264 | pwr_int_n { | |
265 | nvidia,pins = "pwr_int_n"; | |
266 | nvidia,function = "pmi"; | |
267 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
268 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
269 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
270 | }; | |
271 | reset_out_n { | |
272 | nvidia,pins = "reset_out_n"; | |
273 | nvidia,function = "reset_out_n"; | |
274 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
275 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
276 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
277 | }; | |
278 | clk3_out_pee0 { | |
279 | nvidia,pins = "clk3_out_pee0"; | |
280 | nvidia,function = "extperiph3"; | |
281 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
282 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
283 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
284 | }; | |
285 | dap4_din_pp5 { | |
365c483f LD |
286 | nvidia,pins = "dap4_din_pp5"; |
287 | nvidia,function = "i2s3"; | |
288 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
289 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
290 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
291 | }; | |
292 | dap4_dout_pp6 { | |
293 | nvidia,pins = "dap4_dout_pp6", | |
4b20bcbe LD |
294 | "dap4_fs_pp4", |
295 | "dap4_sclk_pp7"; | |
296 | nvidia,function = "i2s3"; | |
365c483f | 297 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
4b20bcbe LD |
298 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
299 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
300 | }; | |
301 | gen1_i2c_sda_pc5 { | |
302 | nvidia,pins = "gen1_i2c_sda_pc5", | |
303 | "gen1_i2c_scl_pc4"; | |
304 | nvidia,function = "i2c1"; | |
305 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
306 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
307 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
308 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
365c483f | 309 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
4b20bcbe | 310 | }; |
365c483f LD |
311 | uart2_cts_n_pj5 { |
312 | nvidia,pins = "uart2_cts_n_pj5"; | |
313 | nvidia,function = "uartb"; | |
4b20bcbe | 314 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
4ffb9385 | 315 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
4b20bcbe LD |
316 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
317 | }; | |
365c483f LD |
318 | uart2_rts_n_pj6 { |
319 | nvidia,pins = "uart2_rts_n_pj6"; | |
4b20bcbe | 320 | nvidia,function = "uartb"; |
365c483f | 321 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
4b20bcbe LD |
322 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
323 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
324 | }; | |
325 | uart2_rxd_pc3 { | |
365c483f | 326 | nvidia,pins = "uart2_rxd_pc3"; |
4b20bcbe LD |
327 | nvidia,function = "irda"; |
328 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
329 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
330 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
331 | }; | |
365c483f LD |
332 | uart2_txd_pc2 { |
333 | nvidia,pins = "uart2_txd_pc2"; | |
334 | nvidia,function = "irda"; | |
335 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
336 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
337 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
338 | }; | |
4b20bcbe LD |
339 | uart3_cts_n_pa1 { |
340 | nvidia,pins = "uart3_cts_n_pa1", | |
365c483f | 341 | "uart3_rxd_pw7"; |
4b20bcbe LD |
342 | nvidia,function = "uartc"; |
343 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
344 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
345 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
346 | }; | |
365c483f LD |
347 | uart3_rts_n_pc0 { |
348 | nvidia,pins = "uart3_rts_n_pc0", | |
349 | "uart3_txd_pw6"; | |
350 | nvidia,function = "uartc"; | |
351 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
352 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
353 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
354 | }; | |
4b20bcbe LD |
355 | hdmi_cec_pee3 { |
356 | nvidia,pins = "hdmi_cec_pee3"; | |
357 | nvidia,function = "cec"; | |
358 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
359 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
360 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
365c483f LD |
361 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
362 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
363 | }; | |
364 | hdmi_int_pn7 { | |
365 | nvidia,pins = "hdmi_int_pn7"; | |
366 | nvidia,function = "rsvd1"; | |
367 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
368 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
369 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
4b20bcbe LD |
370 | }; |
371 | ddc_scl_pv4 { | |
372 | nvidia,pins = "ddc_scl_pv4", | |
373 | "ddc_sda_pv5"; | |
374 | nvidia,function = "i2c4"; | |
375 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
376 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
377 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
365c483f LD |
378 | nvidia,lock = <TEGRA_PIN_DISABLE>; |
379 | nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; | |
380 | }; | |
381 | pj7 { | |
382 | nvidia,pins = "pj7", | |
383 | "pk7"; | |
384 | nvidia,function = "uartd"; | |
385 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
386 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
387 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
388 | }; | |
389 | pb0 { | |
390 | nvidia,pins = "pb0", | |
391 | "pb1"; | |
392 | nvidia,function = "uartd"; | |
393 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
394 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
395 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
396 | }; | |
397 | ph0 { | |
398 | nvidia,pins = "ph0"; | |
399 | nvidia,function = "pwm0"; | |
400 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
401 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
402 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
403 | }; | |
404 | kb_row10_ps2 { | |
405 | nvidia,pins = "kb_row10_ps2"; | |
406 | nvidia,function = "uarta"; | |
407 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
408 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
409 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
410 | }; | |
411 | kb_row9_ps1 { | |
412 | nvidia,pins = "kb_row9_ps1"; | |
413 | nvidia,function = "uarta"; | |
414 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
415 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
416 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
417 | }; | |
418 | kb_row6_pr6 { | |
419 | nvidia,pins = "kb_row6_pr6"; | |
420 | nvidia,function = "displaya_alt"; | |
421 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
422 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
423 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
4b20bcbe LD |
424 | }; |
425 | usb_vbus_en0_pn4 { | |
fa15ffaa TR |
426 | nvidia,pins = "usb_vbus_en0_pn4", |
427 | "usb_vbus_en1_pn5"; | |
4b20bcbe LD |
428 | nvidia,function = "usb"; |
429 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
fa15ffaa | 430 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
4b20bcbe LD |
431 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
432 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
365c483f | 433 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
4b20bcbe LD |
434 | }; |
435 | drive_sdio1 { | |
436 | nvidia,pins = "drive_sdio1"; | |
437 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
438 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
4b20bcbe LD |
439 | nvidia,pull-down-strength = <32>; |
440 | nvidia,pull-up-strength = <42>; | |
441 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
442 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
443 | }; | |
444 | drive_sdio3 { | |
445 | nvidia,pins = "drive_sdio3"; | |
446 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
447 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
4b20bcbe LD |
448 | nvidia,pull-down-strength = <20>; |
449 | nvidia,pull-up-strength = <36>; | |
450 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
451 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
452 | }; | |
453 | drive_gma { | |
454 | nvidia,pins = "drive_gma"; | |
455 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
456 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
457 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | |
458 | nvidia,pull-down-strength = <1>; | |
459 | nvidia,pull-up-strength = <2>; | |
460 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
461 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
462 | nvidia,drive-type = <1>; | |
463 | }; | |
365c483f LD |
464 | als_irq_l { |
465 | nvidia,pins = "gpio_x3_aud_px3"; | |
466 | nvidia,function = "gmi"; | |
467 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
468 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
469 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
470 | }; | |
471 | codec_irq_l { | |
472 | nvidia,pins = "ph4"; | |
473 | nvidia,function = "gmi"; | |
474 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
475 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
476 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
477 | }; | |
478 | lcd_bl_en { | |
479 | nvidia,pins = "ph2"; | |
480 | nvidia,function = "gmi"; | |
481 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
482 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
483 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
484 | }; | |
485 | touch_irq_l { | |
486 | nvidia,pins = "gpio_w3_aud_pw3"; | |
487 | nvidia,function = "spi6"; | |
488 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
489 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
490 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
491 | }; | |
492 | tpm_davint_l { | |
493 | nvidia,pins = "ph6"; | |
494 | nvidia,function = "gmi"; | |
495 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
496 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
497 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
498 | }; | |
499 | ts_irq_l { | |
500 | nvidia,pins = "pk2"; | |
501 | nvidia,function = "gmi"; | |
502 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
503 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
504 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
505 | }; | |
506 | ts_reset_l { | |
507 | nvidia,pins = "pk4"; | |
508 | nvidia,function = "gmi"; | |
509 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
510 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
511 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
512 | }; | |
513 | ts_shdn_l { | |
514 | nvidia,pins = "pk1"; | |
515 | nvidia,function = "gmi"; | |
516 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
517 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
518 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
519 | }; | |
520 | ph7 { | |
521 | nvidia,pins = "ph7"; | |
522 | nvidia,function = "gmi"; | |
523 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
524 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
525 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
526 | }; | |
527 | kb_col0_ap { | |
528 | nvidia,pins = "kb_col0_pq0"; | |
529 | nvidia,function = "rsvd4"; | |
530 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
531 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
532 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
533 | }; | |
534 | lid_open { | |
535 | nvidia,pins = "kb_row4_pr4"; | |
536 | nvidia,function = "rsvd3"; | |
537 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
538 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
539 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
540 | }; | |
541 | en_vdd_sd { | |
542 | nvidia,pins = "kb_row0_pr0"; | |
543 | nvidia,function = "rsvd4"; | |
544 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
545 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
546 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
547 | }; | |
548 | ac_ok { | |
549 | nvidia,pins = "pj0"; | |
550 | nvidia,function = "gmi"; | |
551 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
552 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
553 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
554 | }; | |
555 | sensor_irq_l { | |
556 | nvidia,pins = "pi6"; | |
557 | nvidia,function = "gmi"; | |
558 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
559 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
560 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
561 | }; | |
562 | wifi_en { | |
563 | nvidia,pins = "gpio_x7_aud_px7"; | |
564 | nvidia,function = "rsvd4"; | |
565 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
566 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
567 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
568 | }; | |
569 | wifi_rst_l { | |
570 | nvidia,pins = "clk2_req_pcc5"; | |
571 | nvidia,function = "dap"; | |
572 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
573 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
574 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
575 | }; | |
576 | hp_det_l { | |
577 | nvidia,pins = "ulpi_data1_po2"; | |
578 | nvidia,function = "spi3"; | |
579 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
580 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
581 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
582 | }; | |
4b20bcbe LD |
583 | }; |
584 | }; | |
585 | ||
e30cb238 | 586 | serial@0,70006000 { |
a1425d42 JL |
587 | status = "okay"; |
588 | }; | |
589 | ||
e30cb238 | 590 | pwm: pwm@0,7000a000 { |
e013485d TR |
591 | status = "okay"; |
592 | }; | |
593 | ||
e30cb238 | 594 | i2c@0,7000c000 { |
9d5b2505 SW |
595 | status = "okay"; |
596 | clock-frequency = <100000>; | |
b0e1caee SW |
597 | |
598 | acodec: audio-codec@10 { | |
599 | compatible = "maxim,max98090"; | |
600 | reg = <0x10>; | |
601 | interrupt-parent = <&gpio>; | |
602 | interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; | |
603 | }; | |
9d5b2505 SW |
604 | }; |
605 | ||
e30cb238 | 606 | i2c@0,7000c400 { |
9d5b2505 SW |
607 | status = "okay"; |
608 | clock-frequency = <100000>; | |
609 | }; | |
610 | ||
e30cb238 | 611 | i2c@0,7000c500 { |
9d5b2505 SW |
612 | status = "okay"; |
613 | clock-frequency = <100000>; | |
614 | }; | |
615 | ||
329c39f8 | 616 | hdmi_ddc: i2c@0,7000c700 { |
9d5b2505 SW |
617 | status = "okay"; |
618 | clock-frequency = <100000>; | |
619 | }; | |
620 | ||
e30cb238 | 621 | i2c@0,7000d000 { |
9d5b2505 | 622 | status = "okay"; |
fcacaba7 LD |
623 | clock-frequency = <400000>; |
624 | ||
fdc44f94 | 625 | pmic: pmic@40 { |
fcacaba7 LD |
626 | compatible = "ams,as3722"; |
627 | reg = <0x40>; | |
628 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; | |
629 | ||
7be75df2 LD |
630 | ams,system-power-controller; |
631 | ||
fcacaba7 LD |
632 | #interrupt-cells = <2>; |
633 | interrupt-controller; | |
634 | ||
635 | gpio-controller; | |
636 | #gpio-cells = <2>; | |
637 | ||
638 | pinctrl-names = "default"; | |
639 | pinctrl-0 = <&as3722_default>; | |
640 | ||
641 | as3722_default: pinmux { | |
642 | gpio0 { | |
643 | pins = "gpio0"; | |
644 | function = "gpio"; | |
645 | bias-pull-down; | |
646 | }; | |
647 | ||
648 | gpio1_2_4_7 { | |
649 | pins = "gpio1", "gpio2", "gpio4", "gpio7"; | |
650 | function = "gpio"; | |
651 | bias-pull-up; | |
652 | }; | |
653 | ||
654 | gpio3_6 { | |
655 | pins = "gpio3", "gpio6"; | |
656 | bias-high-impedance; | |
657 | }; | |
658 | ||
659 | gpio5 { | |
660 | pins = "gpio5"; | |
661 | function = "clk32k-out"; | |
662 | }; | |
663 | }; | |
664 | ||
665 | regulators { | |
af144b8d TR |
666 | vsup-sd2-supply = <&vdd_5v0_sys>; |
667 | vsup-sd3-supply = <&vdd_5v0_sys>; | |
668 | vsup-sd4-supply = <&vdd_5v0_sys>; | |
669 | vsup-sd5-supply = <&vdd_5v0_sys>; | |
670 | vin-ldo0-supply = <&vdd_1v35_lp0>; | |
671 | vin-ldo1-6-supply = <&vdd_3v3_run>; | |
672 | vin-ldo2-5-7-supply = <&vddio_1v8>; | |
673 | vin-ldo3-4-supply = <&vdd_3v3_sys>; | |
674 | vin-ldo9-10-supply = <&vdd_5v0_sys>; | |
675 | vin-ldo11-supply = <&vdd_3v3_run>; | |
fcacaba7 LD |
676 | |
677 | sd0 { | |
af144b8d | 678 | regulator-name = "+VDD_CPU_AP"; |
fcacaba7 LD |
679 | regulator-min-microvolt = <700000>; |
680 | regulator-max-microvolt = <1400000>; | |
681 | regulator-min-microamp = <3500000>; | |
682 | regulator-max-microamp = <3500000>; | |
683 | regulator-always-on; | |
684 | regulator-boot-on; | |
685 | ams,external-control = <2>; | |
686 | }; | |
687 | ||
688 | sd1 { | |
af144b8d | 689 | regulator-name = "+VDD_CORE"; |
fcacaba7 LD |
690 | regulator-min-microvolt = <700000>; |
691 | regulator-max-microvolt = <1350000>; | |
692 | regulator-min-microamp = <2500000>; | |
693 | regulator-max-microamp = <2500000>; | |
694 | regulator-always-on; | |
695 | regulator-boot-on; | |
696 | ams,external-control = <1>; | |
697 | }; | |
698 | ||
af144b8d TR |
699 | vdd_1v35_lp0: sd2 { |
700 | regulator-name = "+1.35V_LP0(sd2)"; | |
fcacaba7 LD |
701 | regulator-min-microvolt = <1350000>; |
702 | regulator-max-microvolt = <1350000>; | |
703 | regulator-always-on; | |
704 | regulator-boot-on; | |
705 | }; | |
706 | ||
707 | sd3 { | |
af144b8d | 708 | regulator-name = "+1.35V_LP0(sd3)"; |
fcacaba7 LD |
709 | regulator-min-microvolt = <1350000>; |
710 | regulator-max-microvolt = <1350000>; | |
711 | regulator-always-on; | |
712 | regulator-boot-on; | |
713 | }; | |
714 | ||
329c39f8 | 715 | vdd_1v05_run: sd4 { |
af144b8d | 716 | regulator-name = "+1.05V_RUN"; |
fcacaba7 LD |
717 | regulator-min-microvolt = <1050000>; |
718 | regulator-max-microvolt = <1050000>; | |
fcacaba7 LD |
719 | }; |
720 | ||
af144b8d TR |
721 | vddio_1v8: sd5 { |
722 | regulator-name = "+1.8V_VDDIO"; | |
fcacaba7 LD |
723 | regulator-min-microvolt = <1800000>; |
724 | regulator-max-microvolt = <1800000>; | |
725 | regulator-boot-on; | |
726 | regulator-always-on; | |
727 | }; | |
728 | ||
729 | sd6 { | |
af144b8d | 730 | regulator-name = "+VDD_GPU_AP"; |
fcacaba7 LD |
731 | regulator-min-microvolt = <650000>; |
732 | regulator-max-microvolt = <1200000>; | |
733 | regulator-min-microamp = <3500000>; | |
734 | regulator-max-microamp = <3500000>; | |
735 | regulator-boot-on; | |
736 | regulator-always-on; | |
737 | }; | |
738 | ||
739 | ldo0 { | |
af144b8d | 740 | regulator-name = "+1.05V_RUN_AVDD"; |
fcacaba7 LD |
741 | regulator-min-microvolt = <1050000>; |
742 | regulator-max-microvolt = <1050000>; | |
743 | regulator-boot-on; | |
744 | regulator-always-on; | |
745 | ams,external-control = <1>; | |
746 | }; | |
747 | ||
748 | ldo1 { | |
af144b8d | 749 | regulator-name = "+1.8V_RUN_CAM"; |
fcacaba7 LD |
750 | regulator-min-microvolt = <1800000>; |
751 | regulator-max-microvolt = <1800000>; | |
752 | }; | |
753 | ||
754 | ldo2 { | |
af144b8d | 755 | regulator-name = "+1.2V_GEN_AVDD"; |
fcacaba7 LD |
756 | regulator-min-microvolt = <1200000>; |
757 | regulator-max-microvolt = <1200000>; | |
758 | regulator-boot-on; | |
759 | regulator-always-on; | |
760 | }; | |
761 | ||
762 | ldo3 { | |
af144b8d | 763 | regulator-name = "+1.00V_LP0_VDD_RTC"; |
fcacaba7 LD |
764 | regulator-min-microvolt = <1000000>; |
765 | regulator-max-microvolt = <1000000>; | |
766 | regulator-boot-on; | |
767 | regulator-always-on; | |
768 | ams,enable-tracking; | |
769 | }; | |
770 | ||
431b7be0 | 771 | vdd_run_cam: ldo4 { |
af144b8d | 772 | regulator-name = "+3.3V_RUN_CAM"; |
fcacaba7 LD |
773 | regulator-min-microvolt = <2800000>; |
774 | regulator-max-microvolt = <2800000>; | |
fcacaba7 LD |
775 | }; |
776 | ||
777 | ldo5 { | |
af144b8d | 778 | regulator-name = "+1.2V_RUN_CAM_FRONT"; |
fcacaba7 LD |
779 | regulator-min-microvolt = <1200000>; |
780 | regulator-max-microvolt = <1200000>; | |
781 | }; | |
782 | ||
4989b439 | 783 | vddio_sdmmc3: ldo6 { |
af144b8d | 784 | regulator-name = "+VDDIO_SDMMC3"; |
fcacaba7 LD |
785 | regulator-min-microvolt = <1800000>; |
786 | regulator-max-microvolt = <3300000>; | |
fcacaba7 LD |
787 | }; |
788 | ||
789 | ldo7 { | |
af144b8d | 790 | regulator-name = "+1.05V_RUN_CAM_REAR"; |
fcacaba7 LD |
791 | regulator-min-microvolt = <1050000>; |
792 | regulator-max-microvolt = <1050000>; | |
793 | }; | |
794 | ||
795 | ldo9 { | |
af144b8d | 796 | regulator-name = "+2.8V_RUN_TOUCH"; |
fcacaba7 LD |
797 | regulator-min-microvolt = <2800000>; |
798 | regulator-max-microvolt = <2800000>; | |
799 | }; | |
800 | ||
801 | ldo10 { | |
af144b8d | 802 | regulator-name = "+2.8V_RUN_CAM_AF"; |
fcacaba7 LD |
803 | regulator-min-microvolt = <2800000>; |
804 | regulator-max-microvolt = <2800000>; | |
805 | }; | |
806 | ||
807 | ldo11 { | |
af144b8d | 808 | regulator-name = "+1.8V_RUN_VPP_FUSE"; |
fcacaba7 LD |
809 | regulator-min-microvolt = <1800000>; |
810 | regulator-max-microvolt = <1800000>; | |
811 | }; | |
812 | }; | |
813 | }; | |
9d5b2505 SW |
814 | }; |
815 | ||
e30cb238 | 816 | spi@0,7000d400 { |
146db0ea TR |
817 | status = "okay"; |
818 | ||
f01dd55a | 819 | cros_ec: cros-ec@0 { |
146db0ea TR |
820 | compatible = "google,cros-ec-spi"; |
821 | spi-max-frequency = <4000000>; | |
822 | interrupt-parent = <&gpio>; | |
823 | interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; | |
824 | reg = <0>; | |
825 | ||
826 | google,cros-ec-spi-msg-delay = <2000>; | |
72ceddda DA |
827 | |
828 | i2c-tunnel { | |
829 | compatible = "google,cros-ec-i2c-tunnel"; | |
830 | #address-cells = <1>; | |
831 | #size-cells = <0>; | |
832 | ||
833 | google,remote-bus = <0>; | |
834 | ||
835 | charger: bq24735@9 { | |
836 | compatible = "ti,bq24735"; | |
837 | reg = <0x9>; | |
838 | interrupt-parent = <&gpio>; | |
839 | interrupts = <TEGRA_GPIO(J, 0) | |
840 | GPIO_ACTIVE_HIGH>; | |
841 | ti,ac-detect-gpios = <&gpio | |
842 | TEGRA_GPIO(J, 0) | |
843 | GPIO_ACTIVE_HIGH>; | |
844 | }; | |
845 | ||
846 | battery: sbs-battery@b { | |
847 | compatible = "sbs,sbs-battery"; | |
848 | reg = <0xb>; | |
849 | sbs,i2c-retry-count = <2>; | |
850 | sbs,poll-retry-count = <1>; | |
851 | }; | |
852 | }; | |
146db0ea TR |
853 | }; |
854 | }; | |
855 | ||
e30cb238 | 856 | spi@0,7000da00 { |
11e5b4f9 SW |
857 | status = "okay"; |
858 | spi-max-frequency = <25000000>; | |
859 | spi-flash@0 { | |
860 | compatible = "winbond,w25q32dw"; | |
861 | reg = <0>; | |
862 | spi-max-frequency = <20000000>; | |
863 | }; | |
864 | }; | |
865 | ||
e30cb238 | 866 | pmc@0,7000e400 { |
a1425d42 | 867 | nvidia,invert-interrupt; |
6ec1d127 JL |
868 | nvidia,suspend-mode = <1>; |
869 | nvidia,cpu-pwr-good-time = <500>; | |
870 | nvidia,cpu-pwr-off-time = <300>; | |
871 | nvidia,core-pwr-good-time = <641 3845>; | |
872 | nvidia,core-pwr-off-time = <61036>; | |
873 | nvidia,core-power-req-active-high; | |
874 | nvidia,sys-clock-req-active-high; | |
a1425d42 | 875 | }; |
3b86baf2 | 876 | |
e30cb238 | 877 | sdhci@0,700b0400 { |
784c7444 SW |
878 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; |
879 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; | |
2be8f4a6 | 880 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; |
784c7444 SW |
881 | status = "okay"; |
882 | bus-width = <4>; | |
49228cae | 883 | vqmmc-supply = <&vddio_sdmmc3>; |
784c7444 SW |
884 | }; |
885 | ||
e30cb238 | 886 | sdhci@0,700b0600 { |
784c7444 SW |
887 | status = "okay"; |
888 | bus-width = <8>; | |
889 | }; | |
890 | ||
e30cb238 SW |
891 | ahub@0,70300000 { |
892 | i2s@0,70301100 { | |
b0e1caee SW |
893 | status = "okay"; |
894 | }; | |
895 | }; | |
896 | ||
e30cb238 | 897 | usb@0,7d000000 { |
431b7be0 TR |
898 | status = "okay"; |
899 | }; | |
900 | ||
e30cb238 | 901 | usb-phy@0,7d000000 { |
431b7be0 TR |
902 | status = "okay"; |
903 | vbus-supply = <&vdd_usb1_vbus>; | |
904 | }; | |
905 | ||
e30cb238 | 906 | usb@0,7d004000 { |
431b7be0 TR |
907 | status = "okay"; |
908 | }; | |
909 | ||
e30cb238 | 910 | usb-phy@0,7d004000 { |
431b7be0 TR |
911 | status = "okay"; |
912 | vbus-supply = <&vdd_run_cam>; | |
913 | }; | |
914 | ||
e30cb238 | 915 | usb@0,7d008000 { |
431b7be0 TR |
916 | status = "okay"; |
917 | }; | |
918 | ||
e30cb238 | 919 | usb-phy@0,7d008000 { |
431b7be0 TR |
920 | status = "okay"; |
921 | vbus-supply = <&vdd_usb3_vbus>; | |
922 | }; | |
923 | ||
40e231c7 TR |
924 | backlight: backlight { |
925 | compatible = "pwm-backlight"; | |
926 | ||
927 | enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; | |
928 | power-supply = <&vdd_led>; | |
929 | pwms = <&pwm 1 1000000>; | |
930 | ||
931 | brightness-levels = <0 4 8 16 32 64 128 255>; | |
932 | default-brightness-level = <6>; | |
933 | }; | |
934 | ||
3b86baf2 JL |
935 | clocks { |
936 | compatible = "simple-bus"; | |
937 | #address-cells = <1>; | |
938 | #size-cells = <0>; | |
939 | ||
940 | clk32k_in: clock@0 { | |
941 | compatible = "fixed-clock"; | |
4b356608 | 942 | reg = <0>; |
3b86baf2 JL |
943 | #clock-cells = <0>; |
944 | clock-frequency = <32768>; | |
945 | }; | |
946 | }; | |
b0e1caee | 947 | |
3f748d44 TR |
948 | gpio-keys { |
949 | compatible = "gpio-keys"; | |
950 | ||
951 | power { | |
952 | label = "Power"; | |
953 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; | |
954 | linux,code = <KEY_POWER>; | |
955 | debounce-interval = <10>; | |
956 | gpio-key,wakeup; | |
957 | }; | |
958 | }; | |
959 | ||
40e231c7 TR |
960 | panel: panel { |
961 | compatible = "lg,lp129qe", "simple-panel"; | |
962 | ||
963 | backlight = <&backlight>; | |
964 | ddc-i2c-bus = <&dpaux>; | |
965 | }; | |
966 | ||
fcacaba7 LD |
967 | regulators { |
968 | compatible = "simple-bus"; | |
969 | #address-cells = <1>; | |
970 | #size-cells = <0>; | |
971 | ||
af144b8d | 972 | vdd_mux: regulator@0 { |
fcacaba7 LD |
973 | compatible = "regulator-fixed"; |
974 | reg = <0>; | |
af144b8d TR |
975 | regulator-name = "+VDD_MUX"; |
976 | regulator-min-microvolt = <12000000>; | |
977 | regulator-max-microvolt = <12000000>; | |
fcacaba7 | 978 | regulator-always-on; |
af144b8d | 979 | regulator-boot-on; |
fcacaba7 LD |
980 | }; |
981 | ||
af144b8d | 982 | vdd_5v0_sys: regulator@1 { |
fcacaba7 LD |
983 | compatible = "regulator-fixed"; |
984 | reg = <1>; | |
af144b8d TR |
985 | regulator-name = "+5V_SYS"; |
986 | regulator-min-microvolt = <5000000>; | |
987 | regulator-max-microvolt = <5000000>; | |
fcacaba7 LD |
988 | regulator-always-on; |
989 | regulator-boot-on; | |
af144b8d | 990 | vin-supply = <&vdd_mux>; |
fcacaba7 LD |
991 | }; |
992 | ||
af144b8d | 993 | vdd_3v3_sys: regulator@2 { |
fcacaba7 LD |
994 | compatible = "regulator-fixed"; |
995 | reg = <2>; | |
af144b8d | 996 | regulator-name = "+3.3V_SYS"; |
fcacaba7 LD |
997 | regulator-min-microvolt = <3300000>; |
998 | regulator-max-microvolt = <3300000>; | |
af144b8d TR |
999 | regulator-always-on; |
1000 | regulator-boot-on; | |
1001 | vin-supply = <&vdd_mux>; | |
fcacaba7 LD |
1002 | }; |
1003 | ||
af144b8d | 1004 | vdd_3v3_run: regulator@3 { |
fcacaba7 LD |
1005 | compatible = "regulator-fixed"; |
1006 | reg = <3>; | |
af144b8d TR |
1007 | regulator-name = "+3.3V_RUN"; |
1008 | regulator-min-microvolt = <3300000>; | |
1009 | regulator-max-microvolt = <3300000>; | |
c7fe7672 SW |
1010 | regulator-always-on; |
1011 | regulator-boot-on; | |
fdc44f94 | 1012 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
fcacaba7 | 1013 | enable-active-high; |
af144b8d | 1014 | vin-supply = <&vdd_3v3_sys>; |
fcacaba7 LD |
1015 | }; |
1016 | ||
af144b8d | 1017 | vdd_3v3_hdmi: regulator@4 { |
fcacaba7 LD |
1018 | compatible = "regulator-fixed"; |
1019 | reg = <4>; | |
af144b8d | 1020 | regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; |
fcacaba7 LD |
1021 | regulator-min-microvolt = <3300000>; |
1022 | regulator-max-microvolt = <3300000>; | |
af144b8d | 1023 | vin-supply = <&vdd_3v3_run>; |
fcacaba7 LD |
1024 | }; |
1025 | ||
af144b8d | 1026 | vdd_led: regulator@5 { |
fcacaba7 LD |
1027 | compatible = "regulator-fixed"; |
1028 | reg = <5>; | |
af144b8d TR |
1029 | regulator-name = "+VDD_LED"; |
1030 | gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; | |
fcacaba7 | 1031 | enable-active-high; |
af144b8d | 1032 | vin-supply = <&vdd_mux>; |
fcacaba7 LD |
1033 | }; |
1034 | ||
af144b8d | 1035 | vdd_5v0_ts: regulator@6 { |
fcacaba7 LD |
1036 | compatible = "regulator-fixed"; |
1037 | reg = <6>; | |
af144b8d | 1038 | regulator-name = "+5V_VDD_TS_SW"; |
fcacaba7 LD |
1039 | regulator-min-microvolt = <5000000>; |
1040 | regulator-max-microvolt = <5000000>; | |
1041 | regulator-boot-on; | |
af144b8d | 1042 | gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; |
fcacaba7 | 1043 | enable-active-high; |
af144b8d | 1044 | vin-supply = <&vdd_5v0_sys>; |
fcacaba7 LD |
1045 | }; |
1046 | ||
af144b8d | 1047 | vdd_usb1_vbus: regulator@7 { |
fcacaba7 LD |
1048 | compatible = "regulator-fixed"; |
1049 | reg = <7>; | |
af144b8d | 1050 | regulator-name = "+5V_USB_HS"; |
fcacaba7 LD |
1051 | regulator-min-microvolt = <5000000>; |
1052 | regulator-max-microvolt = <5000000>; | |
af144b8d | 1053 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; |
fcacaba7 | 1054 | enable-active-high; |
fcacaba7 | 1055 | gpio-open-drain; |
af144b8d | 1056 | vin-supply = <&vdd_5v0_sys>; |
fcacaba7 LD |
1057 | }; |
1058 | ||
af144b8d | 1059 | vdd_usb3_vbus: regulator@8 { |
fcacaba7 LD |
1060 | compatible = "regulator-fixed"; |
1061 | reg = <8>; | |
af144b8d TR |
1062 | regulator-name = "+5V_USB_SS"; |
1063 | regulator-min-microvolt = <5000000>; | |
1064 | regulator-max-microvolt = <5000000>; | |
1065 | gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; | |
1066 | enable-active-high; | |
1067 | gpio-open-drain; | |
1068 | vin-supply = <&vdd_5v0_sys>; | |
1069 | }; | |
1070 | ||
1071 | vdd_3v3_panel: regulator@9 { | |
1072 | compatible = "regulator-fixed"; | |
1073 | reg = <9>; | |
1074 | regulator-name = "+3.3V_PANEL"; | |
fcacaba7 LD |
1075 | regulator-min-microvolt = <3300000>; |
1076 | regulator-max-microvolt = <3300000>; | |
fdc44f94 | 1077 | gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; |
af144b8d TR |
1078 | enable-active-high; |
1079 | vin-supply = <&vdd_3v3_run>; | |
1080 | }; | |
1081 | ||
1082 | vdd_3v3_lp0: regulator@10 { | |
1083 | compatible = "regulator-fixed"; | |
1084 | reg = <10>; | |
1085 | regulator-name = "+3.3V_LP0"; | |
1086 | regulator-min-microvolt = <3300000>; | |
1087 | regulator-max-microvolt = <3300000>; | |
1088 | /* | |
1089 | * TODO: find a way to wire this up with the USB EHCI | |
1090 | * controllers so that it can be enabled on demand. | |
1091 | */ | |
1092 | regulator-always-on; | |
fdc44f94 | 1093 | gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; |
fcacaba7 | 1094 | enable-active-high; |
af144b8d | 1095 | vin-supply = <&vdd_3v3_sys>; |
fcacaba7 | 1096 | }; |
329c39f8 TR |
1097 | |
1098 | vdd_hdmi_pll: regulator@11 { | |
1099 | compatible = "regulator-fixed"; | |
1100 | reg = <11>; | |
1101 | regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; | |
1102 | regulator-min-microvolt = <1050000>; | |
1103 | regulator-max-microvolt = <1050000>; | |
1104 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; | |
1105 | vin-supply = <&vdd_1v05_run>; | |
1106 | }; | |
1107 | ||
1108 | vdd_5v0_hdmi: regulator@12 { | |
1109 | compatible = "regulator-fixed"; | |
1110 | reg = <12>; | |
1111 | regulator-name = "+5V_HDMI_CON"; | |
1112 | regulator-min-microvolt = <5000000>; | |
1113 | regulator-max-microvolt = <5000000>; | |
1114 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; | |
1115 | enable-active-high; | |
1116 | vin-supply = <&vdd_5v0_sys>; | |
1117 | }; | |
fcacaba7 LD |
1118 | }; |
1119 | ||
b0e1caee SW |
1120 | sound { |
1121 | compatible = "nvidia,tegra-audio-max98090-venice2", | |
1122 | "nvidia,tegra-audio-max98090"; | |
1123 | nvidia,model = "NVIDIA Tegra Venice2"; | |
1124 | ||
1125 | nvidia,audio-routing = | |
1126 | "Headphones", "HPR", | |
1127 | "Headphones", "HPL", | |
1128 | "Speakers", "SPKR", | |
1129 | "Speakers", "SPKL", | |
1130 | "Mic Jack", "MICBIAS", | |
1131 | "IN34", "Mic Jack"; | |
1132 | ||
1133 | nvidia,i2s-controller = <&tegra_i2s1>; | |
1134 | nvidia,audio-codec = <&acodec>; | |
1135 | ||
1136 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, | |
1137 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, | |
1138 | <&tegra_car TEGRA124_CLK_EXTERN1>; | |
1139 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
1140 | }; | |
a1425d42 | 1141 | }; |
f01dd55a DA |
1142 | |
1143 | #include "cros-ec-keyboard.dtsi" |