projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 3b86baf2 | 1 | #include <dt-bindings/clock/tegra124-car.h> |
| 0a9375d1 | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
| 5b605d44 | 3 | #include <dt-bindings/memory/tegra124-mc.h> |
| 4b20bcbe | 4 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
| ce90d32d | 5 | #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> |
| ad03b1a7 | 6 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 26b76f80 | 7 | #include <dt-bindings/thermal/tegra124-soctherm.h> |
| ad03b1a7 JL |
8 | |
| 9 | #include "skeleton.dtsi" | |
| 10 | ||
| 11 | / { | |
| 12 | compatible = "nvidia,tegra124"; | |
| 870c81a4 | 13 | interrupt-parent = <&lic>; |
| e30cb238 SW |
14 | #address-cells = <2>; |
| 15 | #size-cells = <2>; | |
| ad03b1a7 | 16 | |
| ee588e2a TR |
17 | pcie-controller@0,01003000 { |
| 18 | compatible = "nvidia,tegra124-pcie"; | |
| 19 | device_type = "pci"; | |
| 20 | reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ | |
| 21 | 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ | |
| 22 | 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ | |
| 23 | reg-names = "pads", "afi", "cs"; | |
| 24 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ | |
| 25 | <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ | |
| 26 | interrupt-names = "intr", "msi"; | |
| 27 | ||
| 28 | #interrupt-cells = <1>; | |
| 29 | interrupt-map-mask = <0 0 0 0>; | |
| 30 | interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
| 31 | ||
| 32 | bus-range = <0x00 0xff>; | |
| 33 | #address-cells = <3>; | |
| 34 | #size-cells = <2>; | |
| 35 | ||
| 36 | ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ | |
| 37 | 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ | |
| 38 | 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ | |
| 39 | 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ | |
| 40 | 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ | |
| 41 | ||
| 42 | clocks = <&tegra_car TEGRA124_CLK_PCIE>, | |
| 43 | <&tegra_car TEGRA124_CLK_AFI>, | |
| 44 | <&tegra_car TEGRA124_CLK_PLL_E>, | |
| 45 | <&tegra_car TEGRA124_CLK_CML0>; | |
| 46 | clock-names = "pex", "afi", "pll_e", "cml"; | |
| 47 | resets = <&tegra_car 70>, | |
| 48 | <&tegra_car 72>, | |
| 49 | <&tegra_car 74>; | |
| 50 | reset-names = "pex", "afi", "pcie_x"; | |
| 51 | status = "disabled"; | |
| 52 | ||
| 53 | phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; | |
| 54 | phy-names = "pcie"; | |
| 55 | ||
| 56 | pci@1,0 { | |
| 57 | device_type = "pci"; | |
| 58 | assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; | |
| 59 | reg = <0x000800 0 0 0 0>; | |
| 60 | status = "disabled"; | |
| 61 | ||
| 62 | #address-cells = <3>; | |
| 63 | #size-cells = <2>; | |
| 64 | ranges; | |
| 65 | ||
| 66 | nvidia,num-lanes = <2>; | |
| 67 | }; | |
| 68 | ||
| 69 | pci@2,0 { | |
| 70 | device_type = "pci"; | |
| 71 | assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; | |
| 72 | reg = <0x001000 0 0 0 0>; | |
| 73 | status = "disabled"; | |
| 74 | ||
| 75 | #address-cells = <3>; | |
| 76 | #size-cells = <2>; | |
| 77 | ranges; | |
| 78 | ||
| 79 | nvidia,num-lanes = <1>; | |
| 80 | }; | |
| 81 | }; | |
| 82 | ||
| e30cb238 | 83 | host1x@0,50000000 { |
| ad6be7d1 | 84 | compatible = "nvidia,tegra124-host1x", "simple-bus"; |
| e30cb238 | 85 | reg = <0x0 0x50000000 0x0 0x00034000>; |
| ad6be7d1 TR |
86 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
| 87 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ | |
| 88 | clocks = <&tegra_car TEGRA124_CLK_HOST1X>; | |
| 89 | resets = <&tegra_car 28>; | |
| 90 | reset-names = "host1x"; | |
| 91 | ||
| e30cb238 SW |
92 | #address-cells = <2>; |
| 93 | #size-cells = <2>; | |
| ad6be7d1 | 94 | |
| e30cb238 | 95 | ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; |
| ad6be7d1 | 96 | |
| e30cb238 | 97 | dc@0,54200000 { |
| ad6be7d1 | 98 | compatible = "nvidia,tegra124-dc"; |
| e30cb238 | 99 | reg = <0x0 0x54200000 0x0 0x00040000>; |
| ad6be7d1 TR |
100 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 101 | clocks = <&tegra_car TEGRA124_CLK_DISP1>, | |
| 102 | <&tegra_car TEGRA124_CLK_PLL_P>; | |
| 103 | clock-names = "dc", "parent"; | |
| 104 | resets = <&tegra_car 27>; | |
| 105 | reset-names = "dc"; | |
| 106 | ||
| 5b605d44 TR |
107 | iommus = <&mc TEGRA_SWGROUP_DC>; |
| 108 | ||
| ad6be7d1 TR |
109 | nvidia,head = <0>; |
| 110 | }; | |
| 111 | ||
| e30cb238 | 112 | dc@0,54240000 { |
| ad6be7d1 | 113 | compatible = "nvidia,tegra124-dc"; |
| e30cb238 | 114 | reg = <0x0 0x54240000 0x0 0x00040000>; |
| ad6be7d1 TR |
115 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 116 | clocks = <&tegra_car TEGRA124_CLK_DISP2>, | |
| 117 | <&tegra_car TEGRA124_CLK_PLL_P>; | |
| 118 | clock-names = "dc", "parent"; | |
| 119 | resets = <&tegra_car 26>; | |
| 120 | reset-names = "dc"; | |
| 121 | ||
| 5b605d44 TR |
122 | iommus = <&mc TEGRA_SWGROUP_DCB>; |
| 123 | ||
| ad6be7d1 TR |
124 | nvidia,head = <1>; |
| 125 | }; | |
| d72be031 | 126 | |
| 9dd604df TR |
127 | hdmi@0,54280000 { |
| 128 | compatible = "nvidia,tegra124-hdmi"; | |
| 129 | reg = <0x0 0x54280000 0x0 0x00040000>; | |
| 130 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 131 | clocks = <&tegra_car TEGRA124_CLK_HDMI>, | |
| 132 | <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; | |
| 133 | clock-names = "hdmi", "parent"; | |
| 134 | resets = <&tegra_car 51>; | |
| 135 | reset-names = "hdmi"; | |
| 136 | status = "disabled"; | |
| 137 | }; | |
| 138 | ||
| e30cb238 | 139 | sor@0,54540000 { |
| d72be031 | 140 | compatible = "nvidia,tegra124-sor"; |
| e30cb238 | 141 | reg = <0x0 0x54540000 0x0 0x00040000>; |
| d72be031 TR |
142 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 143 | clocks = <&tegra_car TEGRA124_CLK_SOR0>, | |
| 144 | <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, | |
| 145 | <&tegra_car TEGRA124_CLK_PLL_DP>, | |
| 146 | <&tegra_car TEGRA124_CLK_CLK_M>; | |
| 147 | clock-names = "sor", "parent", "dp", "safe"; | |
| 148 | resets = <&tegra_car 182>; | |
| 149 | reset-names = "sor"; | |
| 150 | status = "disabled"; | |
| 151 | }; | |
| 152 | ||
| edfbad06 | 153 | dpaux: dpaux@0,545c0000 { |
| d72be031 | 154 | compatible = "nvidia,tegra124-dpaux"; |
| e30cb238 | 155 | reg = <0x0 0x545c0000 0x0 0x00040000>; |
| d72be031 TR |
156 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; |
| 157 | clocks = <&tegra_car TEGRA124_CLK_DPAUX>, | |
| 158 | <&tegra_car TEGRA124_CLK_PLL_DP>; | |
| 159 | clock-names = "dpaux", "parent"; | |
| 160 | resets = <&tegra_car 181>; | |
| 161 | reset-names = "dpaux"; | |
| 162 | status = "disabled"; | |
| 163 | }; | |
| ad6be7d1 TR |
164 | }; |
| 165 | ||
| e30cb238 | 166 | gic: interrupt-controller@0,50041000 { |
| ad03b1a7 JL |
167 | compatible = "arm,cortex-a15-gic"; |
| 168 | #interrupt-cells = <3>; | |
| 169 | interrupt-controller; | |
| e30cb238 SW |
170 | reg = <0x0 0x50041000 0x0 0x1000>, |
| 171 | <0x0 0x50042000 0x0 0x1000>, | |
| 172 | <0x0 0x50044000 0x0 0x2000>, | |
| 173 | <0x0 0x50046000 0x0 0x2000>; | |
| ad03b1a7 JL |
174 | interrupts = <GIC_PPI 9 |
| 175 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 870c81a4 | 176 | interrupt-parent = <&gic>; |
| ad03b1a7 JL |
177 | }; |
| 178 | ||
| d86b1e8d TR |
179 | gpu@0,57000000 { |
| 180 | compatible = "nvidia,gk20a"; | |
| 181 | reg = <0x0 0x57000000 0x0 0x01000000>, | |
| 182 | <0x0 0x58000000 0x0 0x01000000>; | |
| 183 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, | |
| 184 | <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; | |
| 185 | interrupt-names = "stall", "nonstall"; | |
| 186 | clocks = <&tegra_car TEGRA124_CLK_GPU>, | |
| 187 | <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; | |
| 188 | clock-names = "gpu", "pwr"; | |
| 189 | resets = <&tegra_car 184>; | |
| 190 | reset-names = "gpu"; | |
| 191 | status = "disabled"; | |
| 192 | }; | |
| 193 | ||
| 870c81a4 MZ |
194 | lic: interrupt-controller@60004000 { |
| 195 | compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; | |
| 196 | reg = <0x0 0x60004000 0x0 0x100>, | |
| 197 | <0x0 0x60004100 0x0 0x100>, | |
| 198 | <0x0 0x60004200 0x0 0x100>, | |
| 199 | <0x0 0x60004300 0x0 0x100>, | |
| 200 | <0x0 0x60004400 0x0 0x100>; | |
| 201 | interrupt-controller; | |
| 202 | #interrupt-cells = <3>; | |
| 203 | interrupt-parent = <&gic>; | |
| 204 | }; | |
| 205 | ||
| e30cb238 | 206 | timer@0,60005000 { |
| ad03b1a7 | 207 | compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; |
| e30cb238 | 208 | reg = <0x0 0x60005000 0x0 0x400>; |
| ad03b1a7 JL |
209 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 210 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
| 211 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
| 212 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
| 213 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
| 214 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; | |
| 3b86baf2 JL |
215 | clocks = <&tegra_car TEGRA124_CLK_TIMER>; |
| 216 | }; | |
| 217 | ||
| e30cb238 | 218 | tegra_car: clock@0,60006000 { |
| 3b86baf2 | 219 | compatible = "nvidia,tegra124-car"; |
| e30cb238 | 220 | reg = <0x0 0x60006000 0x0 0x1000>; |
| 3b86baf2 | 221 | #clock-cells = <1>; |
| f71e4f03 | 222 | #reset-cells = <1>; |
| b273c887 | 223 | nvidia,external-memory-controller = <&emc>; |
| ad03b1a7 JL |
224 | }; |
| 225 | ||
| b1023134 TR |
226 | flow-controller@0,60007000 { |
| 227 | compatible = "nvidia,tegra124-flowctrl"; | |
| 228 | reg = <0x0 0x60007000 0x0 0x1000>; | |
| 229 | }; | |
| 230 | ||
| c5f8e8ca TV |
231 | actmon@0,6000c800 { |
| 232 | compatible = "nvidia,tegra124-actmon"; | |
| 233 | reg = <0x0 0x6000c800 0x0 0x400>; | |
| 234 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
| 235 | clocks = <&tegra_car TEGRA124_CLK_ACTMON>, | |
| 236 | <&tegra_car TEGRA124_CLK_EMC>; | |
| 237 | clock-names = "actmon", "emc"; | |
| 238 | resets = <&tegra_car 119>; | |
| 239 | reset-names = "actmon"; | |
| 240 | }; | |
| 241 | ||
| e30cb238 | 242 | gpio: gpio@0,6000d000 { |
| 0a9375d1 | 243 | compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; |
| e30cb238 | 244 | reg = <0x0 0x6000d000 0x0 0x1000>; |
| 0a9375d1 SW |
245 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 246 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
| 247 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
| 248 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
| 249 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
| 250 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
| 251 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, | |
| 252 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; | |
| 253 | #gpio-cells = <2>; | |
| 254 | gpio-controller; | |
| 255 | #interrupt-cells = <2>; | |
| 256 | interrupt-controller; | |
| 257 | }; | |
| 258 | ||
| e30cb238 | 259 | apbdma: dma@0,60020000 { |
| 2f5a913e | 260 | compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; |
| e30cb238 | 261 | reg = <0x0 0x60020000 0x0 0x1400>; |
| 2f5a913e SW |
262 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 263 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
| 264 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
| 265 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
| 266 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
| 267 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
| 268 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
| 269 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
| 270 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
| 271 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
| 272 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
| 273 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
| 274 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
| 275 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
| 276 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
| 277 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, | |
| 278 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
| 279 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | |
| 280 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | |
| 281 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
| 282 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, | |
| 283 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, | |
| 284 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
| 285 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
| 286 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
| 287 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
| 288 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
| 289 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, | |
| 290 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, | |
| 291 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, | |
| 292 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
| 293 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
| 294 | clocks = <&tegra_car TEGRA124_CLK_APBDMA>; | |
| 295 | resets = <&tegra_car 34>; | |
| 296 | reset-names = "dma"; | |
| 297 | #dma-cells = <1>; | |
| 298 | }; | |
| 299 | ||
| 155dfc7b PDS |
300 | apbmisc@0,70000800 { |
| 301 | compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; | |
| 302 | reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ | |
| 303 | <0x0 0x7000E864 0x0 0x04>; /* Strapping options */ | |
| 304 | }; | |
| 305 | ||
| e30cb238 | 306 | pinmux: pinmux@0,70000868 { |
| caefe637 | 307 | compatible = "nvidia,tegra124-pinmux"; |
| e30cb238 | 308 | reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ |
| 49727d30 SP |
309 | <0x0 0x70003000 0x0 0x434>, /* Mux registers */ |
| 310 | <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ | |
| caefe637 SW |
311 | }; |
| 312 | ||
| ad03b1a7 JL |
313 | /* |
| 314 | * There are two serial driver i.e. 8250 based simple serial | |
| 315 | * driver and APB DMA based serial driver for higher baudrate | |
| 316 | * and performace. To enable the 8250 based driver, the compatible | |
| 317 | * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable | |
| 318 | * the APB DMA based serial driver, the comptible is | |
| 319 | * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". | |
| 320 | */ | |
| 121a2f6d | 321 | uarta: serial@0,70006000 { |
| ad03b1a7 | 322 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
| e30cb238 | 323 | reg = <0x0 0x70006000 0x0 0x40>; |
| ad03b1a7 JL |
324 | reg-shift = <2>; |
| 325 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
| 3b86baf2 | 326 | clocks = <&tegra_car TEGRA124_CLK_UARTA>; |
| f71e4f03 SW |
327 | resets = <&tegra_car 6>; |
| 328 | reset-names = "serial"; | |
| 2f5a913e SW |
329 | dmas = <&apbdma 8>, <&apbdma 8>; |
| 330 | dma-names = "rx", "tx"; | |
| ad03b1a7 JL |
331 | status = "disabled"; |
| 332 | }; | |
| 333 | ||
| 121a2f6d | 334 | uartb: serial@0,70006040 { |
| ad03b1a7 | 335 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
| e30cb238 | 336 | reg = <0x0 0x70006040 0x0 0x40>; |
| ad03b1a7 JL |
337 | reg-shift = <2>; |
| 338 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
| 3b86baf2 | 339 | clocks = <&tegra_car TEGRA124_CLK_UARTB>; |
| f71e4f03 SW |
340 | resets = <&tegra_car 7>; |
| 341 | reset-names = "serial"; | |
| 2f5a913e SW |
342 | dmas = <&apbdma 9>, <&apbdma 9>; |
| 343 | dma-names = "rx", "tx"; | |
| ad03b1a7 JL |
344 | status = "disabled"; |
| 345 | }; | |
| 346 | ||
| 121a2f6d | 347 | uartc: serial@0,70006200 { |
| ad03b1a7 | 348 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
| e30cb238 | 349 | reg = <0x0 0x70006200 0x0 0x40>; |
| ad03b1a7 JL |
350 | reg-shift = <2>; |
| 351 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
| 3b86baf2 | 352 | clocks = <&tegra_car TEGRA124_CLK_UARTC>; |
| f71e4f03 SW |
353 | resets = <&tegra_car 55>; |
| 354 | reset-names = "serial"; | |
| 2f5a913e SW |
355 | dmas = <&apbdma 10>, <&apbdma 10>; |
| 356 | dma-names = "rx", "tx"; | |
| ad03b1a7 JL |
357 | status = "disabled"; |
| 358 | }; | |
| 359 | ||
| 121a2f6d | 360 | uartd: serial@0,70006300 { |
| ad03b1a7 | 361 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
| e30cb238 | 362 | reg = <0x0 0x70006300 0x0 0x40>; |
| ad03b1a7 JL |
363 | reg-shift = <2>; |
| 364 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
| 3b86baf2 | 365 | clocks = <&tegra_car TEGRA124_CLK_UARTD>; |
| f71e4f03 SW |
366 | resets = <&tegra_car 65>; |
| 367 | reset-names = "serial"; | |
| 2f5a913e SW |
368 | dmas = <&apbdma 19>, <&apbdma 19>; |
| 369 | dma-names = "rx", "tx"; | |
| ad03b1a7 JL |
370 | status = "disabled"; |
| 371 | }; | |
| 372 | ||
| edfbad06 | 373 | pwm: pwm@0,7000a000 { |
| 111a1fc2 | 374 | compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; |
| e30cb238 | 375 | reg = <0x0 0x7000a000 0x0 0x100>; |
| 111a1fc2 TR |
376 | #pwm-cells = <2>; |
| 377 | clocks = <&tegra_car TEGRA124_CLK_PWM>; | |
| 378 | resets = <&tegra_car 17>; | |
| 379 | reset-names = "pwm"; | |
| 380 | status = "disabled"; | |
| 381 | }; | |
| 382 | ||
| e30cb238 | 383 | i2c@0,7000c000 { |
| 4f607460 | 384 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 385 | reg = <0x0 0x7000c000 0x0 0x100>; |
| 4f607460 SW |
386 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 387 | #address-cells = <1>; | |
| 388 | #size-cells = <0>; | |
| 389 | clocks = <&tegra_car TEGRA124_CLK_I2C1>; | |
| 390 | clock-names = "div-clk"; | |
| 391 | resets = <&tegra_car 12>; | |
| 392 | reset-names = "i2c"; | |
| 393 | dmas = <&apbdma 21>, <&apbdma 21>; | |
| 394 | dma-names = "rx", "tx"; | |
| 395 | status = "disabled"; | |
| 396 | }; | |
| 397 | ||
| e30cb238 | 398 | i2c@0,7000c400 { |
| 4f607460 | 399 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 400 | reg = <0x0 0x7000c400 0x0 0x100>; |
| 4f607460 SW |
401 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| 402 | #address-cells = <1>; | |
| 403 | #size-cells = <0>; | |
| 404 | clocks = <&tegra_car TEGRA124_CLK_I2C2>; | |
| 405 | clock-names = "div-clk"; | |
| 406 | resets = <&tegra_car 54>; | |
| 407 | reset-names = "i2c"; | |
| 408 | dmas = <&apbdma 22>, <&apbdma 22>; | |
| 409 | dma-names = "rx", "tx"; | |
| 410 | status = "disabled"; | |
| 411 | }; | |
| 412 | ||
| e30cb238 | 413 | i2c@0,7000c500 { |
| 4f607460 | 414 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 415 | reg = <0x0 0x7000c500 0x0 0x100>; |
| 4f607460 SW |
416 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 417 | #address-cells = <1>; | |
| 418 | #size-cells = <0>; | |
| 419 | clocks = <&tegra_car TEGRA124_CLK_I2C3>; | |
| 420 | clock-names = "div-clk"; | |
| 421 | resets = <&tegra_car 67>; | |
| 422 | reset-names = "i2c"; | |
| 423 | dmas = <&apbdma 23>, <&apbdma 23>; | |
| 424 | dma-names = "rx", "tx"; | |
| 425 | status = "disabled"; | |
| 426 | }; | |
| 427 | ||
| e30cb238 | 428 | i2c@0,7000c700 { |
| 4f607460 | 429 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 430 | reg = <0x0 0x7000c700 0x0 0x100>; |
| 4f607460 SW |
431 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| 432 | #address-cells = <1>; | |
| 433 | #size-cells = <0>; | |
| 434 | clocks = <&tegra_car TEGRA124_CLK_I2C4>; | |
| 435 | clock-names = "div-clk"; | |
| 436 | resets = <&tegra_car 103>; | |
| 437 | reset-names = "i2c"; | |
| 438 | dmas = <&apbdma 26>, <&apbdma 26>; | |
| 439 | dma-names = "rx", "tx"; | |
| 440 | status = "disabled"; | |
| 441 | }; | |
| 442 | ||
| e30cb238 | 443 | i2c@0,7000d000 { |
| 4f607460 | 444 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 445 | reg = <0x0 0x7000d000 0x0 0x100>; |
| 4f607460 SW |
446 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
| 447 | #address-cells = <1>; | |
| 448 | #size-cells = <0>; | |
| 449 | clocks = <&tegra_car TEGRA124_CLK_I2C5>; | |
| 450 | clock-names = "div-clk"; | |
| 451 | resets = <&tegra_car 47>; | |
| 452 | reset-names = "i2c"; | |
| 453 | dmas = <&apbdma 24>, <&apbdma 24>; | |
| 454 | dma-names = "rx", "tx"; | |
| 455 | status = "disabled"; | |
| 456 | }; | |
| 457 | ||
| e30cb238 | 458 | i2c@0,7000d100 { |
| 4f607460 | 459 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 460 | reg = <0x0 0x7000d100 0x0 0x100>; |
| 4f607460 SW |
461 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| 462 | #address-cells = <1>; | |
| 463 | #size-cells = <0>; | |
| 464 | clocks = <&tegra_car TEGRA124_CLK_I2C6>; | |
| 465 | clock-names = "div-clk"; | |
| 466 | resets = <&tegra_car 166>; | |
| 467 | reset-names = "i2c"; | |
| 468 | dmas = <&apbdma 30>, <&apbdma 30>; | |
| 469 | dma-names = "rx", "tx"; | |
| 470 | status = "disabled"; | |
| 471 | }; | |
| 472 | ||
| e30cb238 | 473 | spi@0,7000d400 { |
| 9f1ac560 | 474 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 475 | reg = <0x0 0x7000d400 0x0 0x200>; |
| 9f1ac560 TR |
476 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| 477 | #address-cells = <1>; | |
| 478 | #size-cells = <0>; | |
| 479 | clocks = <&tegra_car TEGRA124_CLK_SBC1>; | |
| 480 | clock-names = "spi"; | |
| 481 | resets = <&tegra_car 41>; | |
| 482 | reset-names = "spi"; | |
| 483 | dmas = <&apbdma 15>, <&apbdma 15>; | |
| 484 | dma-names = "rx", "tx"; | |
| 485 | status = "disabled"; | |
| 486 | }; | |
| 487 | ||
| e30cb238 | 488 | spi@0,7000d600 { |
| 9f1ac560 | 489 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 490 | reg = <0x0 0x7000d600 0x0 0x200>; |
| 9f1ac560 TR |
491 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 492 | #address-cells = <1>; | |
| 493 | #size-cells = <0>; | |
| 494 | clocks = <&tegra_car TEGRA124_CLK_SBC2>; | |
| 495 | clock-names = "spi"; | |
| 496 | resets = <&tegra_car 44>; | |
| 497 | reset-names = "spi"; | |
| 498 | dmas = <&apbdma 16>, <&apbdma 16>; | |
| 499 | dma-names = "rx", "tx"; | |
| 500 | status = "disabled"; | |
| 501 | }; | |
| 502 | ||
| e30cb238 | 503 | spi@0,7000d800 { |
| 9f1ac560 | 504 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 505 | reg = <0x0 0x7000d800 0x0 0x200>; |
| 9f1ac560 TR |
506 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 507 | #address-cells = <1>; | |
| 508 | #size-cells = <0>; | |
| 509 | clocks = <&tegra_car TEGRA124_CLK_SBC3>; | |
| 510 | clock-names = "spi"; | |
| 511 | resets = <&tegra_car 46>; | |
| 512 | reset-names = "spi"; | |
| 513 | dmas = <&apbdma 17>, <&apbdma 17>; | |
| 514 | dma-names = "rx", "tx"; | |
| 515 | status = "disabled"; | |
| 516 | }; | |
| 517 | ||
| e30cb238 | 518 | spi@0,7000da00 { |
| 9f1ac560 | 519 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 520 | reg = <0x0 0x7000da00 0x0 0x200>; |
| 9f1ac560 TR |
521 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| 522 | #address-cells = <1>; | |
| 523 | #size-cells = <0>; | |
| 524 | clocks = <&tegra_car TEGRA124_CLK_SBC4>; | |
| 525 | clock-names = "spi"; | |
| 526 | resets = <&tegra_car 68>; | |
| 527 | reset-names = "spi"; | |
| 528 | dmas = <&apbdma 18>, <&apbdma 18>; | |
| 529 | dma-names = "rx", "tx"; | |
| 530 | status = "disabled"; | |
| 531 | }; | |
| 532 | ||
| e30cb238 | 533 | spi@0,7000dc00 { |
| 9f1ac560 | 534 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 535 | reg = <0x0 0x7000dc00 0x0 0x200>; |
| 9f1ac560 TR |
536 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| 537 | #address-cells = <1>; | |
| 538 | #size-cells = <0>; | |
| 539 | clocks = <&tegra_car TEGRA124_CLK_SBC5>; | |
| 540 | clock-names = "spi"; | |
| 541 | resets = <&tegra_car 104>; | |
| 542 | reset-names = "spi"; | |
| 543 | dmas = <&apbdma 27>, <&apbdma 27>; | |
| 544 | dma-names = "rx", "tx"; | |
| 545 | status = "disabled"; | |
| 546 | }; | |
| 547 | ||
| e30cb238 | 548 | spi@0,7000de00 { |
| 9f1ac560 | 549 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 550 | reg = <0x0 0x7000de00 0x0 0x200>; |
| 9f1ac560 TR |
551 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
| 552 | #address-cells = <1>; | |
| 553 | #size-cells = <0>; | |
| 554 | clocks = <&tegra_car TEGRA124_CLK_SBC6>; | |
| 555 | clock-names = "spi"; | |
| 556 | resets = <&tegra_car 105>; | |
| 557 | reset-names = "spi"; | |
| 558 | dmas = <&apbdma 28>, <&apbdma 28>; | |
| 559 | dma-names = "rx", "tx"; | |
| 560 | status = "disabled"; | |
| 561 | }; | |
| 562 | ||
| e30cb238 | 563 | rtc@0,7000e000 { |
| ad03b1a7 | 564 | compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; |
| e30cb238 | 565 | reg = <0x0 0x7000e000 0x0 0x100>; |
| ad03b1a7 | 566 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| 3b86baf2 | 567 | clocks = <&tegra_car TEGRA124_CLK_RTC>; |
| ad03b1a7 JL |
568 | }; |
| 569 | ||
| e30cb238 | 570 | pmc@0,7000e400 { |
| ad03b1a7 | 571 | compatible = "nvidia,tegra124-pmc"; |
| e30cb238 | 572 | reg = <0x0 0x7000e400 0x0 0x400>; |
| 3b86baf2 JL |
573 | clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; |
| 574 | clock-names = "pclk", "clk32k_in"; | |
| ad03b1a7 JL |
575 | }; |
| 576 | ||
| 155dfc7b PDS |
577 | fuse@0,7000f800 { |
| 578 | compatible = "nvidia,tegra124-efuse"; | |
| 579 | reg = <0x0 0x7000f800 0x0 0x400>; | |
| 580 | clocks = <&tegra_car TEGRA124_CLK_FUSE>; | |
| 581 | clock-names = "fuse"; | |
| 582 | resets = <&tegra_car 39>; | |
| 583 | reset-names = "fuse"; | |
| 584 | }; | |
| 585 | ||
| b26ea06b TR |
586 | mc: memory-controller@0,70019000 { |
| 587 | compatible = "nvidia,tegra124-mc"; | |
| 588 | reg = <0x0 0x70019000 0x0 0x1000>; | |
| 589 | clocks = <&tegra_car TEGRA124_CLK_MC>; | |
| 590 | clock-names = "mc"; | |
| 591 | ||
| 592 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
| 593 | ||
| 594 | #iommu-cells = <1>; | |
| 595 | }; | |
| 596 | ||
| b273c887 MP |
597 | emc: emc@0,7001b000 { |
| 598 | compatible = "nvidia,tegra124-emc"; | |
| 599 | reg = <0x0 0x7001b000 0x0 0x1000>; | |
| 600 | ||
| 601 | nvidia,memory-controller = <&mc>; | |
| 602 | }; | |
| 603 | ||
| fdd69096 MP |
604 | sata@0,70020000 { |
| 605 | compatible = "nvidia,tegra124-ahci"; | |
| 606 | ||
| 607 | reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ | |
| 608 | <0x0 0x70020000 0x0 0x7000>; /* SATA */ | |
| 609 | ||
| 610 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
| 611 | ||
| 612 | clocks = <&tegra_car TEGRA124_CLK_SATA>, | |
| 613 | <&tegra_car TEGRA124_CLK_SATA_OOB>, | |
| 614 | <&tegra_car TEGRA124_CLK_CML1>, | |
| 615 | <&tegra_car TEGRA124_CLK_PLL_E>; | |
| 616 | clock-names = "sata", "sata-oob", "cml1", "pll_e"; | |
| 617 | ||
| 618 | resets = <&tegra_car 124>, | |
| 619 | <&tegra_car 123>, | |
| 620 | <&tegra_car 129>; | |
| 621 | reset-names = "sata", "sata-oob", "sata-cold"; | |
| 622 | ||
| 623 | phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; | |
| 624 | phy-names = "sata-phy"; | |
| 625 | ||
| 626 | status = "disabled"; | |
| 627 | }; | |
| 628 | ||
| 6389cb3b DR |
629 | hda@0,70030000 { |
| 630 | compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; | |
| 631 | reg = <0x0 0x70030000 0x0 0x10000>; | |
| 632 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
| 633 | clocks = <&tegra_car TEGRA124_CLK_HDA>, | |
| 634 | <&tegra_car TEGRA124_CLK_HDA2HDMI>, | |
| 635 | <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; | |
| 636 | clock-names = "hda", "hda2hdmi", "hdacodec_2x"; | |
| 637 | resets = <&tegra_car 125>, /* hda */ | |
| 638 | <&tegra_car 128>, /* hda2hdmi */ | |
| 639 | <&tegra_car 111>; /* hda2codec_2x */ | |
| 640 | reset-names = "hda", "hda2hdmi", "hdacodec_2x"; | |
| 641 | status = "disabled"; | |
| 642 | }; | |
| 643 | ||
| ce90d32d TR |
644 | padctl: padctl@0,7009f000 { |
| 645 | compatible = "nvidia,tegra124-xusb-padctl"; | |
| 646 | reg = <0x0 0x7009f000 0x0 0x1000>; | |
| 647 | resets = <&tegra_car 142>; | |
| 648 | reset-names = "padctl"; | |
| 649 | ||
| 650 | #phy-cells = <1>; | |
| 651 | }; | |
| 652 | ||
| e30cb238 | 653 | sdhci@0,700b0000 { |
| 784c7444 | 654 | compatible = "nvidia,tegra124-sdhci"; |
| e30cb238 | 655 | reg = <0x0 0x700b0000 0x0 0x200>; |
| 784c7444 SW |
656 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 657 | clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; | |
| 658 | resets = <&tegra_car 14>; | |
| 659 | reset-names = "sdhci"; | |
| e2b6d77e | 660 | status = "disabled"; |
| 784c7444 SW |
661 | }; |
| 662 | ||
| e30cb238 | 663 | sdhci@0,700b0200 { |
| 784c7444 | 664 | compatible = "nvidia,tegra124-sdhci"; |
| e30cb238 | 665 | reg = <0x0 0x700b0200 0x0 0x200>; |
| 784c7444 SW |
666 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 667 | clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; | |
| 668 | resets = <&tegra_car 9>; | |
| 669 | reset-names = "sdhci"; | |
| e2b6d77e | 670 | status = "disabled"; |
| 784c7444 SW |
671 | }; |
| 672 | ||
| e30cb238 | 673 | sdhci@0,700b0400 { |
| 784c7444 | 674 | compatible = "nvidia,tegra124-sdhci"; |
| e30cb238 | 675 | reg = <0x0 0x700b0400 0x0 0x200>; |
| 784c7444 SW |
676 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| 677 | clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; | |
| 678 | resets = <&tegra_car 69>; | |
| 679 | reset-names = "sdhci"; | |
| e2b6d77e | 680 | status = "disabled"; |
| 784c7444 SW |
681 | }; |
| 682 | ||
| e30cb238 | 683 | sdhci@0,700b0600 { |
| 784c7444 | 684 | compatible = "nvidia,tegra124-sdhci"; |
| e30cb238 | 685 | reg = <0x0 0x700b0600 0x0 0x200>; |
| 784c7444 SW |
686 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| 687 | clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; | |
| 688 | resets = <&tegra_car 15>; | |
| 689 | reset-names = "sdhci"; | |
| e2b6d77e | 690 | status = "disabled"; |
| 784c7444 SW |
691 | }; |
| 692 | ||
| 26b76f80 MP |
693 | soctherm: thermal-sensor@0,700e2000 { |
| 694 | compatible = "nvidia,tegra124-soctherm"; | |
| 695 | reg = <0x0 0x700e2000 0x0 0x1000>; | |
| 696 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; | |
| 697 | clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, | |
| 698 | <&tegra_car TEGRA124_CLK_SOC_THERM>; | |
| 699 | clock-names = "tsensor", "soctherm"; | |
| 700 | resets = <&tegra_car 78>; | |
| 701 | reset-names = "soctherm"; | |
| 702 | #thermal-sensor-cells = <1>; | |
| 703 | }; | |
| 704 | ||
| e30cb238 | 705 | ahub@0,70300000 { |
| e6655578 | 706 | compatible = "nvidia,tegra124-ahub"; |
| e30cb238 SW |
707 | reg = <0x0 0x70300000 0x0 0x200>, |
| 708 | <0x0 0x70300800 0x0 0x800>, | |
| 709 | <0x0 0x70300200 0x0 0x600>; | |
| e6655578 SW |
710 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| 711 | clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, | |
| 712 | <&tegra_car TEGRA124_CLK_APBIF>; | |
| 713 | clock-names = "d_audio", "apbif"; | |
| 714 | resets = <&tegra_car 106>, /* d_audio */ | |
| 715 | <&tegra_car 107>, /* apbif */ | |
| 716 | <&tegra_car 30>, /* i2s0 */ | |
| 717 | <&tegra_car 11>, /* i2s1 */ | |
| 718 | <&tegra_car 18>, /* i2s2 */ | |
| 719 | <&tegra_car 101>, /* i2s3 */ | |
| 720 | <&tegra_car 102>, /* i2s4 */ | |
| 721 | <&tegra_car 108>, /* dam0 */ | |
| 722 | <&tegra_car 109>, /* dam1 */ | |
| 723 | <&tegra_car 110>, /* dam2 */ | |
| 724 | <&tegra_car 10>, /* spdif */ | |
| 725 | <&tegra_car 153>, /* amx */ | |
| 726 | <&tegra_car 185>, /* amx1 */ | |
| 727 | <&tegra_car 154>, /* adx */ | |
| 728 | <&tegra_car 180>, /* adx1 */ | |
| 729 | <&tegra_car 186>, /* afc0 */ | |
| 730 | <&tegra_car 187>, /* afc1 */ | |
| 731 | <&tegra_car 188>, /* afc2 */ | |
| 732 | <&tegra_car 189>, /* afc3 */ | |
| 733 | <&tegra_car 190>, /* afc4 */ | |
| 734 | <&tegra_car 191>; /* afc5 */ | |
| 735 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", | |
| 736 | "i2s3", "i2s4", "dam0", "dam1", "dam2", | |
| 737 | "spdif", "amx", "amx1", "adx", "adx1", | |
| 738 | "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; | |
| 739 | dmas = <&apbdma 1>, <&apbdma 1>, | |
| 740 | <&apbdma 2>, <&apbdma 2>, | |
| 741 | <&apbdma 3>, <&apbdma 3>, | |
| 742 | <&apbdma 4>, <&apbdma 4>, | |
| 743 | <&apbdma 6>, <&apbdma 6>, | |
| 744 | <&apbdma 7>, <&apbdma 7>, | |
| 745 | <&apbdma 12>, <&apbdma 12>, | |
| 746 | <&apbdma 13>, <&apbdma 13>, | |
| 747 | <&apbdma 14>, <&apbdma 14>, | |
| 748 | <&apbdma 29>, <&apbdma 29>; | |
| 749 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", | |
| 750 | "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", | |
| 751 | "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", | |
| 752 | "rx9", "tx9"; | |
| 753 | ranges; | |
| e30cb238 SW |
754 | #address-cells = <2>; |
| 755 | #size-cells = <2>; | |
| e6655578 | 756 | |
| e30cb238 | 757 | tegra_i2s0: i2s@0,70301000 { |
| e6655578 | 758 | compatible = "nvidia,tegra124-i2s"; |
| e30cb238 | 759 | reg = <0x0 0x70301000 0x0 0x100>; |
| e6655578 SW |
760 | nvidia,ahub-cif-ids = <4 4>; |
| 761 | clocks = <&tegra_car TEGRA124_CLK_I2S0>; | |
| 762 | resets = <&tegra_car 30>; | |
| 763 | reset-names = "i2s"; | |
| 764 | status = "disabled"; | |
| 765 | }; | |
| 766 | ||
| e30cb238 | 767 | tegra_i2s1: i2s@0,70301100 { |
| e6655578 | 768 | compatible = "nvidia,tegra124-i2s"; |
| e30cb238 | 769 | reg = <0x0 0x70301100 0x0 0x100>; |
| e6655578 SW |
770 | nvidia,ahub-cif-ids = <5 5>; |
| 771 | clocks = <&tegra_car TEGRA124_CLK_I2S1>; | |
| 772 | resets = <&tegra_car 11>; | |
| 773 | reset-names = "i2s"; | |
| 774 | status = "disabled"; | |
| 775 | }; | |
| 776 | ||
| e30cb238 | 777 | tegra_i2s2: i2s@0,70301200 { |
| e6655578 | 778 | compatible = "nvidia,tegra124-i2s"; |
| e30cb238 | 779 | reg = <0x0 0x70301200 0x0 0x100>; |
| e6655578 SW |
780 | nvidia,ahub-cif-ids = <6 6>; |
| 781 | clocks = <&tegra_car TEGRA124_CLK_I2S2>; | |
| 782 | resets = <&tegra_car 18>; | |
| 783 | reset-names = "i2s"; | |
| 784 | status = "disabled"; | |
| 785 | }; | |
| 786 | ||
| e30cb238 | 787 | tegra_i2s3: i2s@0,70301300 { |
| e6655578 | 788 | compatible = "nvidia,tegra124-i2s"; |
| e30cb238 | 789 | reg = <0x0 0x70301300 0x0 0x100>; |
| e6655578 SW |
790 | nvidia,ahub-cif-ids = <7 7>; |
| 791 | clocks = <&tegra_car TEGRA124_CLK_I2S3>; | |
| 792 | resets = <&tegra_car 101>; | |
| 793 | reset-names = "i2s"; | |
| 794 | status = "disabled"; | |
| 795 | }; | |
| 796 | ||
| e30cb238 | 797 | tegra_i2s4: i2s@0,70301400 { |
| e6655578 | 798 | compatible = "nvidia,tegra124-i2s"; |
| e30cb238 | 799 | reg = <0x0 0x70301400 0x0 0x100>; |
| e6655578 SW |
800 | nvidia,ahub-cif-ids = <8 8>; |
| 801 | clocks = <&tegra_car TEGRA124_CLK_I2S4>; | |
| 802 | resets = <&tegra_car 102>; | |
| 803 | reset-names = "i2s"; | |
| 804 | status = "disabled"; | |
| 805 | }; | |
| 806 | }; | |
| 807 | ||
| e30cb238 | 808 | usb@0,7d000000 { |
| f2d50158 | 809 | compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
| e30cb238 | 810 | reg = <0x0 0x7d000000 0x0 0x4000>; |
| f2d50158 TR |
811 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 812 | phy_type = "utmi"; | |
| 813 | clocks = <&tegra_car TEGRA124_CLK_USBD>; | |
| 814 | resets = <&tegra_car 22>; | |
| 815 | reset-names = "usb"; | |
| 816 | nvidia,phy = <&phy1>; | |
| 817 | status = "disabled"; | |
| 818 | }; | |
| 819 | ||
| e30cb238 | 820 | phy1: usb-phy@0,7d000000 { |
| f2d50158 | 821 | compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; |
| e30cb238 SW |
822 | reg = <0x0 0x7d000000 0x0 0x4000>, |
| 823 | <0x0 0x7d000000 0x0 0x4000>; | |
| f2d50158 TR |
824 | phy_type = "utmi"; |
| 825 | clocks = <&tegra_car TEGRA124_CLK_USBD>, | |
| 826 | <&tegra_car TEGRA124_CLK_PLL_U>, | |
| 827 | <&tegra_car TEGRA124_CLK_USBD>; | |
| 828 | clock-names = "reg", "pll_u", "utmi-pads"; | |
| 308efde2 TT |
829 | resets = <&tegra_car 59>, <&tegra_car 22>; |
| 830 | reset-names = "usb", "utmi-pads"; | |
| f2d50158 TR |
831 | nvidia,hssync-start-delay = <0>; |
| 832 | nvidia,idle-wait-delay = <17>; | |
| 833 | nvidia,elastic-limit = <16>; | |
| 834 | nvidia,term-range-adj = <6>; | |
| 835 | nvidia,xcvr-setup = <9>; | |
| 836 | nvidia,xcvr-lsfslew = <0>; | |
| 837 | nvidia,xcvr-lsrslew = <3>; | |
| 838 | nvidia,hssquelch-level = <2>; | |
| 839 | nvidia,hsdiscon-level = <5>; | |
| 840 | nvidia,xcvr-hsslew = <12>; | |
| 841 | status = "disabled"; | |
| 842 | }; | |
| 843 | ||
| e30cb238 | 844 | usb@0,7d004000 { |
| f2d50158 | 845 | compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
| e30cb238 | 846 | reg = <0x0 0x7d004000 0x0 0x4000>; |
| f2d50158 TR |
847 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| 848 | phy_type = "utmi"; | |
| 849 | clocks = <&tegra_car TEGRA124_CLK_USB2>; | |
| 850 | resets = <&tegra_car 58>; | |
| 851 | reset-names = "usb"; | |
| 852 | nvidia,phy = <&phy2>; | |
| 853 | status = "disabled"; | |
| 854 | }; | |
| 855 | ||
| e30cb238 | 856 | phy2: usb-phy@0,7d004000 { |
| f2d50158 | 857 | compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; |
| e30cb238 SW |
858 | reg = <0x0 0x7d004000 0x0 0x4000>, |
| 859 | <0x0 0x7d000000 0x0 0x4000>; | |
| f2d50158 TR |
860 | phy_type = "utmi"; |
| 861 | clocks = <&tegra_car TEGRA124_CLK_USB2>, | |
| 862 | <&tegra_car TEGRA124_CLK_PLL_U>, | |
| 863 | <&tegra_car TEGRA124_CLK_USBD>; | |
| 864 | clock-names = "reg", "pll_u", "utmi-pads"; | |
| 308efde2 TT |
865 | resets = <&tegra_car 22>, <&tegra_car 22>; |
| 866 | reset-names = "usb", "utmi-pads"; | |
| f2d50158 TR |
867 | nvidia,hssync-start-delay = <0>; |
| 868 | nvidia,idle-wait-delay = <17>; | |
| 869 | nvidia,elastic-limit = <16>; | |
| 870 | nvidia,term-range-adj = <6>; | |
| 871 | nvidia,xcvr-setup = <9>; | |
| 872 | nvidia,xcvr-lsfslew = <0>; | |
| 873 | nvidia,xcvr-lsrslew = <3>; | |
| 874 | nvidia,hssquelch-level = <2>; | |
| 875 | nvidia,hsdiscon-level = <5>; | |
| 876 | nvidia,xcvr-hsslew = <12>; | |
| 308efde2 | 877 | nvidia,has-utmi-pad-registers; |
| f2d50158 TR |
878 | status = "disabled"; |
| 879 | }; | |
| 880 | ||
| e30cb238 | 881 | usb@0,7d008000 { |
| f2d50158 | 882 | compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
| e30cb238 | 883 | reg = <0x0 0x7d008000 0x0 0x4000>; |
| f2d50158 TR |
884 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 885 | phy_type = "utmi"; | |
| 886 | clocks = <&tegra_car TEGRA124_CLK_USB3>; | |
| 887 | resets = <&tegra_car 59>; | |
| 888 | reset-names = "usb"; | |
| 889 | nvidia,phy = <&phy3>; | |
| 890 | status = "disabled"; | |
| 891 | }; | |
| 892 | ||
| e30cb238 | 893 | phy3: usb-phy@0,7d008000 { |
| f2d50158 | 894 | compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; |
| e30cb238 SW |
895 | reg = <0x0 0x7d008000 0x0 0x4000>, |
| 896 | <0x0 0x7d000000 0x0 0x4000>; | |
| f2d50158 TR |
897 | phy_type = "utmi"; |
| 898 | clocks = <&tegra_car TEGRA124_CLK_USB3>, | |
| 899 | <&tegra_car TEGRA124_CLK_PLL_U>, | |
| 900 | <&tegra_car TEGRA124_CLK_USBD>; | |
| 901 | clock-names = "reg", "pll_u", "utmi-pads"; | |
| 308efde2 TT |
902 | resets = <&tegra_car 58>, <&tegra_car 22>; |
| 903 | reset-names = "usb", "utmi-pads"; | |
| f2d50158 TR |
904 | nvidia,hssync-start-delay = <0>; |
| 905 | nvidia,idle-wait-delay = <17>; | |
| 906 | nvidia,elastic-limit = <16>; | |
| 907 | nvidia,term-range-adj = <6>; | |
| 908 | nvidia,xcvr-setup = <9>; | |
| 909 | nvidia,xcvr-lsfslew = <0>; | |
| 910 | nvidia,xcvr-lsrslew = <3>; | |
| 911 | nvidia,hssquelch-level = <2>; | |
| 912 | nvidia,hsdiscon-level = <5>; | |
| 913 | nvidia,xcvr-hsslew = <12>; | |
| 914 | status = "disabled"; | |
| 915 | }; | |
| 916 | ||
| ad03b1a7 JL |
917 | cpus { |
| 918 | #address-cells = <1>; | |
| 919 | #size-cells = <0>; | |
| 920 | ||
| 921 | cpu@0 { | |
| 922 | device_type = "cpu"; | |
| 923 | compatible = "arm,cortex-a15"; | |
| 924 | reg = <0>; | |
| 925 | }; | |
| 926 | ||
| 927 | cpu@1 { | |
| 928 | device_type = "cpu"; | |
| 929 | compatible = "arm,cortex-a15"; | |
| 930 | reg = <1>; | |
| 931 | }; | |
| 932 | ||
| 933 | cpu@2 { | |
| 934 | device_type = "cpu"; | |
| 935 | compatible = "arm,cortex-a15"; | |
| 936 | reg = <2>; | |
| 937 | }; | |
| 938 | ||
| 939 | cpu@3 { | |
| 940 | device_type = "cpu"; | |
| 941 | compatible = "arm,cortex-a15"; | |
| 942 | reg = <3>; | |
| 943 | }; | |
| 944 | }; | |
| 945 | ||
| 26b76f80 MP |
946 | thermal-zones { |
| 947 | cpu { | |
| 948 | polling-delay-passive = <1000>; | |
| 949 | polling-delay = <1000>; | |
| 950 | ||
| 951 | thermal-sensors = | |
| 952 | <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; | |
| 953 | }; | |
| 954 | ||
| 955 | mem { | |
| 956 | polling-delay-passive = <1000>; | |
| 957 | polling-delay = <1000>; | |
| 958 | ||
| 959 | thermal-sensors = | |
| 960 | <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; | |
| 961 | }; | |
| 962 | ||
| 963 | gpu { | |
| 964 | polling-delay-passive = <1000>; | |
| 965 | polling-delay = <1000>; | |
| 966 | ||
| 967 | thermal-sensors = | |
| 968 | <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; | |
| 969 | }; | |
| 970 | ||
| 971 | pllx { | |
| 972 | polling-delay-passive = <1000>; | |
| 973 | polling-delay = <1000>; | |
| 974 | ||
| 975 | thermal-sensors = | |
| 976 | <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; | |
| 977 | }; | |
| 978 | }; | |
| 979 | ||
| ad03b1a7 JL |
980 | timer { |
| 981 | compatible = "arm,armv7-timer"; | |
| 982 | interrupts = <GIC_PPI 13 | |
| 983 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 984 | <GIC_PPI 14 | |
| 985 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 986 | <GIC_PPI 11 | |
| 987 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 988 | <GIC_PPI 10 | |
| 989 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
| 870c81a4 | 990 | interrupt-parent = <&gic>; |
| ad03b1a7 JL |
991 | }; |
| 992 | }; |