[deliverable/linux.git] / arch / arm / boot / dts / tegra124.dtsi

#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra124";
	interrupt-parent = <&gic>;

	gic: interrupt-controller@50041000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x50041000 0x1000>,
		      <0x50042000 0x1000>,
		      <0x50044000 0x2000>,
		      <0x50046000 0x2000>;
		interrupts = <GIC_PPI 9
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
		reg = <0x60005000 0x400>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_TIMER>;
	};

	tegra_car: clock@60006000 {
		compatible = "nvidia,tegra124-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gpio: gpio@6000d000 {
		compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performace. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
	 * the APB DMA based serial driver, the comptible is
	 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
	 */
	serial@70006000 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_UARTA>;
		resets = <&tegra_car 6>;
		reset-names = "serial";
		status = "disabled";
	};

	serial@70006040 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_UARTB>;
		resets = <&tegra_car 7>;
		reset-names = "serial";
		status = "disabled";
	};

	serial@70006200 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x70006200 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_UARTC>;
		resets = <&tegra_car 55>;
		reset-names = "serial";
		status = "disabled";
	};

	serial@70006300 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x70006300 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_UARTD>;
		resets = <&tegra_car 65>;
		reset-names = "serial";
		status = "disabled";
	};

	serial@70006400 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x70006400 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_UARTE>;
		resets = <&tegra_car 66>;
		reset-names = "serial";
		status = "disabled";
	};

	rtc@7000e000 {
		compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_RTC>;
	};

	pmc@7000e400 {
		compatible = "nvidia,tegra124-pmc";
		reg = <0x7000e400 0x400>;
		clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <3>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};
};
Commit	Line	Data
3b86baf2	1	#include <dt-bindings/clock/tegra124-car.h>
0a9375d1	2	#include <dt-bindings/gpio/tegra-gpio.h>
ad03b1a7 JL	3	#include <dt-bindings/interrupt-controller/arm-gic.h>
	4
	5	#include "skeleton.dtsi"
	6
	7	/ {
	8	compatible = "nvidia,tegra124";
	9	interrupt-parent = <&gic>;
	10
	11	gic: interrupt-controller@50041000 {
	12	compatible = "arm,cortex-a15-gic";
	13	#interrupt-cells = <3>;
	14	interrupt-controller;
	15	reg = <0x50041000 0x1000>,
	16	<0x50042000 0x1000>,
	17	<0x50044000 0x2000>,
	18	<0x50046000 0x2000>;
	19	interrupts = <GIC_PPI 9
	20	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	21	};
	22
	23	timer@60005000 {
	24	compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
	25	reg = <0x60005000 0x400>;
	26	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	27	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	28	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	29	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	30	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	31	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
3b86baf2 JL	32	clocks = <&tegra_car TEGRA124_CLK_TIMER>;
	33	};
	34
	35	tegra_car: clock@60006000 {
	36	compatible = "nvidia,tegra124-car";
	37	reg = <0x60006000 0x1000>;
	38	#clock-cells = <1>;
f71e4f03	39	#reset-cells = <1>;
ad03b1a7 JL	40	};
ad03b1a7 JL	41
0a9375d1 SW	42	gpio: gpio@6000d000 {
	43	compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
	44	reg = <0x6000d000 0x1000>;
	45	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	46	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	47	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	48	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	49	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	50	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	51	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
	52	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
	53	#gpio-cells = <2>;
	54	gpio-controller;
	55	#interrupt-cells = <2>;
	56	interrupt-controller;
	57	};
	58
ad03b1a7 JL	59	/*
	60	* There are two serial driver i.e. 8250 based simple serial
	61	* driver and APB DMA based serial driver for higher baudrate
	62	* and performace. To enable the 8250 based driver, the compatible
	63	* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
	64	* the APB DMA based serial driver, the comptible is
	65	* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
	66	*/
	67	serial@70006000 {
	68	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	69	reg = <0x70006000 0x40>;
	70	reg-shift = <2>;
	71	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3b86baf2	72	clocks = <&tegra_car TEGRA124_CLK_UARTA>;
f71e4f03 SW	73	resets = <&tegra_car 6>;
f71e4f03 SW	74	reset-names = "serial";
ad03b1a7 JL	75	status = "disabled";
	76	};
	77
	78	serial@70006040 {
	79	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	80	reg = <0x70006040 0x40>;
	81	reg-shift = <2>;
	82	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3b86baf2	83	clocks = <&tegra_car TEGRA124_CLK_UARTB>;
f71e4f03 SW	84	resets = <&tegra_car 7>;
f71e4f03 SW	85	reset-names = "serial";
ad03b1a7 JL	86	status = "disabled";
	87	};
	88
	89	serial@70006200 {
	90	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	91	reg = <0x70006200 0x40>;
	92	reg-shift = <2>;
	93	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
3b86baf2	94	clocks = <&tegra_car TEGRA124_CLK_UARTC>;
f71e4f03 SW	95	resets = <&tegra_car 55>;
f71e4f03 SW	96	reset-names = "serial";
ad03b1a7 JL	97	status = "disabled";
	98	};
	99
	100	serial@70006300 {
	101	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	102	reg = <0x70006300 0x40>;
	103	reg-shift = <2>;
	104	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
3b86baf2	105	clocks = <&tegra_car TEGRA124_CLK_UARTD>;
f71e4f03 SW	106	resets = <&tegra_car 65>;
f71e4f03 SW	107	reset-names = "serial";
ad03b1a7 JL	108	status = "disabled";
	109	};
	110
	111	serial@70006400 {
	112	compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
	113	reg = <0x70006400 0x40>;
	114	reg-shift = <2>;
	115	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
3b86baf2	116	clocks = <&tegra_car TEGRA124_CLK_UARTE>;
f71e4f03 SW	117	resets = <&tegra_car 66>;
f71e4f03 SW	118	reset-names = "serial";
ad03b1a7 JL	119	status = "disabled";
	120	};
	121
	122	rtc@7000e000 {
	123	compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
	124	reg = <0x7000e000 0x100>;
	125	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
3b86baf2	126	clocks = <&tegra_car TEGRA124_CLK_RTC>;
ad03b1a7 JL	127	};
	128
	129	pmc@7000e400 {
	130	compatible = "nvidia,tegra124-pmc";
	131	reg = <0x7000e400 0x400>;
3b86baf2 JL	132	clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
3b86baf2 JL	133	clock-names = "pclk", "clk32k_in";
ad03b1a7 JL	134	};
	135
	136	cpus {
	137	#address-cells = <1>;
	138	#size-cells = <0>;
	139
	140	cpu@0 {
	141	device_type = "cpu";
	142	compatible = "arm,cortex-a15";
	143	reg = <0>;
	144	};
	145
	146	cpu@1 {
	147	device_type = "cpu";
	148	compatible = "arm,cortex-a15";
	149	reg = <1>;
	150	};
	151
	152	cpu@2 {
	153	device_type = "cpu";
	154	compatible = "arm,cortex-a15";
	155	reg = <2>;
	156	};
	157
	158	cpu@3 {
	159	device_type = "cpu";
	160	compatible = "arm,cortex-a15";
	161	reg = <3>;
	162	};
	163	};
	164
	165	timer {
	166	compatible = "arm,armv7-timer";
	167	interrupts = <GIC_PPI 13
	168	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	169	<GIC_PPI 14
	170	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	171	<GIC_PPI 11
	172	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	173	<GIC_PPI 10
	174	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	175	};
	176	};