Commit | Line | Data |
---|---|---|
731fb450 TR |
1 | /dts-v1/; |
2 | ||
1bd0bd49 | 3 | #include "tegra20-tamonten.dtsi" |
731fb450 TR |
4 | |
5 | / { | |
6 | model = "Avionic Design Medcom-Wide board"; | |
7 | compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; | |
8 | ||
c4574aa0 OJ |
9 | aliases { |
10 | serial0 = &uartd; | |
11 | }; | |
12 | ||
58ecb23f | 13 | pwm@7000a000 { |
b69cd984 AC |
14 | status = "okay"; |
15 | }; | |
16 | ||
f6826156 AB |
17 | host1x@50000000 { |
18 | dc@54200000 { | |
19 | rgb { | |
20 | status = "okay"; | |
21 | nvidia,panel = <&panel>; | |
22 | }; | |
23 | }; | |
24 | }; | |
25 | ||
731fb450 TR |
26 | i2c@7000c000 { |
27 | wm8903: wm8903@1a { | |
28 | compatible = "wlf,wm8903"; | |
29 | reg = <0x1a>; | |
30 | interrupt-parent = <&gpio>; | |
6cecf916 | 31 | interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; |
731fb450 TR |
32 | |
33 | gpio-controller; | |
34 | #gpio-cells = <2>; | |
35 | ||
36 | micdet-cfg = <0>; | |
37 | micdet-delay = <100>; | |
38 | gpio-cfg = <0xffffffff | |
39 | 0xffffffff | |
40 | 0 | |
41 | 0xffffffff | |
42 | 0xffffffff>; | |
43 | }; | |
44 | }; | |
45 | ||
f6826156 | 46 | backlight: backlight { |
731fb450 TR |
47 | compatible = "pwm-backlight"; |
48 | pwms = <&pwm 0 5000000>; | |
49 | ||
50 | brightness-levels = <0 4 8 16 32 64 128 255>; | |
51 | default-brightness-level = <6>; | |
52 | }; | |
53 | ||
f6826156 AB |
54 | panel: panel { |
55 | compatible = "innolux,n156bge-l21", "simple-panel"; | |
56 | ||
57 | power-supply = <&vdd_1v8_reg>, <&vdd_3v3_reg>; | |
58 | enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; | |
59 | ||
60 | backlight = <&backlight>; | |
61 | }; | |
62 | ||
731fb450 TR |
63 | sound { |
64 | compatible = "ad,tegra-audio-wm8903-medcom-wide", | |
65 | "nvidia,tegra-audio-wm8903"; | |
66 | nvidia,model = "Avionic Design Medcom-Wide"; | |
67 | ||
68 | nvidia,audio-routing = | |
69 | "Headphone Jack", "HPOUTR", | |
70 | "Headphone Jack", "HPOUTL", | |
71 | "Int Spk", "ROP", | |
72 | "Int Spk", "RON", | |
73 | "Int Spk", "LOP", | |
74 | "Int Spk", "LON", | |
75 | "Mic Jack", "MICBIAS", | |
76 | "IN1L", "Mic Jack"; | |
77 | ||
78 | nvidia,i2s-controller = <&tegra_i2s1>; | |
79 | nvidia,audio-codec = <&wm8903>; | |
80 | ||
3325f1bc SW |
81 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
82 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; | |
f9cd2b3b | 83 | |
885a8cfa HD |
84 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
85 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | |
86 | <&tegra_car TEGRA20_CLK_CDEV1>; | |
f9cd2b3b | 87 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
731fb450 | 88 | }; |
23e63345 AB |
89 | |
90 | regulators { | |
91 | vcc_24v_reg: regulator@100 { | |
92 | compatible = "regulator-fixed"; | |
93 | reg = <100>; | |
94 | regulator-name = "vcc_24v"; | |
95 | regulator-min-microvolt = <24000000>; | |
96 | regulator-max-microvolt = <24000000>; | |
97 | regulator-always-on; | |
98 | }; | |
99 | ||
100 | vdd_5v0_reg: regulator@101 { | |
101 | compatible = "regulator-fixed"; | |
102 | reg = <101>; | |
103 | regulator-name = "vdd_5v0"; | |
104 | vin-supply = <&vcc_24v_reg>; | |
105 | regulator-min-microvolt = <5000000>; | |
106 | regulator-max-microvolt = <5000000>; | |
107 | regulator-always-on; | |
108 | }; | |
109 | ||
110 | vdd_3v3_reg: regulator@102 { | |
111 | compatible = "regulator-fixed"; | |
112 | reg = <102>; | |
113 | regulator-name = "vdd_3v3"; | |
114 | vin-supply = <&vcc_24v_reg>; | |
115 | regulator-min-microvolt = <3300000>; | |
116 | regulator-max-microvolt = <3300000>; | |
117 | regulator-always-on; | |
118 | }; | |
119 | ||
120 | vdd_1v8_reg: regulator@103 { | |
121 | compatible = "regulator-fixed"; | |
122 | reg = <103>; | |
123 | regulator-name = "vdd_1v8"; | |
124 | vin-supply = <&vdd_3v3_reg>; | |
125 | regulator-min-microvolt = <1800000>; | |
126 | regulator-max-microvolt = <1800000>; | |
127 | regulator-always-on; | |
128 | }; | |
129 | }; | |
731fb450 | 130 | }; |