Commit | Line | Data |
---|---|---|
cc2afa43 MD |
1 | /dts-v1/; |
2 | ||
6bccbd5e | 3 | #include <dt-bindings/input/input.h> |
1bd0bd49 | 4 | #include "tegra20.dtsi" |
cc2afa43 MD |
5 | |
6 | / { | |
7 | model = "Toshiba AC100 / Dynabook AZ"; | |
8 | compatible = "compal,paz00", "nvidia,tegra20"; | |
9 | ||
553c0a20 SW |
10 | aliases { |
11 | rtc0 = "/i2c@7000d000/tps6586x@34"; | |
12 | rtc1 = "/rtc@7000e000"; | |
c4574aa0 OJ |
13 | serial0 = &uarta; |
14 | serial1 = &uartc; | |
553c0a20 SW |
15 | }; |
16 | ||
f5bbb327 JH |
17 | chosen { |
18 | stdout-path = "serial0:115200n8"; | |
19 | }; | |
20 | ||
f9eb26a4 | 21 | memory { |
cc2afa43 MD |
22 | reg = <0x00000000 0x20000000>; |
23 | }; | |
24 | ||
58ecb23f | 25 | host1x@50000000 { |
5816898b MD |
26 | dc@54200000 { |
27 | rgb { | |
28 | status = "okay"; | |
29 | ||
30 | nvidia,panel = <&panel>; | |
31 | }; | |
32 | }; | |
33 | ||
58ecb23f | 34 | hdmi@54280000 { |
11a3c868 SW |
35 | status = "okay"; |
36 | ||
37 | vdd-supply = <&hdmi_vdd_reg>; | |
38 | pll-supply = <&hdmi_pll_reg>; | |
39 | ||
40 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
3325f1bc SW |
41 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
42 | GPIO_ACTIVE_HIGH>; | |
11a3c868 SW |
43 | }; |
44 | }; | |
45 | ||
58ecb23f | 46 | pinmux@70000014 { |
ecc295bb SW |
47 | pinctrl-names = "default"; |
48 | pinctrl-0 = <&state_default>; | |
49 | ||
50 | state_default: pinmux { | |
51 | ata { | |
52 | nvidia,pins = "ata", "atc", "atd", "ate", | |
53 | "dap2", "gmb", "gmc", "gmd", "spia", | |
54 | "spib", "spic", "spid", "spie"; | |
55 | nvidia,function = "gmi"; | |
56 | }; | |
57 | atb { | |
58 | nvidia,pins = "atb", "gma", "gme"; | |
59 | nvidia,function = "sdio4"; | |
60 | }; | |
61 | cdev1 { | |
62 | nvidia,pins = "cdev1"; | |
63 | nvidia,function = "plla_out"; | |
64 | }; | |
65 | cdev2 { | |
66 | nvidia,pins = "cdev2"; | |
67 | nvidia,function = "pllp_out4"; | |
68 | }; | |
69 | crtp { | |
70 | nvidia,pins = "crtp"; | |
71 | nvidia,function = "crt"; | |
72 | }; | |
73 | csus { | |
74 | nvidia,pins = "csus"; | |
75 | nvidia,function = "pllc_out1"; | |
76 | }; | |
77 | dap1 { | |
78 | nvidia,pins = "dap1"; | |
79 | nvidia,function = "dap1"; | |
80 | }; | |
81 | dap3 { | |
82 | nvidia,pins = "dap3"; | |
83 | nvidia,function = "dap3"; | |
84 | }; | |
85 | dap4 { | |
86 | nvidia,pins = "dap4"; | |
87 | nvidia,function = "dap4"; | |
88 | }; | |
89 | ddc { | |
90 | nvidia,pins = "ddc"; | |
91 | nvidia,function = "i2c2"; | |
92 | }; | |
93 | dta { | |
94 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; | |
95 | nvidia,function = "rsvd1"; | |
96 | }; | |
97 | dtf { | |
98 | nvidia,pins = "dtf"; | |
99 | nvidia,function = "i2c3"; | |
100 | }; | |
101 | gpu { | |
102 | nvidia,pins = "gpu", "sdb", "sdd"; | |
103 | nvidia,function = "pwm"; | |
104 | }; | |
105 | gpu7 { | |
106 | nvidia,pins = "gpu7"; | |
107 | nvidia,function = "rtck"; | |
108 | }; | |
109 | gpv { | |
110 | nvidia,pins = "gpv", "slxa", "slxk"; | |
111 | nvidia,function = "pcie"; | |
112 | }; | |
113 | hdint { | |
114 | nvidia,pins = "hdint", "pta"; | |
115 | nvidia,function = "hdmi"; | |
116 | }; | |
117 | i2cp { | |
118 | nvidia,pins = "i2cp"; | |
119 | nvidia,function = "i2cp"; | |
120 | }; | |
121 | irrx { | |
122 | nvidia,pins = "irrx", "irtx"; | |
123 | nvidia,function = "uarta"; | |
124 | }; | |
125 | kbca { | |
126 | nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; | |
127 | nvidia,function = "kbc"; | |
128 | }; | |
129 | kbcb { | |
130 | nvidia,pins = "kbcb", "kbcd"; | |
131 | nvidia,function = "sdio2"; | |
132 | }; | |
133 | lcsn { | |
134 | nvidia,pins = "lcsn", "ld0", "ld1", "ld2", | |
135 | "ld3", "ld4", "ld5", "ld6", "ld7", | |
136 | "ld8", "ld9", "ld10", "ld11", "ld12", | |
137 | "ld13", "ld14", "ld15", "ld16", "ld17", | |
138 | "ldc", "ldi", "lhp0", "lhp1", "lhp2", | |
139 | "lhs", "lm0", "lm1", "lpp", "lpw0", | |
140 | "lpw1", "lpw2", "lsc0", "lsc1", "lsck", | |
141 | "lsda", "lsdi", "lspi", "lvp0", "lvp1", | |
142 | "lvs"; | |
143 | nvidia,function = "displaya"; | |
144 | }; | |
145 | owc { | |
146 | nvidia,pins = "owc"; | |
147 | nvidia,function = "owr"; | |
148 | }; | |
149 | pmc { | |
150 | nvidia,pins = "pmc"; | |
151 | nvidia,function = "pwr_on"; | |
152 | }; | |
153 | rm { | |
154 | nvidia,pins = "rm"; | |
155 | nvidia,function = "i2c1"; | |
156 | }; | |
157 | sdc { | |
158 | nvidia,pins = "sdc"; | |
159 | nvidia,function = "twc"; | |
160 | }; | |
161 | sdio1 { | |
162 | nvidia,pins = "sdio1"; | |
163 | nvidia,function = "sdio1"; | |
164 | }; | |
165 | slxc { | |
166 | nvidia,pins = "slxc", "slxd"; | |
167 | nvidia,function = "spi4"; | |
168 | }; | |
169 | spdi { | |
170 | nvidia,pins = "spdi", "spdo"; | |
171 | nvidia,function = "rsvd2"; | |
172 | }; | |
173 | spif { | |
174 | nvidia,pins = "spif", "uac"; | |
175 | nvidia,function = "rsvd4"; | |
176 | }; | |
177 | spig { | |
178 | nvidia,pins = "spig", "spih"; | |
179 | nvidia,function = "spi2_alt"; | |
180 | }; | |
181 | uaa { | |
182 | nvidia,pins = "uaa", "uab", "uda"; | |
183 | nvidia,function = "ulpi"; | |
184 | }; | |
185 | uad { | |
186 | nvidia,pins = "uad"; | |
187 | nvidia,function = "spdif"; | |
188 | }; | |
189 | uca { | |
190 | nvidia,pins = "uca", "ucb"; | |
191 | nvidia,function = "uartc"; | |
192 | }; | |
193 | conf_ata { | |
194 | nvidia,pins = "ata", "atb", "atc", "atd", "ate", | |
563da21b SW |
195 | "cdev1", "cdev2", "dap1", "dap2", "dtf", |
196 | "gma", "gmb", "gmc", "gmd", "gme", | |
197 | "gpu", "gpu7", "gpv", "i2cp", "pta", | |
198 | "rm", "sdio1", "slxk", "spdo", "uac", | |
199 | "uda"; | |
ba4104e7 LD |
200 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
201 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
ecc295bb | 202 | }; |
ecc295bb SW |
203 | conf_ck32 { |
204 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | |
205 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | |
ba4104e7 | 206 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
ecc295bb SW |
207 | }; |
208 | conf_crtp { | |
209 | nvidia,pins = "crtp", "dap3", "dap4", "dtb", | |
210 | "dtc", "dte", "slxa", "slxc", "slxd", | |
211 | "spdi"; | |
ba4104e7 LD |
212 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
213 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
214 | }; |
215 | conf_csus { | |
216 | nvidia,pins = "csus", "spia", "spib", "spid", | |
217 | "spif"; | |
ba4104e7 LD |
218 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
219 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
220 | }; |
221 | conf_ddc { | |
222 | nvidia,pins = "ddc", "irrx", "irtx", "kbca", | |
223 | "kbcb", "kbcc", "kbcd", "kbce", "kbcf", | |
224 | "spic", "spig", "uaa", "uab"; | |
ba4104e7 LD |
225 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
226 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
ecc295bb SW |
227 | }; |
228 | conf_dta { | |
229 | nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", | |
230 | "spie", "spih", "uad", "uca", "ucb"; | |
ba4104e7 LD |
231 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
232 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
233 | }; |
234 | conf_hdint { | |
235 | nvidia,pins = "hdint", "ld0", "ld1", "ld2", | |
236 | "ld3", "ld4", "ld5", "ld6", "ld7", | |
237 | "ld8", "ld9", "ld10", "ld11", "ld12", | |
238 | "ld13", "ld14", "ld15", "ld16", "ld17", | |
239 | "ldc", "ldi", "lhs", "lsc0", "lspi", | |
240 | "lvs", "pmc"; | |
ba4104e7 | 241 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
ecc295bb SW |
242 | }; |
243 | conf_lc { | |
244 | nvidia,pins = "lc", "ls"; | |
ba4104e7 | 245 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
ecc295bb SW |
246 | }; |
247 | conf_lcsn { | |
248 | nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", | |
249 | "lm0", "lm1", "lpp", "lpw0", "lpw1", | |
250 | "lpw2", "lsc1", "lsck", "lsda", "lsdi", | |
251 | "lvp0", "lvp1", "sdb"; | |
ba4104e7 | 252 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
ecc295bb SW |
253 | }; |
254 | conf_ld17_0 { | |
255 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | |
256 | "ld23_22"; | |
ba4104e7 | 257 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
ecc295bb SW |
258 | }; |
259 | }; | |
260 | }; | |
261 | ||
2a5fdc9a SW |
262 | i2s@70002800 { |
263 | status = "okay"; | |
c04abb3a SW |
264 | }; |
265 | ||
266 | serial@70006000 { | |
2a5fdc9a | 267 | status = "okay"; |
c04abb3a SW |
268 | }; |
269 | ||
c04abb3a | 270 | serial@70006200 { |
2a5fdc9a | 271 | status = "okay"; |
c04abb3a SW |
272 | }; |
273 | ||
5816898b MD |
274 | pwm: pwm@7000a000 { |
275 | status = "okay"; | |
276 | }; | |
277 | ||
278 | lvds_ddc: i2c@7000c000 { | |
2a5fdc9a | 279 | status = "okay"; |
cc2afa43 | 280 | clock-frequency = <400000>; |
613e9657 LR |
281 | |
282 | alc5632: alc5632@1e { | |
283 | compatible = "realtek,alc5632"; | |
284 | reg = <0x1e>; | |
285 | gpio-controller; | |
286 | #gpio-cells = <2>; | |
287 | }; | |
cc2afa43 MD |
288 | }; |
289 | ||
11a3c868 | 290 | hdmi_ddc: i2c@7000c400 { |
2a5fdc9a | 291 | status = "okay"; |
11a3c868 | 292 | clock-frequency = <100000>; |
cc2afa43 MD |
293 | }; |
294 | ||
58ecb23f | 295 | nvec@7000c500 { |
cc2afa43 | 296 | compatible = "nvidia,nvec"; |
ba04c289 | 297 | reg = <0x7000c500 0x100>; |
6cecf916 | 298 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
299 | #address-cells = <1>; |
300 | #size-cells = <0>; | |
cc2afa43 | 301 | clock-frequency = <80000>; |
3325f1bc | 302 | request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; |
cc2afa43 | 303 | slave-addr = <138>; |
885a8cfa | 304 | clocks = <&tegra_car TEGRA20_CLK_I2C3>, |
067cc286 | 305 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; |
d409b3af | 306 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
307 | resets = <&tegra_car 67>; |
308 | reset-names = "i2c"; | |
cc2afa43 MD |
309 | }; |
310 | ||
311 | i2c@7000d000 { | |
2a5fdc9a | 312 | status = "okay"; |
cc2afa43 | 313 | clock-frequency = <400000>; |
1266f897 | 314 | |
217b8f0f SW |
315 | pmic: tps6586x@34 { |
316 | compatible = "ti,tps6586x"; | |
317 | reg = <0x34>; | |
6cecf916 | 318 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
217b8f0f SW |
319 | |
320 | #gpio-cells = <2>; | |
321 | gpio-controller; | |
322 | ||
323 | sys-supply = <&p5valw_reg>; | |
324 | vin-sm0-supply = <&sys_reg>; | |
325 | vin-sm1-supply = <&sys_reg>; | |
326 | vin-sm2-supply = <&sys_reg>; | |
327 | vinldo01-supply = <&sm2_reg>; | |
328 | vinldo23-supply = <&sm2_reg>; | |
329 | vinldo4-supply = <&sm2_reg>; | |
330 | vinldo678-supply = <&sm2_reg>; | |
331 | vinldo9-supply = <&sm2_reg>; | |
332 | ||
333 | regulators { | |
b9c665d7 | 334 | sys_reg: sys { |
217b8f0f SW |
335 | regulator-name = "vdd_sys"; |
336 | regulator-always-on; | |
337 | }; | |
338 | ||
b9c665d7 | 339 | sm0 { |
217b8f0f SW |
340 | regulator-name = "+1.2vs_sm0,vdd_core"; |
341 | regulator-min-microvolt = <1200000>; | |
342 | regulator-max-microvolt = <1200000>; | |
343 | regulator-always-on; | |
344 | }; | |
345 | ||
b9c665d7 | 346 | sm1 { |
217b8f0f SW |
347 | regulator-name = "+1.0vs_sm1,vdd_cpu"; |
348 | regulator-min-microvolt = <1000000>; | |
349 | regulator-max-microvolt = <1000000>; | |
350 | regulator-always-on; | |
351 | }; | |
352 | ||
b9c665d7 | 353 | sm2_reg: sm2 { |
217b8f0f SW |
354 | regulator-name = "+3.7vs_sm2,vin_ldo*"; |
355 | regulator-min-microvolt = <3700000>; | |
356 | regulator-max-microvolt = <3700000>; | |
357 | regulator-always-on; | |
358 | }; | |
359 | ||
360 | /* LDO0 is not connected to anything */ | |
361 | ||
b9c665d7 | 362 | ldo1 { |
217b8f0f SW |
363 | regulator-name = "+1.1vs_ldo1,avdd_pll*"; |
364 | regulator-min-microvolt = <1100000>; | |
365 | regulator-max-microvolt = <1100000>; | |
366 | regulator-always-on; | |
367 | }; | |
368 | ||
b9c665d7 | 369 | ldo2 { |
217b8f0f SW |
370 | regulator-name = "+1.2vs_ldo2,vdd_rtc"; |
371 | regulator-min-microvolt = <1200000>; | |
372 | regulator-max-microvolt = <1200000>; | |
373 | }; | |
374 | ||
b9c665d7 | 375 | ldo3 { |
217b8f0f SW |
376 | regulator-name = "+3.3vs_ldo3,avdd_usb*"; |
377 | regulator-min-microvolt = <3300000>; | |
378 | regulator-max-microvolt = <3300000>; | |
379 | regulator-always-on; | |
380 | }; | |
381 | ||
b9c665d7 | 382 | ldo4 { |
217b8f0f SW |
383 | regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; |
384 | regulator-min-microvolt = <1800000>; | |
385 | regulator-max-microvolt = <1800000>; | |
386 | regulator-always-on; | |
387 | }; | |
388 | ||
b9c665d7 | 389 | ldo5 { |
217b8f0f SW |
390 | regulator-name = "+2.85vs_ldo5,vcore_mmc"; |
391 | regulator-min-microvolt = <2850000>; | |
392 | regulator-max-microvolt = <2850000>; | |
393 | regulator-always-on; | |
394 | }; | |
395 | ||
b9c665d7 | 396 | ldo6 { |
217b8f0f SW |
397 | /* |
398 | * Research indicates this should be | |
399 | * 1.8v; other boards that use this | |
400 | * rail for the same purpose need it | |
401 | * set to 1.8v. The schematic signal | |
402 | * name is incorrect; perhaps copied | |
403 | * from an incorrect NVIDIA reference. | |
404 | */ | |
405 | regulator-name = "+2.85vs_ldo6,avdd_vdac"; | |
406 | regulator-min-microvolt = <1800000>; | |
407 | regulator-max-microvolt = <1800000>; | |
408 | }; | |
409 | ||
11a3c868 | 410 | hdmi_vdd_reg: ldo7 { |
217b8f0f SW |
411 | regulator-name = "+3.3vs_ldo7,avdd_hdmi"; |
412 | regulator-min-microvolt = <3300000>; | |
413 | regulator-max-microvolt = <3300000>; | |
414 | }; | |
415 | ||
11a3c868 | 416 | hdmi_pll_reg: ldo8 { |
217b8f0f SW |
417 | regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; |
418 | regulator-min-microvolt = <1800000>; | |
419 | regulator-max-microvolt = <1800000>; | |
420 | }; | |
421 | ||
b9c665d7 | 422 | ldo9 { |
217b8f0f SW |
423 | regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; |
424 | regulator-min-microvolt = <2850000>; | |
425 | regulator-max-microvolt = <2850000>; | |
426 | regulator-always-on; | |
427 | }; | |
428 | ||
b9c665d7 | 429 | ldo_rtc { |
217b8f0f SW |
430 | regulator-name = "+3.3vs_rtc"; |
431 | regulator-min-microvolt = <3300000>; | |
432 | regulator-max-microvolt = <3300000>; | |
433 | regulator-always-on; | |
434 | }; | |
435 | }; | |
436 | }; | |
437 | ||
1266f897 MD |
438 | adt7461@4c { |
439 | compatible = "adi,adt7461"; | |
440 | reg = <0x4c>; | |
441 | }; | |
cc2afa43 MD |
442 | }; |
443 | ||
58ecb23f | 444 | pmc@7000e400 { |
217b8f0f | 445 | nvidia,invert-interrupt; |
47d2d63b | 446 | nvidia,suspend-mode = <1>; |
a44a019d JL |
447 | nvidia,cpu-pwr-good-time = <2000>; |
448 | nvidia,cpu-pwr-off-time = <0>; | |
449 | nvidia,core-pwr-good-time = <3845 3845>; | |
450 | nvidia,core-pwr-off-time = <0>; | |
451 | nvidia,sys-clock-req-active-high; | |
217b8f0f SW |
452 | }; |
453 | ||
2a5fdc9a SW |
454 | usb@c5000000 { |
455 | status = "okay"; | |
456 | }; | |
457 | ||
4c94c8b5 VB |
458 | usb-phy@c5000000 { |
459 | status = "okay"; | |
460 | }; | |
461 | ||
c04abb3a | 462 | usb@c5004000 { |
2a5fdc9a | 463 | status = "okay"; |
3325f1bc SW |
464 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
465 | GPIO_ACTIVE_LOW>; | |
cc2afa43 MD |
466 | }; |
467 | ||
9dffe3be | 468 | usb-phy@c5004000 { |
4c94c8b5 | 469 | status = "okay"; |
3325f1bc SW |
470 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
471 | GPIO_ACTIVE_LOW>; | |
2a5fdc9a SW |
472 | }; |
473 | ||
9dffe3be VB |
474 | usb@c5008000 { |
475 | status = "okay"; | |
40e8b3a6 VB |
476 | }; |
477 | ||
4c94c8b5 VB |
478 | usb-phy@c5008000 { |
479 | status = "okay"; | |
480 | }; | |
481 | ||
cc2afa43 | 482 | sdhci@c8000000 { |
2a5fdc9a | 483 | status = "okay"; |
3325f1bc SW |
484 | cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; |
485 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; | |
486 | power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; | |
7f217794 | 487 | bus-width = <4>; |
cc2afa43 MD |
488 | }; |
489 | ||
cc2afa43 | 490 | sdhci@c8000600 { |
2a5fdc9a | 491 | status = "okay"; |
7f217794 | 492 | bus-width = <8>; |
7a2617a6 | 493 | non-removable; |
cc2afa43 | 494 | }; |
d8d56c84 | 495 | |
5816898b MD |
496 | backlight: backlight { |
497 | compatible = "pwm-backlight"; | |
498 | ||
499 | enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; | |
500 | pwms = <&pwm 0 5000000>; | |
501 | ||
502 | brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; | |
503 | default-brightness-level = <10>; | |
504 | ||
505 | backlight-boot-off; | |
506 | }; | |
507 | ||
7021d122 JL |
508 | clocks { |
509 | compatible = "simple-bus"; | |
510 | #address-cells = <1>; | |
511 | #size-cells = <0>; | |
512 | ||
58ecb23f | 513 | clk32k_in: clock@0 { |
7021d122 | 514 | compatible = "fixed-clock"; |
4ec2e601 | 515 | reg = <0>; |
7021d122 JL |
516 | #clock-cells = <0>; |
517 | clock-frequency = <32768>; | |
518 | }; | |
519 | }; | |
520 | ||
d8d56c84 MD |
521 | gpio-keys { |
522 | compatible = "gpio-keys"; | |
523 | ||
524 | power { | |
525 | label = "Power"; | |
3325f1bc | 526 | gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; |
6bccbd5e | 527 | linux,code = <KEY_POWER>; |
d1c04d30 | 528 | wakeup-source; |
d8d56c84 MD |
529 | }; |
530 | }; | |
80c9473d MD |
531 | |
532 | gpio-leds { | |
533 | compatible = "gpio-leds"; | |
534 | ||
535 | wifi { | |
536 | label = "wifi-led"; | |
3325f1bc | 537 | gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; |
80c9473d MD |
538 | linux,default-trigger = "rfkill0"; |
539 | }; | |
540 | }; | |
aa607ebf | 541 | |
5816898b MD |
542 | panel: panel { |
543 | compatible = "samsung,ltn101nt05", "simple-panel"; | |
544 | ||
545 | ddc-i2c-bus = <&lvds_ddc>; | |
546 | power-supply = <&vdd_pnl_reg>; | |
547 | enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>; | |
548 | ||
549 | backlight = <&backlight>; | |
550 | }; | |
551 | ||
217b8f0f SW |
552 | regulators { |
553 | compatible = "simple-bus"; | |
554 | #address-cells = <1>; | |
555 | #size-cells = <0>; | |
556 | ||
557 | p5valw_reg: regulator@0 { | |
558 | compatible = "regulator-fixed"; | |
559 | reg = <0>; | |
560 | regulator-name = "+5valw"; | |
561 | regulator-min-microvolt = <5000000>; | |
562 | regulator-max-microvolt = <5000000>; | |
563 | regulator-always-on; | |
564 | }; | |
5816898b MD |
565 | |
566 | vdd_pnl_reg: regulator@1 { | |
567 | compatible = "regulator-fixed"; | |
568 | reg = <1>; | |
569 | regulator-name = "+3VS,vdd_pnl"; | |
570 | regulator-min-microvolt = <3300000>; | |
571 | regulator-max-microvolt = <3300000>; | |
572 | gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; | |
573 | enable-active-high; | |
574 | }; | |
217b8f0f SW |
575 | }; |
576 | ||
c04abb3a SW |
577 | sound { |
578 | compatible = "nvidia,tegra-audio-alc5632-paz00", | |
579 | "nvidia,tegra-audio-alc5632"; | |
580 | ||
581 | nvidia,model = "Compal PAZ00"; | |
582 | ||
583 | nvidia,audio-routing = | |
584 | "Int Spk", "SPKOUT", | |
585 | "Int Spk", "SPKOUTN", | |
586 | "Headset Mic", "MICBIAS1", | |
587 | "MIC1", "Headset Mic", | |
588 | "Headset Stereophone", "HPR", | |
589 | "Headset Stereophone", "HPL", | |
590 | "DMICDAT", "Digital Mic"; | |
591 | ||
592 | nvidia,audio-codec = <&alc5632>; | |
593 | nvidia,i2s-controller = <&tegra_i2s1>; | |
3325f1bc SW |
594 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) |
595 | GPIO_ACTIVE_HIGH>; | |
f9cd2b3b | 596 | |
885a8cfa | 597 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
067cc286 TR |
598 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, |
599 | <&tegra_car TEGRA20_CLK_CDEV1>; | |
f9cd2b3b | 600 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
aa607ebf | 601 | }; |
cc2afa43 | 602 | }; |