Commit | Line | Data |
---|---|---|
cc2afa43 MD |
1 | /dts-v1/; |
2 | ||
6bccbd5e | 3 | #include <dt-bindings/input/input.h> |
1bd0bd49 | 4 | #include "tegra20.dtsi" |
cc2afa43 MD |
5 | |
6 | / { | |
7 | model = "Toshiba AC100 / Dynabook AZ"; | |
8 | compatible = "compal,paz00", "nvidia,tegra20"; | |
9 | ||
553c0a20 SW |
10 | aliases { |
11 | rtc0 = "/i2c@7000d000/tps6586x@34"; | |
12 | rtc1 = "/rtc@7000e000"; | |
13 | }; | |
14 | ||
f9eb26a4 | 15 | memory { |
cc2afa43 MD |
16 | reg = <0x00000000 0x20000000>; |
17 | }; | |
18 | ||
58ecb23f SW |
19 | host1x@50000000 { |
20 | hdmi@54280000 { | |
11a3c868 SW |
21 | status = "okay"; |
22 | ||
23 | vdd-supply = <&hdmi_vdd_reg>; | |
24 | pll-supply = <&hdmi_pll_reg>; | |
25 | ||
26 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
3325f1bc SW |
27 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
28 | GPIO_ACTIVE_HIGH>; | |
11a3c868 SW |
29 | }; |
30 | }; | |
31 | ||
58ecb23f | 32 | pinmux@70000014 { |
ecc295bb SW |
33 | pinctrl-names = "default"; |
34 | pinctrl-0 = <&state_default>; | |
35 | ||
36 | state_default: pinmux { | |
37 | ata { | |
38 | nvidia,pins = "ata", "atc", "atd", "ate", | |
39 | "dap2", "gmb", "gmc", "gmd", "spia", | |
40 | "spib", "spic", "spid", "spie"; | |
41 | nvidia,function = "gmi"; | |
42 | }; | |
43 | atb { | |
44 | nvidia,pins = "atb", "gma", "gme"; | |
45 | nvidia,function = "sdio4"; | |
46 | }; | |
47 | cdev1 { | |
48 | nvidia,pins = "cdev1"; | |
49 | nvidia,function = "plla_out"; | |
50 | }; | |
51 | cdev2 { | |
52 | nvidia,pins = "cdev2"; | |
53 | nvidia,function = "pllp_out4"; | |
54 | }; | |
55 | crtp { | |
56 | nvidia,pins = "crtp"; | |
57 | nvidia,function = "crt"; | |
58 | }; | |
59 | csus { | |
60 | nvidia,pins = "csus"; | |
61 | nvidia,function = "pllc_out1"; | |
62 | }; | |
63 | dap1 { | |
64 | nvidia,pins = "dap1"; | |
65 | nvidia,function = "dap1"; | |
66 | }; | |
67 | dap3 { | |
68 | nvidia,pins = "dap3"; | |
69 | nvidia,function = "dap3"; | |
70 | }; | |
71 | dap4 { | |
72 | nvidia,pins = "dap4"; | |
73 | nvidia,function = "dap4"; | |
74 | }; | |
75 | ddc { | |
76 | nvidia,pins = "ddc"; | |
77 | nvidia,function = "i2c2"; | |
78 | }; | |
79 | dta { | |
80 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; | |
81 | nvidia,function = "rsvd1"; | |
82 | }; | |
83 | dtf { | |
84 | nvidia,pins = "dtf"; | |
85 | nvidia,function = "i2c3"; | |
86 | }; | |
87 | gpu { | |
88 | nvidia,pins = "gpu", "sdb", "sdd"; | |
89 | nvidia,function = "pwm"; | |
90 | }; | |
91 | gpu7 { | |
92 | nvidia,pins = "gpu7"; | |
93 | nvidia,function = "rtck"; | |
94 | }; | |
95 | gpv { | |
96 | nvidia,pins = "gpv", "slxa", "slxk"; | |
97 | nvidia,function = "pcie"; | |
98 | }; | |
99 | hdint { | |
100 | nvidia,pins = "hdint", "pta"; | |
101 | nvidia,function = "hdmi"; | |
102 | }; | |
103 | i2cp { | |
104 | nvidia,pins = "i2cp"; | |
105 | nvidia,function = "i2cp"; | |
106 | }; | |
107 | irrx { | |
108 | nvidia,pins = "irrx", "irtx"; | |
109 | nvidia,function = "uarta"; | |
110 | }; | |
111 | kbca { | |
112 | nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; | |
113 | nvidia,function = "kbc"; | |
114 | }; | |
115 | kbcb { | |
116 | nvidia,pins = "kbcb", "kbcd"; | |
117 | nvidia,function = "sdio2"; | |
118 | }; | |
119 | lcsn { | |
120 | nvidia,pins = "lcsn", "ld0", "ld1", "ld2", | |
121 | "ld3", "ld4", "ld5", "ld6", "ld7", | |
122 | "ld8", "ld9", "ld10", "ld11", "ld12", | |
123 | "ld13", "ld14", "ld15", "ld16", "ld17", | |
124 | "ldc", "ldi", "lhp0", "lhp1", "lhp2", | |
125 | "lhs", "lm0", "lm1", "lpp", "lpw0", | |
126 | "lpw1", "lpw2", "lsc0", "lsc1", "lsck", | |
127 | "lsda", "lsdi", "lspi", "lvp0", "lvp1", | |
128 | "lvs"; | |
129 | nvidia,function = "displaya"; | |
130 | }; | |
131 | owc { | |
132 | nvidia,pins = "owc"; | |
133 | nvidia,function = "owr"; | |
134 | }; | |
135 | pmc { | |
136 | nvidia,pins = "pmc"; | |
137 | nvidia,function = "pwr_on"; | |
138 | }; | |
139 | rm { | |
140 | nvidia,pins = "rm"; | |
141 | nvidia,function = "i2c1"; | |
142 | }; | |
143 | sdc { | |
144 | nvidia,pins = "sdc"; | |
145 | nvidia,function = "twc"; | |
146 | }; | |
147 | sdio1 { | |
148 | nvidia,pins = "sdio1"; | |
149 | nvidia,function = "sdio1"; | |
150 | }; | |
151 | slxc { | |
152 | nvidia,pins = "slxc", "slxd"; | |
153 | nvidia,function = "spi4"; | |
154 | }; | |
155 | spdi { | |
156 | nvidia,pins = "spdi", "spdo"; | |
157 | nvidia,function = "rsvd2"; | |
158 | }; | |
159 | spif { | |
160 | nvidia,pins = "spif", "uac"; | |
161 | nvidia,function = "rsvd4"; | |
162 | }; | |
163 | spig { | |
164 | nvidia,pins = "spig", "spih"; | |
165 | nvidia,function = "spi2_alt"; | |
166 | }; | |
167 | uaa { | |
168 | nvidia,pins = "uaa", "uab", "uda"; | |
169 | nvidia,function = "ulpi"; | |
170 | }; | |
171 | uad { | |
172 | nvidia,pins = "uad"; | |
173 | nvidia,function = "spdif"; | |
174 | }; | |
175 | uca { | |
176 | nvidia,pins = "uca", "ucb"; | |
177 | nvidia,function = "uartc"; | |
178 | }; | |
179 | conf_ata { | |
180 | nvidia,pins = "ata", "atb", "atc", "atd", "ate", | |
563da21b SW |
181 | "cdev1", "cdev2", "dap1", "dap2", "dtf", |
182 | "gma", "gmb", "gmc", "gmd", "gme", | |
183 | "gpu", "gpu7", "gpv", "i2cp", "pta", | |
184 | "rm", "sdio1", "slxk", "spdo", "uac", | |
185 | "uda"; | |
ba4104e7 LD |
186 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
187 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
ecc295bb | 188 | }; |
ecc295bb SW |
189 | conf_ck32 { |
190 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | |
191 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | |
ba4104e7 | 192 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
ecc295bb SW |
193 | }; |
194 | conf_crtp { | |
195 | nvidia,pins = "crtp", "dap3", "dap4", "dtb", | |
196 | "dtc", "dte", "slxa", "slxc", "slxd", | |
197 | "spdi"; | |
ba4104e7 LD |
198 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
199 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
200 | }; |
201 | conf_csus { | |
202 | nvidia,pins = "csus", "spia", "spib", "spid", | |
203 | "spif"; | |
ba4104e7 LD |
204 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
205 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
206 | }; |
207 | conf_ddc { | |
208 | nvidia,pins = "ddc", "irrx", "irtx", "kbca", | |
209 | "kbcb", "kbcc", "kbcd", "kbce", "kbcf", | |
210 | "spic", "spig", "uaa", "uab"; | |
ba4104e7 LD |
211 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
212 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
ecc295bb SW |
213 | }; |
214 | conf_dta { | |
215 | nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", | |
216 | "spie", "spih", "uad", "uca", "ucb"; | |
ba4104e7 LD |
217 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
218 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
219 | }; |
220 | conf_hdint { | |
221 | nvidia,pins = "hdint", "ld0", "ld1", "ld2", | |
222 | "ld3", "ld4", "ld5", "ld6", "ld7", | |
223 | "ld8", "ld9", "ld10", "ld11", "ld12", | |
224 | "ld13", "ld14", "ld15", "ld16", "ld17", | |
225 | "ldc", "ldi", "lhs", "lsc0", "lspi", | |
226 | "lvs", "pmc"; | |
ba4104e7 | 227 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
ecc295bb SW |
228 | }; |
229 | conf_lc { | |
230 | nvidia,pins = "lc", "ls"; | |
ba4104e7 | 231 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
ecc295bb SW |
232 | }; |
233 | conf_lcsn { | |
234 | nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", | |
235 | "lm0", "lm1", "lpp", "lpw0", "lpw1", | |
236 | "lpw2", "lsc1", "lsck", "lsda", "lsdi", | |
237 | "lvp0", "lvp1", "sdb"; | |
ba4104e7 | 238 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
ecc295bb SW |
239 | }; |
240 | conf_ld17_0 { | |
241 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | |
242 | "ld23_22"; | |
ba4104e7 | 243 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
ecc295bb SW |
244 | }; |
245 | }; | |
246 | }; | |
247 | ||
2a5fdc9a SW |
248 | i2s@70002800 { |
249 | status = "okay"; | |
c04abb3a SW |
250 | }; |
251 | ||
252 | serial@70006000 { | |
2a5fdc9a | 253 | status = "okay"; |
c04abb3a SW |
254 | }; |
255 | ||
c04abb3a | 256 | serial@70006200 { |
2a5fdc9a | 257 | status = "okay"; |
c04abb3a SW |
258 | }; |
259 | ||
cc2afa43 | 260 | i2c@7000c000 { |
2a5fdc9a | 261 | status = "okay"; |
cc2afa43 | 262 | clock-frequency = <400000>; |
613e9657 LR |
263 | |
264 | alc5632: alc5632@1e { | |
265 | compatible = "realtek,alc5632"; | |
266 | reg = <0x1e>; | |
267 | gpio-controller; | |
268 | #gpio-cells = <2>; | |
269 | }; | |
cc2afa43 MD |
270 | }; |
271 | ||
11a3c868 | 272 | hdmi_ddc: i2c@7000c400 { |
2a5fdc9a | 273 | status = "okay"; |
11a3c868 | 274 | clock-frequency = <100000>; |
cc2afa43 MD |
275 | }; |
276 | ||
58ecb23f | 277 | nvec@7000c500 { |
cc2afa43 | 278 | compatible = "nvidia,nvec"; |
ba04c289 | 279 | reg = <0x7000c500 0x100>; |
6cecf916 | 280 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
281 | #address-cells = <1>; |
282 | #size-cells = <0>; | |
cc2afa43 | 283 | clock-frequency = <80000>; |
3325f1bc | 284 | request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; |
cc2afa43 | 285 | slave-addr = <138>; |
885a8cfa HD |
286 | clocks = <&tegra_car TEGRA20_CLK_I2C3>, |
287 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
d409b3af | 288 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
289 | resets = <&tegra_car 67>; |
290 | reset-names = "i2c"; | |
cc2afa43 MD |
291 | }; |
292 | ||
293 | i2c@7000d000 { | |
2a5fdc9a | 294 | status = "okay"; |
cc2afa43 | 295 | clock-frequency = <400000>; |
1266f897 | 296 | |
217b8f0f SW |
297 | pmic: tps6586x@34 { |
298 | compatible = "ti,tps6586x"; | |
299 | reg = <0x34>; | |
6cecf916 | 300 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
217b8f0f SW |
301 | |
302 | #gpio-cells = <2>; | |
303 | gpio-controller; | |
304 | ||
305 | sys-supply = <&p5valw_reg>; | |
306 | vin-sm0-supply = <&sys_reg>; | |
307 | vin-sm1-supply = <&sys_reg>; | |
308 | vin-sm2-supply = <&sys_reg>; | |
309 | vinldo01-supply = <&sm2_reg>; | |
310 | vinldo23-supply = <&sm2_reg>; | |
311 | vinldo4-supply = <&sm2_reg>; | |
312 | vinldo678-supply = <&sm2_reg>; | |
313 | vinldo9-supply = <&sm2_reg>; | |
314 | ||
315 | regulators { | |
b9c665d7 | 316 | sys_reg: sys { |
217b8f0f SW |
317 | regulator-name = "vdd_sys"; |
318 | regulator-always-on; | |
319 | }; | |
320 | ||
b9c665d7 | 321 | sm0 { |
217b8f0f SW |
322 | regulator-name = "+1.2vs_sm0,vdd_core"; |
323 | regulator-min-microvolt = <1200000>; | |
324 | regulator-max-microvolt = <1200000>; | |
325 | regulator-always-on; | |
326 | }; | |
327 | ||
b9c665d7 | 328 | sm1 { |
217b8f0f SW |
329 | regulator-name = "+1.0vs_sm1,vdd_cpu"; |
330 | regulator-min-microvolt = <1000000>; | |
331 | regulator-max-microvolt = <1000000>; | |
332 | regulator-always-on; | |
333 | }; | |
334 | ||
b9c665d7 | 335 | sm2_reg: sm2 { |
217b8f0f SW |
336 | regulator-name = "+3.7vs_sm2,vin_ldo*"; |
337 | regulator-min-microvolt = <3700000>; | |
338 | regulator-max-microvolt = <3700000>; | |
339 | regulator-always-on; | |
340 | }; | |
341 | ||
342 | /* LDO0 is not connected to anything */ | |
343 | ||
b9c665d7 | 344 | ldo1 { |
217b8f0f SW |
345 | regulator-name = "+1.1vs_ldo1,avdd_pll*"; |
346 | regulator-min-microvolt = <1100000>; | |
347 | regulator-max-microvolt = <1100000>; | |
348 | regulator-always-on; | |
349 | }; | |
350 | ||
b9c665d7 | 351 | ldo2 { |
217b8f0f SW |
352 | regulator-name = "+1.2vs_ldo2,vdd_rtc"; |
353 | regulator-min-microvolt = <1200000>; | |
354 | regulator-max-microvolt = <1200000>; | |
355 | }; | |
356 | ||
b9c665d7 | 357 | ldo3 { |
217b8f0f SW |
358 | regulator-name = "+3.3vs_ldo3,avdd_usb*"; |
359 | regulator-min-microvolt = <3300000>; | |
360 | regulator-max-microvolt = <3300000>; | |
361 | regulator-always-on; | |
362 | }; | |
363 | ||
b9c665d7 | 364 | ldo4 { |
217b8f0f SW |
365 | regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; |
366 | regulator-min-microvolt = <1800000>; | |
367 | regulator-max-microvolt = <1800000>; | |
368 | regulator-always-on; | |
369 | }; | |
370 | ||
b9c665d7 | 371 | ldo5 { |
217b8f0f SW |
372 | regulator-name = "+2.85vs_ldo5,vcore_mmc"; |
373 | regulator-min-microvolt = <2850000>; | |
374 | regulator-max-microvolt = <2850000>; | |
375 | regulator-always-on; | |
376 | }; | |
377 | ||
b9c665d7 | 378 | ldo6 { |
217b8f0f SW |
379 | /* |
380 | * Research indicates this should be | |
381 | * 1.8v; other boards that use this | |
382 | * rail for the same purpose need it | |
383 | * set to 1.8v. The schematic signal | |
384 | * name is incorrect; perhaps copied | |
385 | * from an incorrect NVIDIA reference. | |
386 | */ | |
387 | regulator-name = "+2.85vs_ldo6,avdd_vdac"; | |
388 | regulator-min-microvolt = <1800000>; | |
389 | regulator-max-microvolt = <1800000>; | |
390 | }; | |
391 | ||
11a3c868 | 392 | hdmi_vdd_reg: ldo7 { |
217b8f0f SW |
393 | regulator-name = "+3.3vs_ldo7,avdd_hdmi"; |
394 | regulator-min-microvolt = <3300000>; | |
395 | regulator-max-microvolt = <3300000>; | |
396 | }; | |
397 | ||
11a3c868 | 398 | hdmi_pll_reg: ldo8 { |
217b8f0f SW |
399 | regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; |
400 | regulator-min-microvolt = <1800000>; | |
401 | regulator-max-microvolt = <1800000>; | |
402 | }; | |
403 | ||
b9c665d7 | 404 | ldo9 { |
217b8f0f SW |
405 | regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; |
406 | regulator-min-microvolt = <2850000>; | |
407 | regulator-max-microvolt = <2850000>; | |
408 | regulator-always-on; | |
409 | }; | |
410 | ||
b9c665d7 | 411 | ldo_rtc { |
217b8f0f SW |
412 | regulator-name = "+3.3vs_rtc"; |
413 | regulator-min-microvolt = <3300000>; | |
414 | regulator-max-microvolt = <3300000>; | |
415 | regulator-always-on; | |
416 | }; | |
417 | }; | |
418 | }; | |
419 | ||
1266f897 MD |
420 | adt7461@4c { |
421 | compatible = "adi,adt7461"; | |
422 | reg = <0x4c>; | |
423 | }; | |
cc2afa43 MD |
424 | }; |
425 | ||
58ecb23f | 426 | pmc@7000e400 { |
217b8f0f | 427 | nvidia,invert-interrupt; |
47d2d63b | 428 | nvidia,suspend-mode = <1>; |
a44a019d JL |
429 | nvidia,cpu-pwr-good-time = <2000>; |
430 | nvidia,cpu-pwr-off-time = <0>; | |
431 | nvidia,core-pwr-good-time = <3845 3845>; | |
432 | nvidia,core-pwr-off-time = <0>; | |
433 | nvidia,sys-clock-req-active-high; | |
217b8f0f SW |
434 | }; |
435 | ||
2a5fdc9a SW |
436 | usb@c5000000 { |
437 | status = "okay"; | |
438 | }; | |
439 | ||
4c94c8b5 VB |
440 | usb-phy@c5000000 { |
441 | status = "okay"; | |
442 | }; | |
443 | ||
c04abb3a | 444 | usb@c5004000 { |
2a5fdc9a | 445 | status = "okay"; |
3325f1bc SW |
446 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
447 | GPIO_ACTIVE_LOW>; | |
cc2afa43 MD |
448 | }; |
449 | ||
9dffe3be | 450 | usb-phy@c5004000 { |
4c94c8b5 | 451 | status = "okay"; |
3325f1bc SW |
452 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
453 | GPIO_ACTIVE_LOW>; | |
2a5fdc9a SW |
454 | }; |
455 | ||
9dffe3be VB |
456 | usb@c5008000 { |
457 | status = "okay"; | |
40e8b3a6 VB |
458 | }; |
459 | ||
4c94c8b5 VB |
460 | usb-phy@c5008000 { |
461 | status = "okay"; | |
462 | }; | |
463 | ||
cc2afa43 | 464 | sdhci@c8000000 { |
2a5fdc9a | 465 | status = "okay"; |
3325f1bc SW |
466 | cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; |
467 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; | |
468 | power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; | |
7f217794 | 469 | bus-width = <4>; |
cc2afa43 MD |
470 | }; |
471 | ||
cc2afa43 | 472 | sdhci@c8000600 { |
2a5fdc9a | 473 | status = "okay"; |
7f217794 | 474 | bus-width = <8>; |
7a2617a6 | 475 | non-removable; |
cc2afa43 | 476 | }; |
d8d56c84 | 477 | |
7021d122 JL |
478 | clocks { |
479 | compatible = "simple-bus"; | |
480 | #address-cells = <1>; | |
481 | #size-cells = <0>; | |
482 | ||
58ecb23f | 483 | clk32k_in: clock@0 { |
7021d122 JL |
484 | compatible = "fixed-clock"; |
485 | reg=<0>; | |
486 | #clock-cells = <0>; | |
487 | clock-frequency = <32768>; | |
488 | }; | |
489 | }; | |
490 | ||
d8d56c84 MD |
491 | gpio-keys { |
492 | compatible = "gpio-keys"; | |
493 | ||
494 | power { | |
495 | label = "Power"; | |
3325f1bc | 496 | gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; |
6bccbd5e | 497 | linux,code = <KEY_POWER>; |
d8d56c84 MD |
498 | gpio-key,wakeup; |
499 | }; | |
500 | }; | |
80c9473d MD |
501 | |
502 | gpio-leds { | |
503 | compatible = "gpio-leds"; | |
504 | ||
505 | wifi { | |
506 | label = "wifi-led"; | |
3325f1bc | 507 | gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; |
80c9473d MD |
508 | linux,default-trigger = "rfkill0"; |
509 | }; | |
510 | }; | |
aa607ebf | 511 | |
217b8f0f SW |
512 | regulators { |
513 | compatible = "simple-bus"; | |
514 | #address-cells = <1>; | |
515 | #size-cells = <0>; | |
516 | ||
517 | p5valw_reg: regulator@0 { | |
518 | compatible = "regulator-fixed"; | |
519 | reg = <0>; | |
520 | regulator-name = "+5valw"; | |
521 | regulator-min-microvolt = <5000000>; | |
522 | regulator-max-microvolt = <5000000>; | |
523 | regulator-always-on; | |
524 | }; | |
525 | }; | |
526 | ||
c04abb3a SW |
527 | sound { |
528 | compatible = "nvidia,tegra-audio-alc5632-paz00", | |
529 | "nvidia,tegra-audio-alc5632"; | |
530 | ||
531 | nvidia,model = "Compal PAZ00"; | |
532 | ||
533 | nvidia,audio-routing = | |
534 | "Int Spk", "SPKOUT", | |
535 | "Int Spk", "SPKOUTN", | |
536 | "Headset Mic", "MICBIAS1", | |
537 | "MIC1", "Headset Mic", | |
538 | "Headset Stereophone", "HPR", | |
539 | "Headset Stereophone", "HPL", | |
540 | "DMICDAT", "Digital Mic"; | |
541 | ||
542 | nvidia,audio-codec = <&alc5632>; | |
543 | nvidia,i2s-controller = <&tegra_i2s1>; | |
3325f1bc SW |
544 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) |
545 | GPIO_ACTIVE_HIGH>; | |
f9cd2b3b | 546 | |
885a8cfa HD |
547 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
548 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | |
549 | <&tegra_car TEGRA20_CLK_CDEV1>; | |
f9cd2b3b | 550 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
aa607ebf | 551 | }; |
cc2afa43 | 552 | }; |