Commit | Line | Data |
---|---|---|
cc2afa43 MD |
1 | /dts-v1/; |
2 | ||
1bd0bd49 | 3 | #include "tegra20.dtsi" |
cc2afa43 MD |
4 | |
5 | / { | |
6 | model = "Toshiba AC100 / Dynabook AZ"; | |
7 | compatible = "compal,paz00", "nvidia,tegra20"; | |
8 | ||
f9eb26a4 | 9 | memory { |
cc2afa43 MD |
10 | reg = <0x00000000 0x20000000>; |
11 | }; | |
12 | ||
11a3c868 SW |
13 | host1x { |
14 | hdmi { | |
15 | status = "okay"; | |
16 | ||
17 | vdd-supply = <&hdmi_vdd_reg>; | |
18 | pll-supply = <&hdmi_pll_reg>; | |
19 | ||
20 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
3325f1bc SW |
21 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
22 | GPIO_ACTIVE_HIGH>; | |
11a3c868 SW |
23 | }; |
24 | }; | |
25 | ||
f9eb26a4 | 26 | pinmux { |
ecc295bb SW |
27 | pinctrl-names = "default"; |
28 | pinctrl-0 = <&state_default>; | |
29 | ||
30 | state_default: pinmux { | |
31 | ata { | |
32 | nvidia,pins = "ata", "atc", "atd", "ate", | |
33 | "dap2", "gmb", "gmc", "gmd", "spia", | |
34 | "spib", "spic", "spid", "spie"; | |
35 | nvidia,function = "gmi"; | |
36 | }; | |
37 | atb { | |
38 | nvidia,pins = "atb", "gma", "gme"; | |
39 | nvidia,function = "sdio4"; | |
40 | }; | |
41 | cdev1 { | |
42 | nvidia,pins = "cdev1"; | |
43 | nvidia,function = "plla_out"; | |
44 | }; | |
45 | cdev2 { | |
46 | nvidia,pins = "cdev2"; | |
47 | nvidia,function = "pllp_out4"; | |
48 | }; | |
49 | crtp { | |
50 | nvidia,pins = "crtp"; | |
51 | nvidia,function = "crt"; | |
52 | }; | |
53 | csus { | |
54 | nvidia,pins = "csus"; | |
55 | nvidia,function = "pllc_out1"; | |
56 | }; | |
57 | dap1 { | |
58 | nvidia,pins = "dap1"; | |
59 | nvidia,function = "dap1"; | |
60 | }; | |
61 | dap3 { | |
62 | nvidia,pins = "dap3"; | |
63 | nvidia,function = "dap3"; | |
64 | }; | |
65 | dap4 { | |
66 | nvidia,pins = "dap4"; | |
67 | nvidia,function = "dap4"; | |
68 | }; | |
69 | ddc { | |
70 | nvidia,pins = "ddc"; | |
71 | nvidia,function = "i2c2"; | |
72 | }; | |
73 | dta { | |
74 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; | |
75 | nvidia,function = "rsvd1"; | |
76 | }; | |
77 | dtf { | |
78 | nvidia,pins = "dtf"; | |
79 | nvidia,function = "i2c3"; | |
80 | }; | |
81 | gpu { | |
82 | nvidia,pins = "gpu", "sdb", "sdd"; | |
83 | nvidia,function = "pwm"; | |
84 | }; | |
85 | gpu7 { | |
86 | nvidia,pins = "gpu7"; | |
87 | nvidia,function = "rtck"; | |
88 | }; | |
89 | gpv { | |
90 | nvidia,pins = "gpv", "slxa", "slxk"; | |
91 | nvidia,function = "pcie"; | |
92 | }; | |
93 | hdint { | |
94 | nvidia,pins = "hdint", "pta"; | |
95 | nvidia,function = "hdmi"; | |
96 | }; | |
97 | i2cp { | |
98 | nvidia,pins = "i2cp"; | |
99 | nvidia,function = "i2cp"; | |
100 | }; | |
101 | irrx { | |
102 | nvidia,pins = "irrx", "irtx"; | |
103 | nvidia,function = "uarta"; | |
104 | }; | |
105 | kbca { | |
106 | nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; | |
107 | nvidia,function = "kbc"; | |
108 | }; | |
109 | kbcb { | |
110 | nvidia,pins = "kbcb", "kbcd"; | |
111 | nvidia,function = "sdio2"; | |
112 | }; | |
113 | lcsn { | |
114 | nvidia,pins = "lcsn", "ld0", "ld1", "ld2", | |
115 | "ld3", "ld4", "ld5", "ld6", "ld7", | |
116 | "ld8", "ld9", "ld10", "ld11", "ld12", | |
117 | "ld13", "ld14", "ld15", "ld16", "ld17", | |
118 | "ldc", "ldi", "lhp0", "lhp1", "lhp2", | |
119 | "lhs", "lm0", "lm1", "lpp", "lpw0", | |
120 | "lpw1", "lpw2", "lsc0", "lsc1", "lsck", | |
121 | "lsda", "lsdi", "lspi", "lvp0", "lvp1", | |
122 | "lvs"; | |
123 | nvidia,function = "displaya"; | |
124 | }; | |
125 | owc { | |
126 | nvidia,pins = "owc"; | |
127 | nvidia,function = "owr"; | |
128 | }; | |
129 | pmc { | |
130 | nvidia,pins = "pmc"; | |
131 | nvidia,function = "pwr_on"; | |
132 | }; | |
133 | rm { | |
134 | nvidia,pins = "rm"; | |
135 | nvidia,function = "i2c1"; | |
136 | }; | |
137 | sdc { | |
138 | nvidia,pins = "sdc"; | |
139 | nvidia,function = "twc"; | |
140 | }; | |
141 | sdio1 { | |
142 | nvidia,pins = "sdio1"; | |
143 | nvidia,function = "sdio1"; | |
144 | }; | |
145 | slxc { | |
146 | nvidia,pins = "slxc", "slxd"; | |
147 | nvidia,function = "spi4"; | |
148 | }; | |
149 | spdi { | |
150 | nvidia,pins = "spdi", "spdo"; | |
151 | nvidia,function = "rsvd2"; | |
152 | }; | |
153 | spif { | |
154 | nvidia,pins = "spif", "uac"; | |
155 | nvidia,function = "rsvd4"; | |
156 | }; | |
157 | spig { | |
158 | nvidia,pins = "spig", "spih"; | |
159 | nvidia,function = "spi2_alt"; | |
160 | }; | |
161 | uaa { | |
162 | nvidia,pins = "uaa", "uab", "uda"; | |
163 | nvidia,function = "ulpi"; | |
164 | }; | |
165 | uad { | |
166 | nvidia,pins = "uad"; | |
167 | nvidia,function = "spdif"; | |
168 | }; | |
169 | uca { | |
170 | nvidia,pins = "uca", "ucb"; | |
171 | nvidia,function = "uartc"; | |
172 | }; | |
173 | conf_ata { | |
174 | nvidia,pins = "ata", "atb", "atc", "atd", "ate", | |
563da21b SW |
175 | "cdev1", "cdev2", "dap1", "dap2", "dtf", |
176 | "gma", "gmb", "gmc", "gmd", "gme", | |
177 | "gpu", "gpu7", "gpv", "i2cp", "pta", | |
178 | "rm", "sdio1", "slxk", "spdo", "uac", | |
179 | "uda"; | |
ecc295bb SW |
180 | nvidia,pull = <0>; |
181 | nvidia,tristate = <0>; | |
182 | }; | |
ecc295bb SW |
183 | conf_ck32 { |
184 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | |
185 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | |
186 | nvidia,pull = <0>; | |
187 | }; | |
188 | conf_crtp { | |
189 | nvidia,pins = "crtp", "dap3", "dap4", "dtb", | |
190 | "dtc", "dte", "slxa", "slxc", "slxd", | |
191 | "spdi"; | |
192 | nvidia,pull = <0>; | |
193 | nvidia,tristate = <1>; | |
194 | }; | |
195 | conf_csus { | |
196 | nvidia,pins = "csus", "spia", "spib", "spid", | |
197 | "spif"; | |
198 | nvidia,pull = <1>; | |
199 | nvidia,tristate = <1>; | |
200 | }; | |
201 | conf_ddc { | |
202 | nvidia,pins = "ddc", "irrx", "irtx", "kbca", | |
203 | "kbcb", "kbcc", "kbcd", "kbce", "kbcf", | |
204 | "spic", "spig", "uaa", "uab"; | |
205 | nvidia,pull = <2>; | |
206 | nvidia,tristate = <0>; | |
207 | }; | |
208 | conf_dta { | |
209 | nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", | |
210 | "spie", "spih", "uad", "uca", "ucb"; | |
211 | nvidia,pull = <2>; | |
212 | nvidia,tristate = <1>; | |
213 | }; | |
214 | conf_hdint { | |
215 | nvidia,pins = "hdint", "ld0", "ld1", "ld2", | |
216 | "ld3", "ld4", "ld5", "ld6", "ld7", | |
217 | "ld8", "ld9", "ld10", "ld11", "ld12", | |
218 | "ld13", "ld14", "ld15", "ld16", "ld17", | |
219 | "ldc", "ldi", "lhs", "lsc0", "lspi", | |
220 | "lvs", "pmc"; | |
221 | nvidia,tristate = <0>; | |
222 | }; | |
223 | conf_lc { | |
224 | nvidia,pins = "lc", "ls"; | |
225 | nvidia,pull = <2>; | |
226 | }; | |
227 | conf_lcsn { | |
228 | nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", | |
229 | "lm0", "lm1", "lpp", "lpw0", "lpw1", | |
230 | "lpw2", "lsc1", "lsck", "lsda", "lsdi", | |
231 | "lvp0", "lvp1", "sdb"; | |
232 | nvidia,tristate = <1>; | |
233 | }; | |
234 | conf_ld17_0 { | |
235 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | |
236 | "ld23_22"; | |
237 | nvidia,pull = <1>; | |
238 | }; | |
239 | }; | |
240 | }; | |
241 | ||
2a5fdc9a SW |
242 | i2s@70002800 { |
243 | status = "okay"; | |
c04abb3a SW |
244 | }; |
245 | ||
246 | serial@70006000 { | |
2a5fdc9a | 247 | status = "okay"; |
c04abb3a SW |
248 | }; |
249 | ||
c04abb3a | 250 | serial@70006200 { |
2a5fdc9a | 251 | status = "okay"; |
c04abb3a SW |
252 | }; |
253 | ||
cc2afa43 | 254 | i2c@7000c000 { |
2a5fdc9a | 255 | status = "okay"; |
cc2afa43 | 256 | clock-frequency = <400000>; |
613e9657 LR |
257 | |
258 | alc5632: alc5632@1e { | |
259 | compatible = "realtek,alc5632"; | |
260 | reg = <0x1e>; | |
261 | gpio-controller; | |
262 | #gpio-cells = <2>; | |
263 | }; | |
cc2afa43 MD |
264 | }; |
265 | ||
11a3c868 | 266 | hdmi_ddc: i2c@7000c400 { |
2a5fdc9a | 267 | status = "okay"; |
11a3c868 | 268 | clock-frequency = <100000>; |
cc2afa43 MD |
269 | }; |
270 | ||
f9eb26a4 | 271 | nvec { |
cc2afa43 | 272 | compatible = "nvidia,nvec"; |
ba04c289 | 273 | reg = <0x7000c500 0x100>; |
6cecf916 | 274 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
275 | #address-cells = <1>; |
276 | #size-cells = <0>; | |
cc2afa43 | 277 | clock-frequency = <80000>; |
3325f1bc | 278 | request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; |
cc2afa43 | 279 | slave-addr = <138>; |
885a8cfa HD |
280 | clocks = <&tegra_car TEGRA20_CLK_I2C3>, |
281 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
d409b3af | 282 | clock-names = "div-clk", "fast-clk"; |
cc2afa43 MD |
283 | }; |
284 | ||
285 | i2c@7000d000 { | |
2a5fdc9a | 286 | status = "okay"; |
cc2afa43 | 287 | clock-frequency = <400000>; |
1266f897 | 288 | |
217b8f0f SW |
289 | pmic: tps6586x@34 { |
290 | compatible = "ti,tps6586x"; | |
291 | reg = <0x34>; | |
6cecf916 | 292 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
217b8f0f SW |
293 | |
294 | #gpio-cells = <2>; | |
295 | gpio-controller; | |
296 | ||
297 | sys-supply = <&p5valw_reg>; | |
298 | vin-sm0-supply = <&sys_reg>; | |
299 | vin-sm1-supply = <&sys_reg>; | |
300 | vin-sm2-supply = <&sys_reg>; | |
301 | vinldo01-supply = <&sm2_reg>; | |
302 | vinldo23-supply = <&sm2_reg>; | |
303 | vinldo4-supply = <&sm2_reg>; | |
304 | vinldo678-supply = <&sm2_reg>; | |
305 | vinldo9-supply = <&sm2_reg>; | |
306 | ||
307 | regulators { | |
b9c665d7 | 308 | sys_reg: sys { |
217b8f0f SW |
309 | regulator-name = "vdd_sys"; |
310 | regulator-always-on; | |
311 | }; | |
312 | ||
b9c665d7 | 313 | sm0 { |
217b8f0f SW |
314 | regulator-name = "+1.2vs_sm0,vdd_core"; |
315 | regulator-min-microvolt = <1200000>; | |
316 | regulator-max-microvolt = <1200000>; | |
317 | regulator-always-on; | |
318 | }; | |
319 | ||
b9c665d7 | 320 | sm1 { |
217b8f0f SW |
321 | regulator-name = "+1.0vs_sm1,vdd_cpu"; |
322 | regulator-min-microvolt = <1000000>; | |
323 | regulator-max-microvolt = <1000000>; | |
324 | regulator-always-on; | |
325 | }; | |
326 | ||
b9c665d7 | 327 | sm2_reg: sm2 { |
217b8f0f SW |
328 | regulator-name = "+3.7vs_sm2,vin_ldo*"; |
329 | regulator-min-microvolt = <3700000>; | |
330 | regulator-max-microvolt = <3700000>; | |
331 | regulator-always-on; | |
332 | }; | |
333 | ||
334 | /* LDO0 is not connected to anything */ | |
335 | ||
b9c665d7 | 336 | ldo1 { |
217b8f0f SW |
337 | regulator-name = "+1.1vs_ldo1,avdd_pll*"; |
338 | regulator-min-microvolt = <1100000>; | |
339 | regulator-max-microvolt = <1100000>; | |
340 | regulator-always-on; | |
341 | }; | |
342 | ||
b9c665d7 | 343 | ldo2 { |
217b8f0f SW |
344 | regulator-name = "+1.2vs_ldo2,vdd_rtc"; |
345 | regulator-min-microvolt = <1200000>; | |
346 | regulator-max-microvolt = <1200000>; | |
347 | }; | |
348 | ||
b9c665d7 | 349 | ldo3 { |
217b8f0f SW |
350 | regulator-name = "+3.3vs_ldo3,avdd_usb*"; |
351 | regulator-min-microvolt = <3300000>; | |
352 | regulator-max-microvolt = <3300000>; | |
353 | regulator-always-on; | |
354 | }; | |
355 | ||
b9c665d7 | 356 | ldo4 { |
217b8f0f SW |
357 | regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; |
358 | regulator-min-microvolt = <1800000>; | |
359 | regulator-max-microvolt = <1800000>; | |
360 | regulator-always-on; | |
361 | }; | |
362 | ||
b9c665d7 | 363 | ldo5 { |
217b8f0f SW |
364 | regulator-name = "+2.85vs_ldo5,vcore_mmc"; |
365 | regulator-min-microvolt = <2850000>; | |
366 | regulator-max-microvolt = <2850000>; | |
367 | regulator-always-on; | |
368 | }; | |
369 | ||
b9c665d7 | 370 | ldo6 { |
217b8f0f SW |
371 | /* |
372 | * Research indicates this should be | |
373 | * 1.8v; other boards that use this | |
374 | * rail for the same purpose need it | |
375 | * set to 1.8v. The schematic signal | |
376 | * name is incorrect; perhaps copied | |
377 | * from an incorrect NVIDIA reference. | |
378 | */ | |
379 | regulator-name = "+2.85vs_ldo6,avdd_vdac"; | |
380 | regulator-min-microvolt = <1800000>; | |
381 | regulator-max-microvolt = <1800000>; | |
382 | }; | |
383 | ||
11a3c868 | 384 | hdmi_vdd_reg: ldo7 { |
217b8f0f SW |
385 | regulator-name = "+3.3vs_ldo7,avdd_hdmi"; |
386 | regulator-min-microvolt = <3300000>; | |
387 | regulator-max-microvolt = <3300000>; | |
388 | }; | |
389 | ||
11a3c868 | 390 | hdmi_pll_reg: ldo8 { |
217b8f0f SW |
391 | regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; |
392 | regulator-min-microvolt = <1800000>; | |
393 | regulator-max-microvolt = <1800000>; | |
394 | }; | |
395 | ||
b9c665d7 | 396 | ldo9 { |
217b8f0f SW |
397 | regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; |
398 | regulator-min-microvolt = <2850000>; | |
399 | regulator-max-microvolt = <2850000>; | |
400 | regulator-always-on; | |
401 | }; | |
402 | ||
b9c665d7 | 403 | ldo_rtc { |
217b8f0f SW |
404 | regulator-name = "+3.3vs_rtc"; |
405 | regulator-min-microvolt = <3300000>; | |
406 | regulator-max-microvolt = <3300000>; | |
407 | regulator-always-on; | |
408 | }; | |
409 | }; | |
410 | }; | |
411 | ||
1266f897 MD |
412 | adt7461@4c { |
413 | compatible = "adi,adt7461"; | |
414 | reg = <0x4c>; | |
415 | }; | |
cc2afa43 MD |
416 | }; |
417 | ||
217b8f0f SW |
418 | pmc { |
419 | nvidia,invert-interrupt; | |
a44a019d JL |
420 | nvidia,suspend-mode = <2>; |
421 | nvidia,cpu-pwr-good-time = <2000>; | |
422 | nvidia,cpu-pwr-off-time = <0>; | |
423 | nvidia,core-pwr-good-time = <3845 3845>; | |
424 | nvidia,core-pwr-off-time = <0>; | |
425 | nvidia,sys-clock-req-active-high; | |
217b8f0f SW |
426 | }; |
427 | ||
2a5fdc9a SW |
428 | usb@c5000000 { |
429 | status = "okay"; | |
430 | }; | |
431 | ||
4c94c8b5 VB |
432 | usb-phy@c5000000 { |
433 | status = "okay"; | |
434 | }; | |
435 | ||
c04abb3a | 436 | usb@c5004000 { |
2a5fdc9a | 437 | status = "okay"; |
3325f1bc SW |
438 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
439 | GPIO_ACTIVE_LOW>; | |
cc2afa43 MD |
440 | }; |
441 | ||
9dffe3be | 442 | usb-phy@c5004000 { |
4c94c8b5 | 443 | status = "okay"; |
3325f1bc SW |
444 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
445 | GPIO_ACTIVE_LOW>; | |
2a5fdc9a SW |
446 | }; |
447 | ||
9dffe3be VB |
448 | usb@c5008000 { |
449 | status = "okay"; | |
40e8b3a6 VB |
450 | }; |
451 | ||
4c94c8b5 VB |
452 | usb-phy@c5008000 { |
453 | status = "okay"; | |
454 | }; | |
455 | ||
cc2afa43 | 456 | sdhci@c8000000 { |
2a5fdc9a | 457 | status = "okay"; |
3325f1bc SW |
458 | cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; |
459 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; | |
460 | power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; | |
7f217794 | 461 | bus-width = <4>; |
cc2afa43 MD |
462 | }; |
463 | ||
cc2afa43 | 464 | sdhci@c8000600 { |
2a5fdc9a | 465 | status = "okay"; |
7f217794 | 466 | bus-width = <8>; |
7a2617a6 | 467 | non-removable; |
cc2afa43 | 468 | }; |
d8d56c84 | 469 | |
7021d122 JL |
470 | clocks { |
471 | compatible = "simple-bus"; | |
472 | #address-cells = <1>; | |
473 | #size-cells = <0>; | |
474 | ||
475 | clk32k_in: clock { | |
476 | compatible = "fixed-clock"; | |
477 | reg=<0>; | |
478 | #clock-cells = <0>; | |
479 | clock-frequency = <32768>; | |
480 | }; | |
481 | }; | |
482 | ||
d8d56c84 MD |
483 | gpio-keys { |
484 | compatible = "gpio-keys"; | |
485 | ||
486 | power { | |
487 | label = "Power"; | |
3325f1bc | 488 | gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; |
d8d56c84 MD |
489 | linux,code = <116>; /* KEY_POWER */ |
490 | gpio-key,wakeup; | |
491 | }; | |
492 | }; | |
80c9473d MD |
493 | |
494 | gpio-leds { | |
495 | compatible = "gpio-leds"; | |
496 | ||
497 | wifi { | |
498 | label = "wifi-led"; | |
3325f1bc | 499 | gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; |
80c9473d MD |
500 | linux,default-trigger = "rfkill0"; |
501 | }; | |
502 | }; | |
aa607ebf | 503 | |
217b8f0f SW |
504 | regulators { |
505 | compatible = "simple-bus"; | |
506 | #address-cells = <1>; | |
507 | #size-cells = <0>; | |
508 | ||
509 | p5valw_reg: regulator@0 { | |
510 | compatible = "regulator-fixed"; | |
511 | reg = <0>; | |
512 | regulator-name = "+5valw"; | |
513 | regulator-min-microvolt = <5000000>; | |
514 | regulator-max-microvolt = <5000000>; | |
515 | regulator-always-on; | |
516 | }; | |
517 | }; | |
518 | ||
c04abb3a SW |
519 | sound { |
520 | compatible = "nvidia,tegra-audio-alc5632-paz00", | |
521 | "nvidia,tegra-audio-alc5632"; | |
522 | ||
523 | nvidia,model = "Compal PAZ00"; | |
524 | ||
525 | nvidia,audio-routing = | |
526 | "Int Spk", "SPKOUT", | |
527 | "Int Spk", "SPKOUTN", | |
528 | "Headset Mic", "MICBIAS1", | |
529 | "MIC1", "Headset Mic", | |
530 | "Headset Stereophone", "HPR", | |
531 | "Headset Stereophone", "HPL", | |
532 | "DMICDAT", "Digital Mic"; | |
533 | ||
534 | nvidia,audio-codec = <&alc5632>; | |
535 | nvidia,i2s-controller = <&tegra_i2s1>; | |
3325f1bc SW |
536 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) |
537 | GPIO_ACTIVE_HIGH>; | |
f9cd2b3b | 538 | |
885a8cfa HD |
539 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
540 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | |
541 | <&tegra_car TEGRA20_CLK_CDEV1>; | |
f9cd2b3b | 542 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
aa607ebf | 543 | }; |
cc2afa43 | 544 | }; |