projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 8e267f3d GL |
1 | /dts-v1/; |
| 2 | ||
| 8e267f3d GL |
3 | /include/ "tegra20.dtsi" |
| 4 | ||
| 5 | / { | |
| 6 | model = "NVIDIA Seaboard"; | |
| 7 | compatible = "nvidia,seaboard", "nvidia,tegra20"; | |
| 8 | ||
| 8e267f3d | 9 | memory { |
| 95decf84 | 10 | reg = <0x00000000 0x40000000>; |
| 8e267f3d GL |
11 | }; |
| 12 | ||
| f9eb26a4 | 13 | pinmux { |
| ecc295bb SW |
14 | pinctrl-names = "default"; |
| 15 | pinctrl-0 = <&state_default>; | |
| 16 | ||
| 17 | state_default: pinmux { | |
| 18 | ata { | |
| 19 | nvidia,pins = "ata"; | |
| 20 | nvidia,function = "ide"; | |
| 21 | }; | |
| 22 | atb { | |
| 23 | nvidia,pins = "atb", "gma", "gme"; | |
| 24 | nvidia,function = "sdio4"; | |
| 25 | }; | |
| 26 | atc { | |
| 27 | nvidia,pins = "atc"; | |
| 28 | nvidia,function = "nand"; | |
| 29 | }; | |
| 30 | atd { | |
| 31 | nvidia,pins = "atd", "ate", "gmb", "spia", | |
| 32 | "spib", "spic"; | |
| 33 | nvidia,function = "gmi"; | |
| 34 | }; | |
| 35 | cdev1 { | |
| 36 | nvidia,pins = "cdev1"; | |
| 37 | nvidia,function = "plla_out"; | |
| 38 | }; | |
| 39 | cdev2 { | |
| 40 | nvidia,pins = "cdev2"; | |
| 41 | nvidia,function = "pllp_out4"; | |
| 42 | }; | |
| 43 | crtp { | |
| 44 | nvidia,pins = "crtp", "lm1"; | |
| 45 | nvidia,function = "crt"; | |
| 46 | }; | |
| 47 | csus { | |
| 48 | nvidia,pins = "csus"; | |
| 49 | nvidia,function = "vi_sensor_clk"; | |
| 50 | }; | |
| 51 | dap1 { | |
| 52 | nvidia,pins = "dap1"; | |
| 53 | nvidia,function = "dap1"; | |
| 54 | }; | |
| 55 | dap2 { | |
| 56 | nvidia,pins = "dap2"; | |
| 57 | nvidia,function = "dap2"; | |
| 58 | }; | |
| 59 | dap3 { | |
| 60 | nvidia,pins = "dap3"; | |
| 61 | nvidia,function = "dap3"; | |
| 62 | }; | |
| 63 | dap4 { | |
| 64 | nvidia,pins = "dap4"; | |
| 65 | nvidia,function = "dap4"; | |
| 66 | }; | |
| ecc295bb SW |
67 | dta { |
| 68 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; | |
| 69 | nvidia,function = "vi"; | |
| 70 | }; | |
| 71 | dtf { | |
| 72 | nvidia,pins = "dtf"; | |
| 73 | nvidia,function = "i2c3"; | |
| 74 | }; | |
| 75 | gmc { | |
| 76 | nvidia,pins = "gmc"; | |
| 77 | nvidia,function = "uartd"; | |
| 78 | }; | |
| 79 | gmd { | |
| 80 | nvidia,pins = "gmd"; | |
| 81 | nvidia,function = "sflash"; | |
| 82 | }; | |
| 83 | gpu { | |
| 84 | nvidia,pins = "gpu"; | |
| 85 | nvidia,function = "pwm"; | |
| 86 | }; | |
| 87 | gpu7 { | |
| 88 | nvidia,pins = "gpu7"; | |
| 89 | nvidia,function = "rtck"; | |
| 90 | }; | |
| 91 | gpv { | |
| 92 | nvidia,pins = "gpv", "slxa", "slxk"; | |
| 93 | nvidia,function = "pcie"; | |
| 94 | }; | |
| 95 | hdint { | |
| 96 | nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1", | |
| 802a8499 | 97 | "lsck", "lsda"; |
| ecc295bb SW |
98 | nvidia,function = "hdmi"; |
| 99 | }; | |
| 100 | i2cp { | |
| 101 | nvidia,pins = "i2cp"; | |
| 102 | nvidia,function = "i2cp"; | |
| 103 | }; | |
| 104 | irrx { | |
| 105 | nvidia,pins = "irrx", "irtx"; | |
| 106 | nvidia,function = "uartb"; | |
| 107 | }; | |
| 108 | kbca { | |
| 109 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
| 110 | "kbce", "kbcf"; | |
| 111 | nvidia,function = "kbc"; | |
| 112 | }; | |
| 113 | lcsn { | |
| 114 | nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", | |
| 115 | "lsdi", "lvp0"; | |
| 116 | nvidia,function = "rsvd4"; | |
| 117 | }; | |
| 118 | ld0 { | |
| 119 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
| 120 | "ld5", "ld6", "ld7", "ld8", "ld9", | |
| 121 | "ld10", "ld11", "ld12", "ld13", "ld14", | |
| 122 | "ld15", "ld16", "ld17", "ldi", "lhp0", | |
| 123 | "lhp1", "lhp2", "lhs", "lpp", "lsc0", | |
| 124 | "lspi", "lvp1", "lvs"; | |
| 125 | nvidia,function = "displaya"; | |
| 126 | }; | |
| a18cf6dc SW |
127 | owc { |
| 128 | nvidia,pins = "owc", "spdi", "spdo", "uac"; | |
| 129 | nvidia,function = "rsvd2"; | |
| 130 | }; | |
| ecc295bb SW |
131 | pmc { |
| 132 | nvidia,pins = "pmc"; | |
| 133 | nvidia,function = "pwr_on"; | |
| 134 | }; | |
| 135 | rm { | |
| 136 | nvidia,pins = "rm"; | |
| 137 | nvidia,function = "i2c1"; | |
| 138 | }; | |
| 139 | sdb { | |
| 140 | nvidia,pins = "sdb", "sdc", "sdd"; | |
| 141 | nvidia,function = "sdio3"; | |
| 142 | }; | |
| 143 | sdio1 { | |
| 144 | nvidia,pins = "sdio1"; | |
| 145 | nvidia,function = "sdio1"; | |
| 146 | }; | |
| 147 | slxc { | |
| 148 | nvidia,pins = "slxc", "slxd"; | |
| 149 | nvidia,function = "spdif"; | |
| 150 | }; | |
| 151 | spid { | |
| 152 | nvidia,pins = "spid", "spie", "spif"; | |
| 153 | nvidia,function = "spi1"; | |
| 154 | }; | |
| 155 | spig { | |
| 156 | nvidia,pins = "spig", "spih"; | |
| 157 | nvidia,function = "spi2_alt"; | |
| 158 | }; | |
| 159 | uaa { | |
| 160 | nvidia,pins = "uaa", "uab", "uda"; | |
| 161 | nvidia,function = "ulpi"; | |
| 162 | }; | |
| 163 | uad { | |
| 164 | nvidia,pins = "uad"; | |
| 165 | nvidia,function = "irda"; | |
| 166 | }; | |
| 167 | uca { | |
| 168 | nvidia,pins = "uca", "ucb"; | |
| 169 | nvidia,function = "uartc"; | |
| 170 | }; | |
| 171 | conf_ata { | |
| 172 | nvidia,pins = "ata", "atb", "atc", "atd", | |
| 173 | "cdev1", "cdev2", "dap1", "dap2", | |
| a18cf6dc | 174 | "dap4", "ddc", "dtf", "gma", "gmc", "gmd", |
| ecc295bb SW |
175 | "gme", "gpu", "gpu7", "i2cp", "irrx", |
| 176 | "irtx", "pta", "rm", "sdc", "sdd", | |
| 177 | "slxd", "slxk", "spdi", "spdo", "uac", | |
| 178 | "uad", "uca", "ucb", "uda"; | |
| 179 | nvidia,pull = <0>; | |
| 180 | nvidia,tristate = <0>; | |
| 181 | }; | |
| 182 | conf_ate { | |
| a18cf6dc | 183 | nvidia,pins = "ate", "csus", "dap3", |
| ecc295bb SW |
184 | "gpv", "owc", "slxc", "spib", "spid", |
| 185 | "spie"; | |
| 186 | nvidia,pull = <0>; | |
| 187 | nvidia,tristate = <1>; | |
| 188 | }; | |
| 189 | conf_ck32 { | |
| 190 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | |
| 191 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | |
| 192 | nvidia,pull = <0>; | |
| 193 | }; | |
| 194 | conf_crtp { | |
| 195 | nvidia,pins = "crtp", "gmb", "slxa", "spia", | |
| 196 | "spig", "spih"; | |
| 197 | nvidia,pull = <2>; | |
| 198 | nvidia,tristate = <1>; | |
| 199 | }; | |
| 200 | conf_dta { | |
| 201 | nvidia,pins = "dta", "dtb", "dtc", "dtd"; | |
| 202 | nvidia,pull = <1>; | |
| 203 | nvidia,tristate = <0>; | |
| 204 | }; | |
| 205 | conf_dte { | |
| 206 | nvidia,pins = "dte", "spif"; | |
| 207 | nvidia,pull = <1>; | |
| 208 | nvidia,tristate = <1>; | |
| 209 | }; | |
| 210 | conf_hdint { | |
| 211 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", | |
| 212 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", | |
| 213 | "lvp0"; | |
| 214 | nvidia,tristate = <1>; | |
| 215 | }; | |
| 216 | conf_kbca { | |
| 217 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
| 218 | "kbce", "kbcf", "sdio1", "spic", "uaa", | |
| 219 | "uab"; | |
| 220 | nvidia,pull = <2>; | |
| 221 | nvidia,tristate = <0>; | |
| 222 | }; | |
| 223 | conf_lc { | |
| 224 | nvidia,pins = "lc", "ls"; | |
| 225 | nvidia,pull = <2>; | |
| 226 | }; | |
| 227 | conf_ld0 { | |
| 228 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
| 229 | "ld5", "ld6", "ld7", "ld8", "ld9", | |
| 230 | "ld10", "ld11", "ld12", "ld13", "ld14", | |
| 231 | "ld15", "ld16", "ld17", "ldi", "lhp0", | |
| 232 | "lhp1", "lhp2", "lhs", "lm0", "lpp", | |
| 233 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", | |
| 234 | "lvs", "pmc", "sdb"; | |
| 235 | nvidia,tristate = <0>; | |
| 236 | }; | |
| 237 | conf_ld17_0 { | |
| 238 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | |
| 239 | "ld23_22"; | |
| 240 | nvidia,pull = <1>; | |
| 241 | }; | |
| 242 | drive_sdio1 { | |
| 243 | nvidia,pins = "drive_sdio1"; | |
| 244 | nvidia,high-speed-mode = <0>; | |
| 245 | nvidia,schmitt = <0>; | |
| 246 | nvidia,low-power-mode = <3>; | |
| 247 | nvidia,pull-down-strength = <31>; | |
| 248 | nvidia,pull-up-strength = <31>; | |
| 249 | nvidia,slew-rate-rising = <3>; | |
| 250 | nvidia,slew-rate-falling = <3>; | |
| 251 | }; | |
| 252 | }; | |
| a18cf6dc SW |
253 | |
| 254 | state_i2cmux_ddc: pinmux_i2cmux_ddc { | |
| 255 | ddc { | |
| 256 | nvidia,pins = "ddc"; | |
| 257 | nvidia,function = "i2c2"; | |
| 258 | }; | |
| 259 | pta { | |
| 260 | nvidia,pins = "pta"; | |
| 261 | nvidia,function = "rsvd4"; | |
| 262 | }; | |
| 263 | }; | |
| 264 | ||
| 265 | state_i2cmux_pta: pinmux_i2cmux_pta { | |
| 266 | ddc { | |
| 267 | nvidia,pins = "ddc"; | |
| 268 | nvidia,function = "rsvd4"; | |
| 269 | }; | |
| 270 | pta { | |
| 271 | nvidia,pins = "pta"; | |
| 272 | nvidia,function = "i2c2"; | |
| 273 | }; | |
| 274 | }; | |
| 275 | ||
| 276 | state_i2cmux_idle: pinmux_i2cmux_idle { | |
| 277 | ddc { | |
| 278 | nvidia,pins = "ddc"; | |
| 279 | nvidia,function = "rsvd4"; | |
| 280 | }; | |
| 281 | pta { | |
| 282 | nvidia,pins = "pta"; | |
| 283 | nvidia,function = "rsvd4"; | |
| 284 | }; | |
| 285 | }; | |
| ecc295bb SW |
286 | }; |
| 287 | ||
| 2a5fdc9a SW |
288 | i2s@70002800 { |
| 289 | status = "okay"; | |
| c04abb3a SW |
290 | }; |
| 291 | ||
| 292 | serial@70006300 { | |
| 2a5fdc9a | 293 | status = "okay"; |
| c04abb3a SW |
294 | clock-frequency = <216000000>; |
| 295 | }; | |
| 296 | ||
| 88950f3b | 297 | i2c@7000c000 { |
| 2a5fdc9a | 298 | status = "okay"; |
| 88950f3b | 299 | clock-frequency = <400000>; |
| 797acf70 SW |
300 | |
| 301 | wm8903: wm8903@1a { | |
| 302 | compatible = "wlf,wm8903"; | |
| 303 | reg = <0x1a>; | |
| 304 | interrupt-parent = <&gpio>; | |
| 95decf84 | 305 | interrupts = <187 0x04>; |
| 797acf70 SW |
306 | |
| 307 | gpio-controller; | |
| 308 | #gpio-cells = <2>; | |
| 309 | ||
| 310 | micdet-cfg = <0>; | |
| 311 | micdet-delay = <100>; | |
| 95decf84 | 312 | gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; |
| 797acf70 | 313 | }; |
| b46b0b54 LD |
314 | |
| 315 | /* ALS and proximity sensor */ | |
| 316 | isl29018@44 { | |
| 317 | compatible = "isil,isl29018"; | |
| 318 | reg = <0x44>; | |
| 319 | interrupt-parent = <&gpio>; | |
| 95decf84 | 320 | interrupts = <202 0x04>; /* GPIO PZ2 */ |
| b46b0b54 | 321 | }; |
| 45dbe9dd OJ |
322 | |
| 323 | gyrometer@68 { | |
| 324 | compatible = "invn,mpu3050"; | |
| 325 | reg = <0x68>; | |
| 326 | interrupt-parent = <&gpio>; | |
| 327 | interrupts = <204 0x04>; /* gpio PZ4 */ | |
| 328 | }; | |
| 88950f3b SW |
329 | }; |
| 330 | ||
| 331 | i2c@7000c400 { | |
| 2a5fdc9a | 332 | status = "okay"; |
| 22bd1f7e | 333 | clock-frequency = <100000>; |
| 88950f3b SW |
334 | }; |
| 335 | ||
| a18cf6dc SW |
336 | i2cmux { |
| 337 | compatible = "i2c-mux-pinctrl"; | |
| 338 | #address-cells = <1>; | |
| 339 | #size-cells = <0>; | |
| 340 | ||
| 341 | i2c-parent = <&{/i2c@7000c400}>; | |
| 342 | ||
| 343 | pinctrl-names = "ddc", "pta", "idle"; | |
| 344 | pinctrl-0 = <&state_i2cmux_ddc>; | |
| 345 | pinctrl-1 = <&state_i2cmux_pta>; | |
| 346 | pinctrl-2 = <&state_i2cmux_idle>; | |
| 347 | ||
| 348 | i2c@0 { | |
| 349 | reg = <0>; | |
| 350 | #address-cells = <1>; | |
| 351 | #size-cells = <0>; | |
| 352 | }; | |
| 353 | ||
| 354 | i2c@1 { | |
| 355 | reg = <1>; | |
| 356 | #address-cells = <1>; | |
| 357 | #size-cells = <0>; | |
| 0879c5f7 SW |
358 | |
| 359 | smart-battery@b { | |
| 360 | compatible = "ti,bq20z75", "smart-battery-1.1"; | |
| 361 | reg = <0xb>; | |
| 362 | ti,i2c-retry-count = <2>; | |
| 363 | ti,poll-retry-count = <10>; | |
| 364 | }; | |
| a18cf6dc SW |
365 | }; |
| 366 | }; | |
| 367 | ||
| 88950f3b | 368 | i2c@7000c500 { |
| 2a5fdc9a | 369 | status = "okay"; |
| 88950f3b SW |
370 | clock-frequency = <400000>; |
| 371 | }; | |
| 372 | ||
| 373 | i2c@7000d000 { | |
| 2a5fdc9a | 374 | status = "okay"; |
| 88950f3b | 375 | clock-frequency = <400000>; |
| 401c9a50 | 376 | |
| 6529e638 SW |
377 | pmic: tps6586x@34 { |
| 378 | compatible = "ti,tps6586x"; | |
| 379 | reg = <0x34>; | |
| 380 | interrupts = <0 86 0x4>; | |
| 381 | ||
| 44b12ef7 SW |
382 | ti,system-power-controller; |
| 383 | ||
| 6529e638 SW |
384 | #gpio-cells = <2>; |
| 385 | gpio-controller; | |
| 386 | ||
| 387 | sys-supply = <&vdd_5v0_reg>; | |
| 388 | vin-sm0-supply = <&sys_reg>; | |
| 389 | vin-sm1-supply = <&sys_reg>; | |
| 390 | vin-sm2-supply = <&sys_reg>; | |
| 391 | vinldo01-supply = <&sm2_reg>; | |
| 392 | vinldo23-supply = <&sm2_reg>; | |
| 393 | vinldo4-supply = <&sm2_reg>; | |
| 394 | vinldo678-supply = <&sm2_reg>; | |
| 395 | vinldo9-supply = <&sm2_reg>; | |
| 396 | ||
| 397 | regulators { | |
| b9c665d7 | 398 | sys_reg: sys { |
| 6529e638 SW |
399 | regulator-name = "vdd_sys"; |
| 400 | regulator-always-on; | |
| 401 | }; | |
| 402 | ||
| b9c665d7 | 403 | sm0 { |
| 6529e638 SW |
404 | regulator-name = "vdd_sm0,vdd_core"; |
| 405 | regulator-min-microvolt = <1300000>; | |
| 406 | regulator-max-microvolt = <1300000>; | |
| 407 | regulator-always-on; | |
| 408 | }; | |
| 409 | ||
| b9c665d7 | 410 | sm1 { |
| 6529e638 SW |
411 | regulator-name = "vdd_sm1,vdd_cpu"; |
| 412 | regulator-min-microvolt = <1125000>; | |
| 413 | regulator-max-microvolt = <1125000>; | |
| 414 | regulator-always-on; | |
| 415 | }; | |
| 416 | ||
| b9c665d7 | 417 | sm2_reg: sm2 { |
| 6529e638 SW |
418 | regulator-name = "vdd_sm2,vin_ldo*"; |
| 419 | regulator-min-microvolt = <3700000>; | |
| 420 | regulator-max-microvolt = <3700000>; | |
| 421 | regulator-always-on; | |
| 422 | }; | |
| 423 | ||
| 424 | /* LDO0 is not connected to anything */ | |
| 425 | ||
| b9c665d7 | 426 | ldo1 { |
| 6529e638 SW |
427 | regulator-name = "vdd_ldo1,avdd_pll*"; |
| 428 | regulator-min-microvolt = <1100000>; | |
| 429 | regulator-max-microvolt = <1100000>; | |
| 430 | regulator-always-on; | |
| 431 | }; | |
| 432 | ||
| b9c665d7 | 433 | ldo2 { |
| 6529e638 SW |
434 | regulator-name = "vdd_ldo2,vdd_rtc"; |
| 435 | regulator-min-microvolt = <1200000>; | |
| 436 | regulator-max-microvolt = <1200000>; | |
| 437 | }; | |
| 438 | ||
| b9c665d7 | 439 | ldo3 { |
| 6529e638 SW |
440 | regulator-name = "vdd_ldo3,avdd_usb*"; |
| 441 | regulator-min-microvolt = <3300000>; | |
| 442 | regulator-max-microvolt = <3300000>; | |
| 443 | regulator-always-on; | |
| 444 | }; | |
| 445 | ||
| b9c665d7 | 446 | ldo4 { |
| 6529e638 SW |
447 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; |
| 448 | regulator-min-microvolt = <1800000>; | |
| 449 | regulator-max-microvolt = <1800000>; | |
| 450 | regulator-always-on; | |
| 451 | }; | |
| 452 | ||
| b9c665d7 | 453 | ldo5 { |
| 6529e638 SW |
454 | regulator-name = "vdd_ldo5,vcore_mmc"; |
| 455 | regulator-min-microvolt = <2850000>; | |
| 456 | regulator-max-microvolt = <2850000>; | |
| 457 | regulator-always-on; | |
| 458 | }; | |
| 459 | ||
| b9c665d7 | 460 | ldo6 { |
| 6529e638 SW |
461 | regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; |
| 462 | regulator-min-microvolt = <1800000>; | |
| 463 | regulator-max-microvolt = <1800000>; | |
| 464 | }; | |
| 465 | ||
| b9c665d7 | 466 | ldo7 { |
| 6529e638 SW |
467 | regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; |
| 468 | regulator-min-microvolt = <3300000>; | |
| 469 | regulator-max-microvolt = <3300000>; | |
| 470 | }; | |
| 471 | ||
| b9c665d7 | 472 | ldo8 { |
| 6529e638 SW |
473 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; |
| 474 | regulator-min-microvolt = <1800000>; | |
| 475 | regulator-max-microvolt = <1800000>; | |
| 476 | }; | |
| 477 | ||
| b9c665d7 | 478 | ldo9 { |
| 6529e638 SW |
479 | regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; |
| 480 | regulator-min-microvolt = <2850000>; | |
| 481 | regulator-max-microvolt = <2850000>; | |
| 482 | regulator-always-on; | |
| 483 | }; | |
| 484 | ||
| b9c665d7 | 485 | ldo_rtc { |
| 6529e638 SW |
486 | regulator-name = "vdd_rtc_out,vdd_cell"; |
| 487 | regulator-min-microvolt = <3300000>; | |
| 488 | regulator-max-microvolt = <3300000>; | |
| 489 | regulator-always-on; | |
| 490 | }; | |
| 491 | }; | |
| 492 | }; | |
| 493 | ||
| 45dbe9dd | 494 | temperature-sensor@4c { |
| 9846210b | 495 | compatible = "onnn,nct1008"; |
| 401c9a50 SW |
496 | reg = <0x4c>; |
| 497 | }; | |
| 45dbe9dd OJ |
498 | |
| 499 | magnetometer@c { | |
| 9846210b | 500 | compatible = "ak,ak8975"; |
| 45dbe9dd OJ |
501 | reg = <0xc>; |
| 502 | interrupt-parent = <&gpio>; | |
| 503 | interrupts = <109 0x04>; /* gpio PN5 */ | |
| 504 | }; | |
| 88950f3b SW |
505 | }; |
| 506 | ||
| 6529e638 SW |
507 | pmc { |
| 508 | nvidia,invert-interrupt; | |
| 509 | }; | |
| 510 | ||
| bbfc33bd | 511 | memory-controller@7000f400 { |
| c04abb3a SW |
512 | emc-table@190000 { |
| 513 | reg = <190000>; | |
| 514 | compatible = "nvidia,tegra20-emc-table"; | |
| 515 | clock-frequency = <190000>; | |
| 516 | nvidia,emc-registers = <0x0000000c 0x00000026 | |
| 517 | 0x00000009 0x00000003 0x00000004 0x00000004 | |
| 518 | 0x00000002 0x0000000c 0x00000003 0x00000003 | |
| 519 | 0x00000002 0x00000001 0x00000004 0x00000005 | |
| 520 | 0x00000004 0x00000009 0x0000000d 0x0000059f | |
| 521 | 0x00000000 0x00000003 0x00000003 0x00000003 | |
| 522 | 0x00000003 0x00000001 0x0000000b 0x000000c8 | |
| 523 | 0x00000003 0x00000007 0x00000004 0x0000000f | |
| 524 | 0x00000002 0x00000000 0x00000000 0x00000002 | |
| 525 | 0x00000000 0x00000000 0x00000083 0xa06204ae | |
| 526 | 0x007dc010 0x00000000 0x00000000 0x00000000 | |
| 527 | 0x00000000 0x00000000 0x00000000 0x00000000>; | |
| 528 | }; | |
| 31c1ec92 | 529 | |
| c04abb3a SW |
530 | emc-table@380000 { |
| 531 | reg = <380000>; | |
| 532 | compatible = "nvidia,tegra20-emc-table"; | |
| 533 | clock-frequency = <380000>; | |
| 534 | nvidia,emc-registers = <0x00000017 0x0000004b | |
| 535 | 0x00000012 0x00000006 0x00000004 0x00000005 | |
| 536 | 0x00000003 0x0000000c 0x00000006 0x00000006 | |
| 537 | 0x00000003 0x00000001 0x00000004 0x00000005 | |
| 538 | 0x00000004 0x00000009 0x0000000d 0x00000b5f | |
| 539 | 0x00000000 0x00000003 0x00000003 0x00000006 | |
| 540 | 0x00000006 0x00000001 0x00000011 0x000000c8 | |
| 541 | 0x00000003 0x0000000e 0x00000007 0x0000000f | |
| 542 | 0x00000002 0x00000000 0x00000000 0x00000002 | |
| 543 | 0x00000000 0x00000000 0x00000083 0xe044048b | |
| 544 | 0x007d8010 0x00000000 0x00000000 0x00000000 | |
| 545 | 0x00000000 0x00000000 0x00000000 0x00000000>; | |
| 546 | }; | |
| 31c1ec92 SW |
547 | }; |
| 548 | ||
| c04abb3a | 549 | usb@c5000000 { |
| 2a5fdc9a | 550 | status = "okay"; |
| c04abb3a SW |
551 | nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ |
| 552 | dr_mode = "otg"; | |
| 8e267f3d GL |
553 | }; |
| 554 | ||
| c04abb3a | 555 | usb@c5004000 { |
| 2a5fdc9a | 556 | status = "okay"; |
| c04abb3a | 557 | nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ |
| 31c1ec92 SW |
558 | }; |
| 559 | ||
| 2a5fdc9a SW |
560 | usb@c5008000 { |
| 561 | status = "okay"; | |
| 1292c129 SW |
562 | }; |
| 563 | ||
| da2fc651 WN |
564 | sdhci@c8000000 { |
| 565 | status = "okay"; | |
| 566 | power-gpios = <&gpio 86 0>; /* gpio PK6 */ | |
| 567 | bus-width = <4>; | |
| 568 | }; | |
| 569 | ||
| 8e267f3d | 570 | sdhci@c8000400 { |
| 2a5fdc9a | 571 | status = "okay"; |
| a0638eb6 SW |
572 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ |
| 573 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | |
| 574 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ | |
| 7f217794 | 575 | bus-width = <4>; |
| 8e267f3d | 576 | }; |
| 6111d50c SW |
577 | |
| 578 | sdhci@c8000600 { | |
| 2a5fdc9a | 579 | status = "okay"; |
| 7f217794 | 580 | bus-width = <8>; |
| 6111d50c | 581 | }; |
| c27317c0 | 582 | |
| f0d14306 SW |
583 | gpio-keys { |
| 584 | compatible = "gpio-keys"; | |
| 585 | ||
| 586 | power { | |
| 587 | label = "Power"; | |
| 588 | gpios = <&gpio 170 1>; /* gpio PV2, active low */ | |
| 589 | linux,code = <116>; /* KEY_POWER */ | |
| 590 | gpio-key,wakeup; | |
| 591 | }; | |
| 592 | ||
| 593 | lid { | |
| 594 | label = "Lid"; | |
| 595 | gpios = <&gpio 23 0>; /* gpio PC7 */ | |
| 596 | linux,input-type = <5>; /* EV_SW */ | |
| 597 | linux,code = <0>; /* SW_LID */ | |
| 598 | debounce-interval = <1>; | |
| 599 | gpio-key,wakeup; | |
| 600 | }; | |
| 601 | }; | |
| d8017a97 | 602 | |
| 6529e638 SW |
603 | regulators { |
| 604 | compatible = "simple-bus"; | |
| 605 | #address-cells = <1>; | |
| 606 | #size-cells = <0>; | |
| 607 | ||
| 608 | vdd_5v0_reg: regulator@0 { | |
| 609 | compatible = "regulator-fixed"; | |
| 610 | reg = <0>; | |
| 611 | regulator-name = "vdd_5v0"; | |
| 612 | regulator-min-microvolt = <5000000>; | |
| 613 | regulator-max-microvolt = <5000000>; | |
| 614 | regulator-always-on; | |
| 615 | }; | |
| 616 | ||
| 617 | regulator@1 { | |
| 618 | compatible = "regulator-fixed"; | |
| 619 | reg = <1>; | |
| 620 | regulator-name = "vdd_1v5"; | |
| 621 | regulator-min-microvolt = <1500000>; | |
| 622 | regulator-max-microvolt = <1500000>; | |
| 623 | gpio = <&pmic 0 0>; | |
| 624 | }; | |
| 625 | ||
| 626 | regulator@2 { | |
| 627 | compatible = "regulator-fixed"; | |
| 628 | reg = <2>; | |
| 629 | regulator-name = "vdd_1v2"; | |
| 630 | regulator-min-microvolt = <1200000>; | |
| 631 | regulator-max-microvolt = <1200000>; | |
| 632 | gpio = <&pmic 1 0>; | |
| 633 | enable-active-high; | |
| 634 | }; | |
| 635 | }; | |
| 636 | ||
| c04abb3a SW |
637 | sound { |
| 638 | compatible = "nvidia,tegra-audio-wm8903-seaboard", | |
| 639 | "nvidia,tegra-audio-wm8903"; | |
| 640 | nvidia,model = "NVIDIA Tegra Seaboard"; | |
| d8017a97 | 641 | |
| c04abb3a SW |
642 | nvidia,audio-routing = |
| 643 | "Headphone Jack", "HPOUTR", | |
| 644 | "Headphone Jack", "HPOUTL", | |
| 645 | "Int Spk", "ROP", | |
| 646 | "Int Spk", "RON", | |
| 647 | "Int Spk", "LOP", | |
| 648 | "Int Spk", "LON", | |
| 649 | "Mic Jack", "MICBIAS", | |
| 650 | "IN1R", "Mic Jack"; | |
| aa607ebf | 651 | |
| c04abb3a SW |
652 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 653 | nvidia,audio-codec = <&wm8903>; | |
| 654 | ||
| 655 | nvidia,spkr-en-gpios = <&wm8903 2 0>; | |
| 656 | nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */ | |
| aa607ebf | 657 | }; |
| 8e267f3d | 658 | }; |