[deliverable/linux.git] / arch / arm / boot / dts / tegra20-tamonten.dtsi

#include "tegra20.dtsi"

/ {
	model = "Avionic Design Tamonten SOM";
	compatible = "ad,tamonten", "nvidia,tegra20";

	aliases {
		rtc0 = "/i2c@7000d000/tps6586x@34";
		rtc1 = "/rtc@7000e000";
		serial0 = &uartd;
	};

	memory {
		reg = <0x00000000 0x20000000>;
	};

	host1x@50000000 {
		hdmi@54280000 {
			vdd-supply = <&hdmi_vdd_reg>;
			pll-supply = <&hdmi_pll_reg>;

			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
				GPIO_ACTIVE_HIGH>;
		};
	};

	pinmux@70000014 {
		pinctrl-names = "default";
		pinctrl-0 = <&state_default>;

		state_default: pinmux {
			ata {
				nvidia,pins = "ata";
				nvidia,function = "ide";
			};
			atb {
				nvidia,pins = "atb", "gma", "gme";
				nvidia,function = "sdio4";
			};
			atc {
				nvidia,pins = "atc";
				nvidia,function = "nand";
			};
			atd {
				nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
					"spia", "spib", "spic";
				nvidia,function = "gmi";
			};
			cdev1 {
				nvidia,pins = "cdev1";
				nvidia,function = "plla_out";
			};
			cdev2 {
				nvidia,pins = "cdev2";
				nvidia,function = "pllp_out4";
			};
			crtp {
				nvidia,pins = "crtp";
				nvidia,function = "crt";
			};
			csus {
				nvidia,pins = "csus";
				nvidia,function = "vi_sensor_clk";
			};
			dap1 {
				nvidia,pins = "dap1";
				nvidia,function = "dap1";
			};
			dap2 {
				nvidia,pins = "dap2";
				nvidia,function = "dap2";
			};
			dap3 {
				nvidia,pins = "dap3";
				nvidia,function = "dap3";
			};
			dap4 {
				nvidia,pins = "dap4";
				nvidia,function = "dap4";
			};
			dta {
				nvidia,pins = "dta", "dtd";
				nvidia,function = "sdio2";
			};
			dtb {
				nvidia,pins = "dtb", "dtc", "dte";
				nvidia,function = "rsvd1";
			};
			dtf {
				nvidia,pins = "dtf";
				nvidia,function = "i2c3";
			};
			gmc {
				nvidia,pins = "gmc";
				nvidia,function = "uartd";
			};
			gpu7 {
				nvidia,pins = "gpu7";
				nvidia,function = "rtck";
			};
			gpv {
				nvidia,pins = "gpv", "slxa", "slxk";
				nvidia,function = "pcie";
			};
			hdint {
				nvidia,pins = "hdint";
				nvidia,function = "hdmi";
			};
			i2cp {
				nvidia,pins = "i2cp";
				nvidia,function = "i2cp";
			};
			irrx {
				nvidia,pins = "irrx", "irtx";
				nvidia,function = "uarta";
			};
			kbca {
				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
					"kbce", "kbcf";
				nvidia,function = "kbc";
			};
			lcsn {
				nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
					"ld3", "ld4", "ld5", "ld6", "ld7",
					"ld8", "ld9", "ld10", "ld11", "ld12",
					"ld13", "ld14", "ld15", "ld16", "ld17",
					"ldc", "ldi", "lhp0", "lhp1", "lhp2",
					"lhs", "lm0", "lm1", "lpp", "lpw0",
					"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
					"lsda", "lsdi", "lspi", "lvp0", "lvp1",
					"lvs";
				nvidia,function = "displaya";
			};
			owc {
				nvidia,pins = "owc", "spdi", "spdo", "uac";
				nvidia,function = "rsvd2";
			};
			pmc {
				nvidia,pins = "pmc";
				nvidia,function = "pwr_on";
			};
			rm {
				nvidia,pins = "rm";
				nvidia,function = "i2c1";
			};
			sdb {
				nvidia,pins = "sdb", "sdc", "sdd";
				nvidia,function = "pwm";
			};
			sdio1 {
				nvidia,pins = "sdio1";
				nvidia,function = "sdio1";
			};
			slxc {
				nvidia,pins = "slxc", "slxd";
				nvidia,function = "spdif";
			};
			spid {
				nvidia,pins = "spid", "spie", "spif";
				nvidia,function = "spi1";
			};
			spig {
				nvidia,pins = "spig", "spih";
				nvidia,function = "spi2_alt";
			};
			uaa {
				nvidia,pins = "uaa", "uab", "uda";
				nvidia,function = "ulpi";
			};
			uad {
				nvidia,pins = "uad";
				nvidia,function = "irda";
			};
			uca {
				nvidia,pins = "uca", "ucb";
				nvidia,function = "uartc";
			};
			conf_ata {
				nvidia,pins = "ata", "atb", "atc", "atd", "ate",
					"cdev1", "cdev2", "dap1", "dtb", "gma",
					"gmb", "gmc", "gmd", "gme", "gpu7",
					"gpv", "i2cp", "pta", "rm", "slxa",
					"slxk", "spia", "spib", "uac";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			conf_ck32 {
				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			};
			conf_csus {
				nvidia,pins = "csus", "spid", "spif";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			conf_crtp {
				nvidia,pins = "crtp", "dap2", "dap3", "dap4",
					"dtc", "dte", "dtf", "gpu", "sdio1",
					"slxc", "slxd", "spdi", "spdo", "spig",
					"uda";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			conf_ddc {
				nvidia,pins = "ddc", "dta", "dtd", "kbca",
					"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
					"sdc";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			conf_hdint {
				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
					"lpw1", "lsc1", "lsck", "lsda", "lsdi",
					"lvp0", "owc", "sdb";
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			conf_irrx {
				nvidia,pins = "irrx", "irtx", "sdd", "spic",
					"spie", "spih", "uaa", "uab", "uad",
					"uca", "ucb";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			conf_lc {
				nvidia,pins = "lc", "ls";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
			};
			conf_ld0 {
				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
					"ld5", "ld6", "ld7", "ld8", "ld9",
					"ld10", "ld11", "ld12", "ld13", "ld14",
					"ld15", "ld16", "ld17", "ldi", "lhp0",
					"lhp1", "lhp2", "lhs", "lm0", "lpp",
					"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
					"lvs", "pmc";
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			conf_ld17_0 {
				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
					"ld23_22";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			};
		};

		state_i2cmux_ddc: pinmux_i2cmux_ddc {
			ddc {
				nvidia,pins = "ddc";
				nvidia,function = "i2c2";
			};
			pta {
				nvidia,pins = "pta";
				nvidia,function = "rsvd4";
			};
		};

		state_i2cmux_pta: pinmux_i2cmux_pta {
			ddc {
				nvidia,pins = "ddc";
				nvidia,function = "rsvd4";
			};
			pta {
				nvidia,pins = "pta";
				nvidia,function = "i2c2";
			};
		};

		state_i2cmux_idle: pinmux_i2cmux_idle {
			ddc {
				nvidia,pins = "ddc";
				nvidia,function = "rsvd4";
			};
			pta {
				nvidia,pins = "pta";
				nvidia,function = "rsvd4";
			};
		};
	};

	i2s@70002800 {
		status = "okay";
	};

	serial@70006300 {
		status = "okay";
	};

	i2c@7000c000 {
		clock-frequency = <400000>;
		status = "okay";
	};

	i2c@7000c400 {
		clock-frequency = <100000>;
		status = "okay";
	};

	i2cmux {
		compatible = "i2c-mux-pinctrl";
		#address-cells = <1>;
		#size-cells = <0>;

		i2c-parent = <&{/i2c@7000c400}>;

		pinctrl-names = "ddc", "pta", "idle";
		pinctrl-0 = <&state_i2cmux_ddc>;
		pinctrl-1 = <&state_i2cmux_pta>;
		pinctrl-2 = <&state_i2cmux_idle>;

		hdmi_ddc: i2c@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	i2c@7000d000 {
		clock-frequency = <400000>;
		status = "okay";

		pmic: tps6586x@34 {
			compatible = "ti,tps6586x";
			reg = <0x34>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

			ti,system-power-controller;

			#gpio-cells = <2>;
			gpio-controller;

			/* vdd_5v0_reg must be provided by the base board */
			sys-supply = <&vdd_5v0_reg>;
			vin-sm0-supply = <&sys_reg>;
			vin-sm1-supply = <&sys_reg>;
			vin-sm2-supply = <&sys_reg>;
			vinldo01-supply = <&sm2_reg>;
			vinldo23-supply = <&sm2_reg>;
			vinldo4-supply = <&sm2_reg>;
			vinldo678-supply = <&sm2_reg>;
			vinldo9-supply = <&sm2_reg>;

			regulators {
				sys_reg: sys {
					regulator-name = "vdd_sys";
					regulator-always-on;
				};

				sm0 {
					regulator-name = "vdd_sys_sm0,vdd_core";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
				};

				sm1 {
					regulator-name = "vdd_sys_sm1,vdd_cpu";
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1000000>;
					regulator-always-on;
				};

				sm2_reg: sm2 {
					regulator-name = "vdd_sys_sm2,vin_ldo*";
					regulator-min-microvolt = <3700000>;
					regulator-max-microvolt = <3700000>;
					regulator-always-on;
				};

				pci_clk_reg: ldo0 {
					regulator-name = "vdd_ldo0,vddio_pex_clk";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
				};

				ldo1 {
					regulator-name = "vdd_ldo1,avdd_pll*";
					regulator-min-microvolt = <1100000>;
					regulator-max-microvolt = <1100000>;
					regulator-always-on;
				};

				ldo2 {
					regulator-name = "vdd_ldo2,vdd_rtc";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
				};

				ldo3 {
					regulator-name = "vdd_ldo3,avdd_usb*";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
				};

				ldo4 {
					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
				};

				ldo5 {
					regulator-name = "vdd_ldo5,vcore_mmc";
					regulator-min-microvolt = <2850000>;
					regulator-max-microvolt = <2850000>;
				};

				ldo6 {
					regulator-name = "vdd_ldo6,avdd_vdac";
					/*
					 * According to the Tegra 2 Automotive
					 * DataSheet, a typical value for this
					 * would be 2.8V, but the PMIC only
					 * supports 2.85V.
					 */
					regulator-min-microvolt = <2850000>;
					regulator-max-microvolt = <2850000>;
				};

				hdmi_vdd_reg: ldo7 {
					regulator-name = "vdd_ldo7,avdd_hdmi";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
				};

				hdmi_pll_reg: ldo8 {
					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
				};

				ldo9 {
					regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
					/*
					 * According to the Tegra 2 Automotive
					 * DataSheet, a typical value for this
					 * would be 2.8V, but the PMIC only
					 * supports 2.85V.
					 */
					regulator-min-microvolt = <2850000>;
					regulator-max-microvolt = <2850000>;
					regulator-always-on;
				};

				ldo_rtc {
					regulator-name = "vdd_rtc_out";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
				};
			};
		};

		temperature-sensor@4c {
			compatible = "onnn,nct1008";
			reg = <0x4c>;
		};
	};

	pmc@7000e400 {
		nvidia,invert-interrupt;
		nvidia,suspend-mode = <1>;
		nvidia,cpu-pwr-good-time = <5000>;
		nvidia,cpu-pwr-off-time = <5000>;
		nvidia,core-pwr-good-time = <3845 3845>;
		nvidia,core-pwr-off-time = <3875>;
		nvidia,sys-clock-req-active-high;
	};

	pcie-controller@80003000 {
		avdd-pex-supply = <&pci_vdd_reg>;
		vdd-pex-supply = <&pci_vdd_reg>;
		avdd-pex-pll-supply = <&pci_vdd_reg>;
		avdd-plle-supply = <&pci_vdd_reg>;
		vddio-pex-clk-supply = <&pci_clk_reg>;
	};

	usb@c5008000 {
		status = "okay";
	};

	usb-phy@c5008000 {
		status = "okay";
	};

	sdhci@c8000600 {
		cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
		wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
		bus-width = <4>;
		status = "okay";
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		clk32k_in: clock@0 {
			compatible = "fixed-clock";
			reg=<0>;
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	regulators {
		compatible = "simple-bus";

		#address-cells = <1>;
		#size-cells = <0>;

		pci_vdd_reg: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "vdd_1v05";
			regulator-min-microvolt = <1050000>;
			regulator-max-microvolt = <1050000>;
			gpio = <&pmic 2 0>;
			enable-active-high;
		};
	};
};
Commit	Line	Data
1bd0bd49	1	#include "tegra20.dtsi"
307e28ee TR	2
	3	/ {
	4	model = "Avionic Design Tamonten SOM";
	5	compatible = "ad,tamonten", "nvidia,tegra20";
	6
553c0a20 SW	7	aliases {
	8	rtc0 = "/i2c@7000d000/tps6586x@34";
	9	rtc1 = "/rtc@7000e000";
c4574aa0	10	serial0 = &uartd;
553c0a20 SW	11	};
553c0a20 SW	12
307e28ee TR	13	memory {
	14	reg = <0x00000000 0x20000000>;
	15	};
	16
58ecb23f SW	17	host1x@50000000 {
58ecb23f SW	18	hdmi@54280000 {
e6f09796 TR	19	vdd-supply = <&hdmi_vdd_reg>;
	20	pll-supply = <&hdmi_pll_reg>;
	21
	22	nvidia,ddc-i2c-bus = <&hdmi_ddc>;
3325f1bc SW	23	nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
3325f1bc SW	24	GPIO_ACTIVE_HIGH>;
e6f09796 TR	25	};
	26	};
	27
58ecb23f	28	pinmux@70000014 {
307e28ee TR	29	pinctrl-names = "default";
	30	pinctrl-0 = <&state_default>;
	31
	32	state_default: pinmux {
	33	ata {
	34	nvidia,pins = "ata";
	35	nvidia,function = "ide";
	36	};
	37	atb {
	38	nvidia,pins = "atb", "gma", "gme";
	39	nvidia,function = "sdio4";
	40	};
	41	atc {
	42	nvidia,pins = "atc";
	43	nvidia,function = "nand";
	44	};
	45	atd {
	46	nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
	47	"spia", "spib", "spic";
	48	nvidia,function = "gmi";
	49	};
	50	cdev1 {
	51	nvidia,pins = "cdev1";
	52	nvidia,function = "plla_out";
	53	};
	54	cdev2 {
	55	nvidia,pins = "cdev2";
	56	nvidia,function = "pllp_out4";
	57	};
	58	crtp {
	59	nvidia,pins = "crtp";
	60	nvidia,function = "crt";
	61	};
	62	csus {
	63	nvidia,pins = "csus";
	64	nvidia,function = "vi_sensor_clk";
	65	};
	66	dap1 {
	67	nvidia,pins = "dap1";
	68	nvidia,function = "dap1";
	69	};
	70	dap2 {
	71	nvidia,pins = "dap2";
	72	nvidia,function = "dap2";
	73	};
	74	dap3 {
	75	nvidia,pins = "dap3";
	76	nvidia,function = "dap3";
	77	};
	78	dap4 {
	79	nvidia,pins = "dap4";
	80	nvidia,function = "dap4";
	81	};
307e28ee TR	82	dta {
	83	nvidia,pins = "dta", "dtd";
	84	nvidia,function = "sdio2";
	85	};
	86	dtb {
	87	nvidia,pins = "dtb", "dtc", "dte";
	88	nvidia,function = "rsvd1";
	89	};
	90	dtf {
	91	nvidia,pins = "dtf";
	92	nvidia,function = "i2c3";
	93	};
	94	gmc {
	95	nvidia,pins = "gmc";
	96	nvidia,function = "uartd";
	97	};
	98	gpu7 {
	99	nvidia,pins = "gpu7";
	100	nvidia,function = "rtck";
	101	};
	102	gpv {
	103	nvidia,pins = "gpv", "slxa", "slxk";
	104	nvidia,function = "pcie";
	105	};
	106	hdint {
ec319903	107	nvidia,pins = "hdint";
307e28ee TR	108	nvidia,function = "hdmi";
	109	};
	110	i2cp {
	111	nvidia,pins = "i2cp";
	112	nvidia,function = "i2cp";
	113	};
	114	irrx {
	115	nvidia,pins = "irrx", "irtx";
	116	nvidia,function = "uarta";
	117	};
	118	kbca {
	119	nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
	120	"kbce", "kbcf";
	121	nvidia,function = "kbc";
	122	};
	123	lcsn {
	124	nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
	125	"ld3", "ld4", "ld5", "ld6", "ld7",
	126	"ld8", "ld9", "ld10", "ld11", "ld12",
	127	"ld13", "ld14", "ld15", "ld16", "ld17",
	128	"ldc", "ldi", "lhp0", "lhp1", "lhp2",
	129	"lhs", "lm0", "lm1", "lpp", "lpw0",
	130	"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
	131	"lsda", "lsdi", "lspi", "lvp0", "lvp1",
	132	"lvs";
	133	nvidia,function = "displaya";
	134	};
	135	owc {
	136	nvidia,pins = "owc", "spdi", "spdo", "uac";
	137	nvidia,function = "rsvd2";
	138	};
	139	pmc {
	140	nvidia,pins = "pmc";
	141	nvidia,function = "pwr_on";
	142	};
	143	rm {
	144	nvidia,pins = "rm";
	145	nvidia,function = "i2c1";
	146	};
	147	sdb {
	148	nvidia,pins = "sdb", "sdc", "sdd";
	149	nvidia,function = "pwm";
	150	};
	151	sdio1 {
	152	nvidia,pins = "sdio1";
	153	nvidia,function = "sdio1";
	154	};
	155	slxc {
	156	nvidia,pins = "slxc", "slxd";
	157	nvidia,function = "spdif";
	158	};
	159	spid {
	160	nvidia,pins = "spid", "spie", "spif";
	161	nvidia,function = "spi1";
	162	};
	163	spig {
	164	nvidia,pins = "spig", "spih";
	165	nvidia,function = "spi2_alt";
	166	};
	167	uaa {
	168	nvidia,pins = "uaa", "uab", "uda";
	169	nvidia,function = "ulpi";
	170	};
	171	uad {
172	nvidia,pins = "uad";
173	nvidia,function = "irda";
174	};
175	uca {
176	nvidia,pins = "uca", "ucb";
177	nvidia,function = "uartc";
178	};
179	conf_ata {
180	nvidia,pins = "ata", "atb", "atc", "atd", "ate",
181	"cdev1", "cdev2", "dap1", "dtb", "gma",
182	"gmb", "gmc", "gmd", "gme", "gpu7",
183	"gpv", "i2cp", "pta", "rm", "slxa",
184	"slxk", "spia", "spib", "uac";
ba4104e7 LD	185	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	186	nvidia,tristate = <TEGRA_PIN_DISABLE>;
307e28ee TR	187	};
	188	conf_ck32 {
	189	nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
	190	"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
ba4104e7	191	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
307e28ee TR	192	};
	193	conf_csus {
	194	nvidia,pins = "csus", "spid", "spif";
ba4104e7 LD	195	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
ba4104e7 LD	196	nvidia,tristate = <TEGRA_PIN_ENABLE>;
307e28ee TR	197	};
	198	conf_crtp {
	199	nvidia,pins = "crtp", "dap2", "dap3", "dap4",
	200	"dtc", "dte", "dtf", "gpu", "sdio1",
	201	"slxc", "slxd", "spdi", "spdo", "spig",
	202	"uda";
ba4104e7 LD	203	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ba4104e7 LD	204	nvidia,tristate = <TEGRA_PIN_ENABLE>;
307e28ee TR	205	};
	206	conf_ddc {
	207	nvidia,pins = "ddc", "dta", "dtd", "kbca",
	208	"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
	209	"sdc";
ba4104e7 LD	210	nvidia,pull = <TEGRA_PIN_PULL_UP>;
ba4104e7 LD	211	nvidia,tristate = <TEGRA_PIN_DISABLE>;
307e28ee TR	212	};
	213	conf_hdint {
	214	nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
	215	"lpw1", "lsc1", "lsck", "lsda", "lsdi",
	216	"lvp0", "owc", "sdb";
ba4104e7	217	nvidia,tristate = <TEGRA_PIN_ENABLE>;
307e28ee TR	218	};
	219	conf_irrx {
	220	nvidia,pins = "irrx", "irtx", "sdd", "spic",
	221	"spie", "spih", "uaa", "uab", "uad",
	222	"uca", "ucb";
ba4104e7 LD	223	nvidia,pull = <TEGRA_PIN_PULL_UP>;
ba4104e7 LD	224	nvidia,tristate = <TEGRA_PIN_ENABLE>;
307e28ee TR	225	};
	226	conf_lc {
	227	nvidia,pins = "lc", "ls";
ba4104e7	228	nvidia,pull = <TEGRA_PIN_PULL_UP>;
307e28ee TR	229	};
	230	conf_ld0 {
	231	nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
	232	"ld5", "ld6", "ld7", "ld8", "ld9",
	233	"ld10", "ld11", "ld12", "ld13", "ld14",
	234	"ld15", "ld16", "ld17", "ldi", "lhp0",
	235	"lhp1", "lhp2", "lhs", "lm0", "lpp",
	236	"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
	237	"lvs", "pmc";
ba4104e7	238	nvidia,tristate = <TEGRA_PIN_DISABLE>;
307e28ee TR	239	};
	240	conf_ld17_0 {
	241	nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
	242	"ld23_22";
ba4104e7	243	nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
307e28ee TR	244	};
307e28ee TR	245	};
ec319903 TR	246
	247	state_i2cmux_ddc: pinmux_i2cmux_ddc {
	248	ddc {
	249	nvidia,pins = "ddc";
	250	nvidia,function = "i2c2";
	251	};
	252	pta {
	253	nvidia,pins = "pta";
	254	nvidia,function = "rsvd4";
	255	};
	256	};
	257
	258	state_i2cmux_pta: pinmux_i2cmux_pta {
	259	ddc {
	260	nvidia,pins = "ddc";
	261	nvidia,function = "rsvd4";
	262	};
	263	pta {
	264	nvidia,pins = "pta";
	265	nvidia,function = "i2c2";
	266	};
	267	};
	268
	269	state_i2cmux_idle: pinmux_i2cmux_idle {
	270	ddc {
	271	nvidia,pins = "ddc";
	272	nvidia,function = "rsvd4";
	273	};
	274	pta {
	275	nvidia,pins = "pta";
	276	nvidia,function = "rsvd4";
	277	};
	278	};
307e28ee TR	279	};
	280
	281	i2s@70002800 {
	282	status = "okay";
	283	};
	284
	285	serial@70006300 {
307e28ee TR	286	status = "okay";
	287	};
	288
	289	i2c@7000c000 {
	290	clock-frequency = <400000>;
	291	status = "okay";
	292	};
	293
ec319903 TR	294	i2c@7000c400 {
	295	clock-frequency = <100000>;
	296	status = "okay";
	297	};
	298
	299	i2cmux {
	300	compatible = "i2c-mux-pinctrl";
	301	#address-cells = <1>;
	302	#size-cells = <0>;
	303
	304	i2c-parent = <&{/i2c@7000c400}>;
	305
	306	pinctrl-names = "ddc", "pta", "idle";
	307	pinctrl-0 = <&state_i2cmux_ddc>;
	308	pinctrl-1 = <&state_i2cmux_pta>;
	309	pinctrl-2 = <&state_i2cmux_idle>;
	310
e6f09796	311	hdmi_ddc: i2c@0 {
ec319903 TR	312	reg = <0>;
	313	#address-cells = <1>;
	314	#size-cells = <0>;
	315	};
	316
	317	i2c@1 {
	318	reg = <1>;
	319	#address-cells = <1>;
	320	#size-cells = <0>;
	321	};
	322	};
	323
307e28ee TR	324	i2c@7000d000 {
	325	clock-frequency = <400000>;
	326	status = "okay";
	327
	328	pmic: tps6586x@34 {
	329	compatible = "ti,tps6586x";
	330	reg = <0x34>;
6cecf916	331	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
307e28ee TR	332
	333	ti,system-power-controller;
	334
	335	#gpio-cells = <2>;
	336	gpio-controller;
	337
23e63345	338	/* vdd_5v0_reg must be provided by the base board */
307e28ee TR	339	sys-supply = <&vdd_5v0_reg>;
	340	vin-sm0-supply = <&sys_reg>;
	341	vin-sm1-supply = <&sys_reg>;
	342	vin-sm2-supply = <&sys_reg>;
	343	vinldo01-supply = <&sm2_reg>;
	344	vinldo23-supply = <&sm2_reg>;
	345	vinldo4-supply = <&sm2_reg>;
	346	vinldo678-supply = <&sm2_reg>;
	347	vinldo9-supply = <&sm2_reg>;
	348
	349	regulators {
b9c665d7	350	sys_reg: sys {
307e28ee TR	351	regulator-name = "vdd_sys";
	352	regulator-always-on;
	353	};
	354
b9c665d7	355	sm0 {
307e28ee TR	356	regulator-name = "vdd_sys_sm0,vdd_core";
	357	regulator-min-microvolt = <1200000>;
	358	regulator-max-microvolt = <1200000>;
	359	regulator-always-on;
	360	};
	361
b9c665d7	362	sm1 {
307e28ee TR	363	regulator-name = "vdd_sys_sm1,vdd_cpu";
	364	regulator-min-microvolt = <1000000>;
	365	regulator-max-microvolt = <1000000>;
	366	regulator-always-on;
	367	};
	368
b9c665d7	369	sm2_reg: sm2 {
307e28ee TR	370	regulator-name = "vdd_sys_sm2,vin_ldo*";
	371	regulator-min-microvolt = <3700000>;
	372	regulator-max-microvolt = <3700000>;
	373	regulator-always-on;
	374	};
	375
1b2d6b84	376	pci_clk_reg: ldo0 {
307e28ee TR	377	regulator-name = "vdd_ldo0,vddio_pex_clk";
	378	regulator-min-microvolt = <3300000>;
	379	regulator-max-microvolt = <3300000>;
	380	};
	381
b9c665d7	382	ldo1 {
307e28ee TR	383	regulator-name = "vdd_ldo1,avdd_pll*";
	384	regulator-min-microvolt = <1100000>;
	385	regulator-max-microvolt = <1100000>;
	386	regulator-always-on;
	387	};
	388
b9c665d7	389	ldo2 {
307e28ee TR	390	regulator-name = "vdd_ldo2,vdd_rtc";
	391	regulator-min-microvolt = <1200000>;
	392	regulator-max-microvolt = <1200000>;
	393	};
	394
b9c665d7	395	ldo3 {
307e28ee TR	396	regulator-name = "vdd_ldo3,avdd_usb*";
	397	regulator-min-microvolt = <3300000>;
	398	regulator-max-microvolt = <3300000>;
	399	regulator-always-on;
	400	};
	401
b9c665d7	402	ldo4 {
307e28ee TR	403	regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
	404	regulator-min-microvolt = <1800000>;
	405	regulator-max-microvolt = <1800000>;
	406	regulator-always-on;
	407	};
	408
b9c665d7	409	ldo5 {
307e28ee TR	410	regulator-name = "vdd_ldo5,vcore_mmc";
	411	regulator-min-microvolt = <2850000>;
	412	regulator-max-microvolt = <2850000>;
	413	};
	414
b9c665d7	415	ldo6 {
307e28ee TR	416	regulator-name = "vdd_ldo6,avdd_vdac";
	417	/*
	418	* According to the Tegra 2 Automotive
	419	* DataSheet, a typical value for this
	420	* would be 2.8V, but the PMIC only
	421	* supports 2.85V.
	422	*/
	423	regulator-min-microvolt = <2850000>;
	424	regulator-max-microvolt = <2850000>;
	425	};
	426
e6f09796	427	hdmi_vdd_reg: ldo7 {
307e28ee TR	428	regulator-name = "vdd_ldo7,avdd_hdmi";
	429	regulator-min-microvolt = <3300000>;
	430	regulator-max-microvolt = <3300000>;
	431	};
	432
e6f09796	433	hdmi_pll_reg: ldo8 {
307e28ee TR	434	regulator-name = "vdd_ldo8,avdd_hdmi_pll";
	435	regulator-min-microvolt = <1800000>;
	436	regulator-max-microvolt = <1800000>;
	437	};
	438
b9c665d7	439	ldo9 {
307e28ee TR	440	regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
	441	/*
	442	* According to the Tegra 2 Automotive
	443	* DataSheet, a typical value for this
	444	* would be 2.8V, but the PMIC only
	445	* supports 2.85V.
	446	*/
	447	regulator-min-microvolt = <2850000>;
	448	regulator-max-microvolt = <2850000>;
	449	regulator-always-on;
	450	};
	451
b9c665d7	452	ldo_rtc {
307e28ee TR	453	regulator-name = "vdd_rtc_out";
	454	regulator-min-microvolt = <3300000>;
	455	regulator-max-microvolt = <3300000>;
	456	regulator-always-on;
	457	};
	458	};
	459	};
840a4080 TR	460
	461	temperature-sensor@4c {
	462	compatible = "onnn,nct1008";
	463	reg = <0x4c>;
	464	};
307e28ee TR	465	};
307e28ee TR	466
58ecb23f	467	pmc@7000e400 {
307e28ee	468	nvidia,invert-interrupt;
47d2d63b	469	nvidia,suspend-mode = <1>;
a44a019d JL	470	nvidia,cpu-pwr-good-time = <5000>;
	471	nvidia,cpu-pwr-off-time = <5000>;
	472	nvidia,core-pwr-good-time = <3845 3845>;
	473	nvidia,core-pwr-off-time = <3875>;
	474	nvidia,sys-clock-req-active-high;
307e28ee TR	475	};
307e28ee TR	476
58ecb23f	477	pcie-controller@80003000 {
cca8614d TR	478	avdd-pex-supply = <&pci_vdd_reg>;
	479	vdd-pex-supply = <&pci_vdd_reg>;
	480	avdd-pex-pll-supply = <&pci_vdd_reg>;
	481	avdd-plle-supply = <&pci_vdd_reg>;
	482	vddio-pex-clk-supply = <&pci_clk_reg>;
1b2d6b84 TR	483	};
1b2d6b84 TR	484
307e28ee TR	485	usb@c5008000 {
	486	status = "okay";
	487	};
	488
4c94c8b5 VB	489	usb-phy@c5008000 {
	490	status = "okay";
	491	};
	492
307e28ee	493	sdhci@c8000600 {
3325f1bc SW	494	cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
3325f1bc SW	495	wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
307e28ee TR	496	bus-width = <4>;
	497	status = "okay";
	498	};
	499
7021d122 JL	500	clocks {
	501	compatible = "simple-bus";
	502	#address-cells = <1>;
	503	#size-cells = <0>;
	504
58ecb23f	505	clk32k_in: clock@0 {
7021d122 JL	506	compatible = "fixed-clock";
	507	reg=<0>;
	508	#clock-cells = <0>;
	509	clock-frequency = <32768>;
	510	};
	511	};
	512
307e28ee TR	513	regulators {
	514	compatible = "simple-bus";
	515
	516	#address-cells = <1>;
	517	#size-cells = <0>;
	518
1b2d6b84 TR	519	pci_vdd_reg: regulator@1 {
	520	compatible = "regulator-fixed";
	521	reg = <1>;
	522	regulator-name = "vdd_1v05";
	523	regulator-min-microvolt = <1050000>;
	524	regulator-max-microvolt = <1050000>;
	525	gpio = <&pmic 2 0>;
	526	enable-active-high;
	527	};
307e28ee TR	528	};
307e28ee TR	529	};