Commit | Line | Data |
---|---|---|
add29e61 PDS |
1 | /dts-v1/; |
2 | ||
1bd0bd49 | 3 | #include "tegra20.dtsi" |
add29e61 PDS |
4 | |
5 | / { | |
8fef5dff | 6 | model = "NVIDIA Tegra20 Ventana evaluation board"; |
add29e61 PDS |
7 | compatible = "nvidia,ventana", "nvidia,tegra20"; |
8 | ||
add29e61 | 9 | memory { |
95decf84 | 10 | reg = <0x00000000 0x40000000>; |
add29e61 PDS |
11 | }; |
12 | ||
97d5520f SW |
13 | host1x { |
14 | hdmi { | |
15 | status = "okay"; | |
16 | ||
17 | vdd-supply = <&hdmi_vdd_reg>; | |
18 | pll-supply = <&hdmi_pll_reg>; | |
19 | ||
20 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
3325f1bc SW |
21 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
22 | GPIO_ACTIVE_HIGH>; | |
97d5520f SW |
23 | }; |
24 | }; | |
25 | ||
f9eb26a4 | 26 | pinmux { |
ecc295bb SW |
27 | pinctrl-names = "default"; |
28 | pinctrl-0 = <&state_default>; | |
29 | ||
30 | state_default: pinmux { | |
31 | ata { | |
32 | nvidia,pins = "ata"; | |
33 | nvidia,function = "ide"; | |
34 | }; | |
35 | atb { | |
36 | nvidia,pins = "atb", "gma", "gme"; | |
37 | nvidia,function = "sdio4"; | |
38 | }; | |
39 | atc { | |
40 | nvidia,pins = "atc"; | |
41 | nvidia,function = "nand"; | |
42 | }; | |
43 | atd { | |
44 | nvidia,pins = "atd", "ate", "gmb", "spia", | |
45 | "spib", "spic"; | |
46 | nvidia,function = "gmi"; | |
47 | }; | |
48 | cdev1 { | |
49 | nvidia,pins = "cdev1"; | |
50 | nvidia,function = "plla_out"; | |
51 | }; | |
52 | cdev2 { | |
53 | nvidia,pins = "cdev2"; | |
54 | nvidia,function = "pllp_out4"; | |
55 | }; | |
56 | crtp { | |
57 | nvidia,pins = "crtp", "lm1"; | |
58 | nvidia,function = "crt"; | |
59 | }; | |
60 | csus { | |
61 | nvidia,pins = "csus"; | |
62 | nvidia,function = "vi_sensor_clk"; | |
63 | }; | |
64 | dap1 { | |
65 | nvidia,pins = "dap1"; | |
66 | nvidia,function = "dap1"; | |
67 | }; | |
68 | dap2 { | |
69 | nvidia,pins = "dap2"; | |
70 | nvidia,function = "dap2"; | |
71 | }; | |
72 | dap3 { | |
73 | nvidia,pins = "dap3"; | |
74 | nvidia,function = "dap3"; | |
75 | }; | |
76 | dap4 { | |
77 | nvidia,pins = "dap4"; | |
78 | nvidia,function = "dap4"; | |
79 | }; | |
ecc295bb SW |
80 | dta { |
81 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; | |
82 | nvidia,function = "vi"; | |
83 | }; | |
84 | dtf { | |
85 | nvidia,pins = "dtf"; | |
86 | nvidia,function = "i2c3"; | |
87 | }; | |
88 | gmc { | |
89 | nvidia,pins = "gmc"; | |
90 | nvidia,function = "uartd"; | |
91 | }; | |
92 | gmd { | |
93 | nvidia,pins = "gmd"; | |
94 | nvidia,function = "sflash"; | |
95 | }; | |
96 | gpu { | |
97 | nvidia,pins = "gpu"; | |
98 | nvidia,function = "pwm"; | |
99 | }; | |
100 | gpu7 { | |
101 | nvidia,pins = "gpu7"; | |
102 | nvidia,function = "rtck"; | |
103 | }; | |
104 | gpv { | |
105 | nvidia,pins = "gpv", "slxa", "slxk"; | |
106 | nvidia,function = "pcie"; | |
107 | }; | |
108 | hdint { | |
cf633464 | 109 | nvidia,pins = "hdint"; |
ecc295bb SW |
110 | nvidia,function = "hdmi"; |
111 | }; | |
112 | i2cp { | |
113 | nvidia,pins = "i2cp"; | |
114 | nvidia,function = "i2cp"; | |
115 | }; | |
116 | irrx { | |
117 | nvidia,pins = "irrx", "irtx"; | |
118 | nvidia,function = "uartb"; | |
119 | }; | |
120 | kbca { | |
121 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
122 | "kbce", "kbcf"; | |
123 | nvidia,function = "kbc"; | |
124 | }; | |
125 | lcsn { | |
126 | nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", | |
127 | "lsdi", "lvp0"; | |
128 | nvidia,function = "rsvd4"; | |
129 | }; | |
130 | ld0 { | |
131 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
132 | "ld5", "ld6", "ld7", "ld8", "ld9", | |
133 | "ld10", "ld11", "ld12", "ld13", "ld14", | |
134 | "ld15", "ld16", "ld17", "ldi", "lhp0", | |
135 | "lhp1", "lhp2", "lhs", "lpp", "lpw0", | |
136 | "lpw2", "lsc0", "lsc1", "lsck", "lsda", | |
137 | "lspi", "lvp1", "lvs"; | |
138 | nvidia,function = "displaya"; | |
139 | }; | |
cf633464 MZ |
140 | owc { |
141 | nvidia,pins = "owc", "spdi", "spdo", "uac"; | |
142 | nvidia,function = "rsvd2"; | |
143 | }; | |
ecc295bb SW |
144 | pmc { |
145 | nvidia,pins = "pmc"; | |
146 | nvidia,function = "pwr_on"; | |
147 | }; | |
148 | rm { | |
149 | nvidia,pins = "rm"; | |
150 | nvidia,function = "i2c1"; | |
151 | }; | |
152 | sdb { | |
153 | nvidia,pins = "sdb", "sdc", "sdd", "slxc"; | |
154 | nvidia,function = "sdio3"; | |
155 | }; | |
156 | sdio1 { | |
157 | nvidia,pins = "sdio1"; | |
158 | nvidia,function = "sdio1"; | |
159 | }; | |
160 | slxd { | |
161 | nvidia,pins = "slxd"; | |
162 | nvidia,function = "spdif"; | |
163 | }; | |
164 | spid { | |
165 | nvidia,pins = "spid", "spie", "spif"; | |
166 | nvidia,function = "spi1"; | |
167 | }; | |
168 | spig { | |
169 | nvidia,pins = "spig", "spih"; | |
170 | nvidia,function = "spi2_alt"; | |
171 | }; | |
172 | uaa { | |
173 | nvidia,pins = "uaa", "uab", "uda"; | |
174 | nvidia,function = "ulpi"; | |
175 | }; | |
176 | uad { | |
177 | nvidia,pins = "uad"; | |
178 | nvidia,function = "irda"; | |
179 | }; | |
180 | uca { | |
181 | nvidia,pins = "uca", "ucb"; | |
182 | nvidia,function = "uartc"; | |
183 | }; | |
184 | conf_ata { | |
185 | nvidia,pins = "ata", "atb", "atc", "atd", | |
186 | "cdev1", "cdev2", "dap1", "dap2", | |
187 | "dap4", "ddc", "dtf", "gma", "gmc", | |
188 | "gme", "gpu", "gpu7", "i2cp", "irrx", | |
189 | "irtx", "pta", "rm", "sdc", "sdd", | |
190 | "slxc", "slxd", "slxk", "spdi", "spdo", | |
191 | "uac", "uad", "uca", "ucb", "uda"; | |
192 | nvidia,pull = <0>; | |
193 | nvidia,tristate = <0>; | |
194 | }; | |
195 | conf_ate { | |
196 | nvidia,pins = "ate", "csus", "dap3", "gmd", | |
197 | "gpv", "owc", "spia", "spib", "spic", | |
198 | "spid", "spie", "spig"; | |
199 | nvidia,pull = <0>; | |
200 | nvidia,tristate = <1>; | |
201 | }; | |
202 | conf_ck32 { | |
203 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | |
204 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | |
205 | nvidia,pull = <0>; | |
206 | }; | |
207 | conf_crtp { | |
208 | nvidia,pins = "crtp", "gmb", "slxa", "spih"; | |
209 | nvidia,pull = <2>; | |
210 | nvidia,tristate = <1>; | |
211 | }; | |
212 | conf_dta { | |
213 | nvidia,pins = "dta", "dtb", "dtc", "dtd"; | |
214 | nvidia,pull = <1>; | |
215 | nvidia,tristate = <0>; | |
216 | }; | |
217 | conf_dte { | |
218 | nvidia,pins = "dte", "spif"; | |
219 | nvidia,pull = <1>; | |
220 | nvidia,tristate = <1>; | |
221 | }; | |
222 | conf_hdint { | |
223 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", | |
224 | "lpw1", "lsck", "lsda", "lsdi", "lvp0"; | |
225 | nvidia,tristate = <1>; | |
226 | }; | |
227 | conf_kbca { | |
228 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
229 | "kbce", "kbcf", "sdio1", "uaa", "uab"; | |
230 | nvidia,pull = <2>; | |
231 | nvidia,tristate = <0>; | |
232 | }; | |
233 | conf_lc { | |
234 | nvidia,pins = "lc", "ls"; | |
235 | nvidia,pull = <2>; | |
236 | }; | |
237 | conf_ld0 { | |
238 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
239 | "ld5", "ld6", "ld7", "ld8", "ld9", | |
240 | "ld10", "ld11", "ld12", "ld13", "ld14", | |
241 | "ld15", "ld16", "ld17", "ldi", "lhp0", | |
242 | "lhp1", "lhp2", "lhs", "lm0", "lpp", | |
243 | "lpw0", "lpw2", "lsc0", "lsc1", "lspi", | |
244 | "lvp1", "lvs", "pmc", "sdb"; | |
245 | nvidia,tristate = <0>; | |
246 | }; | |
247 | conf_ld17_0 { | |
248 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | |
249 | "ld23_22"; | |
250 | nvidia,pull = <1>; | |
251 | }; | |
c729429e WN |
252 | drive_sdio1 { |
253 | nvidia,pins = "drive_sdio1"; | |
254 | nvidia,high-speed-mode = <0>; | |
255 | nvidia,schmitt = <1>; | |
256 | nvidia,low-power-mode = <3>; | |
257 | nvidia,pull-down-strength = <31>; | |
258 | nvidia,pull-up-strength = <31>; | |
259 | nvidia,slew-rate-rising = <3>; | |
260 | nvidia,slew-rate-falling = <3>; | |
261 | }; | |
ecc295bb | 262 | }; |
cf633464 MZ |
263 | |
264 | state_i2cmux_ddc: pinmux_i2cmux_ddc { | |
265 | ddc { | |
266 | nvidia,pins = "ddc"; | |
267 | nvidia,function = "i2c2"; | |
268 | }; | |
269 | pta { | |
270 | nvidia,pins = "pta"; | |
271 | nvidia,function = "rsvd4"; | |
272 | }; | |
273 | }; | |
274 | ||
275 | state_i2cmux_pta: pinmux_i2cmux_pta { | |
276 | ddc { | |
277 | nvidia,pins = "ddc"; | |
278 | nvidia,function = "rsvd4"; | |
279 | }; | |
280 | pta { | |
281 | nvidia,pins = "pta"; | |
282 | nvidia,function = "i2c2"; | |
283 | }; | |
284 | }; | |
285 | ||
286 | state_i2cmux_idle: pinmux_i2cmux_idle { | |
287 | ddc { | |
288 | nvidia,pins = "ddc"; | |
289 | nvidia,function = "rsvd4"; | |
290 | }; | |
291 | pta { | |
292 | nvidia,pins = "pta"; | |
293 | nvidia,function = "rsvd4"; | |
294 | }; | |
295 | }; | |
ecc295bb SW |
296 | }; |
297 | ||
2a5fdc9a SW |
298 | i2s@70002800 { |
299 | status = "okay"; | |
c04abb3a SW |
300 | }; |
301 | ||
302 | serial@70006300 { | |
2a5fdc9a | 303 | status = "okay"; |
c04abb3a SW |
304 | }; |
305 | ||
88950f3b | 306 | i2c@7000c000 { |
2a5fdc9a | 307 | status = "okay"; |
88950f3b | 308 | clock-frequency = <400000>; |
797acf70 SW |
309 | |
310 | wm8903: wm8903@1a { | |
311 | compatible = "wlf,wm8903"; | |
312 | reg = <0x1a>; | |
313 | interrupt-parent = <&gpio>; | |
3325f1bc | 314 | interrupts = <TEGRA_GPIO(X, 3) 0x04>; |
797acf70 SW |
315 | |
316 | gpio-controller; | |
317 | #gpio-cells = <2>; | |
318 | ||
319 | micdet-cfg = <0>; | |
320 | micdet-delay = <100>; | |
95decf84 | 321 | gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; |
797acf70 | 322 | }; |
b46b0b54 LD |
323 | |
324 | /* ALS and proximity sensor */ | |
325 | isl29018@44 { | |
326 | compatible = "isil,isl29018"; | |
327 | reg = <0x44>; | |
328 | interrupt-parent = <&gpio>; | |
3325f1bc | 329 | interrupts = <TEGRA_GPIO(Z, 2) 0x04>; |
b46b0b54 | 330 | }; |
88950f3b SW |
331 | }; |
332 | ||
333 | i2c@7000c400 { | |
2a5fdc9a | 334 | status = "okay"; |
97d5520f | 335 | clock-frequency = <100000>; |
88950f3b SW |
336 | }; |
337 | ||
cf633464 MZ |
338 | i2cmux { |
339 | compatible = "i2c-mux-pinctrl"; | |
340 | #address-cells = <1>; | |
341 | #size-cells = <0>; | |
342 | ||
343 | i2c-parent = <&{/i2c@7000c400}>; | |
344 | ||
345 | pinctrl-names = "ddc", "pta", "idle"; | |
346 | pinctrl-0 = <&state_i2cmux_ddc>; | |
347 | pinctrl-1 = <&state_i2cmux_pta>; | |
348 | pinctrl-2 = <&state_i2cmux_idle>; | |
349 | ||
97d5520f | 350 | hdmi_ddc: i2c@0 { |
cf633464 MZ |
351 | reg = <0>; |
352 | #address-cells = <1>; | |
353 | #size-cells = <0>; | |
354 | }; | |
355 | ||
356 | i2c@1 { | |
357 | reg = <1>; | |
358 | #address-cells = <1>; | |
359 | #size-cells = <0>; | |
360 | }; | |
361 | }; | |
362 | ||
88950f3b | 363 | i2c@7000c500 { |
2a5fdc9a | 364 | status = "okay"; |
88950f3b SW |
365 | clock-frequency = <400000>; |
366 | }; | |
367 | ||
368 | i2c@7000d000 { | |
2a5fdc9a | 369 | status = "okay"; |
88950f3b | 370 | clock-frequency = <400000>; |
017a0104 SW |
371 | |
372 | pmic: tps6586x@34 { | |
373 | compatible = "ti,tps6586x"; | |
374 | reg = <0x34>; | |
375 | interrupts = <0 86 0x4>; | |
376 | ||
44b12ef7 SW |
377 | ti,system-power-controller; |
378 | ||
017a0104 SW |
379 | #gpio-cells = <2>; |
380 | gpio-controller; | |
381 | ||
382 | sys-supply = <&vdd_5v0_reg>; | |
383 | vin-sm0-supply = <&sys_reg>; | |
384 | vin-sm1-supply = <&sys_reg>; | |
385 | vin-sm2-supply = <&sys_reg>; | |
386 | vinldo01-supply = <&sm2_reg>; | |
387 | vinldo23-supply = <&sm2_reg>; | |
388 | vinldo4-supply = <&sm2_reg>; | |
389 | vinldo678-supply = <&sm2_reg>; | |
390 | vinldo9-supply = <&sm2_reg>; | |
391 | ||
392 | regulators { | |
b9c665d7 | 393 | sys_reg: sys { |
017a0104 SW |
394 | regulator-name = "vdd_sys"; |
395 | regulator-always-on; | |
396 | }; | |
397 | ||
b9c665d7 | 398 | sm0 { |
017a0104 SW |
399 | regulator-name = "vdd_sm0,vdd_core"; |
400 | regulator-min-microvolt = <1200000>; | |
401 | regulator-max-microvolt = <1200000>; | |
402 | regulator-always-on; | |
403 | }; | |
404 | ||
b9c665d7 | 405 | sm1 { |
017a0104 SW |
406 | regulator-name = "vdd_sm1,vdd_cpu"; |
407 | regulator-min-microvolt = <1000000>; | |
408 | regulator-max-microvolt = <1000000>; | |
409 | regulator-always-on; | |
410 | }; | |
411 | ||
b9c665d7 | 412 | sm2_reg: sm2 { |
017a0104 SW |
413 | regulator-name = "vdd_sm2,vin_ldo*"; |
414 | regulator-min-microvolt = <3700000>; | |
415 | regulator-max-microvolt = <3700000>; | |
416 | regulator-always-on; | |
417 | }; | |
418 | ||
419 | /* LDO0 is not connected to anything */ | |
420 | ||
b9c665d7 | 421 | ldo1 { |
017a0104 SW |
422 | regulator-name = "vdd_ldo1,avdd_pll*"; |
423 | regulator-min-microvolt = <1100000>; | |
424 | regulator-max-microvolt = <1100000>; | |
425 | regulator-always-on; | |
426 | }; | |
427 | ||
b9c665d7 | 428 | ldo2 { |
017a0104 SW |
429 | regulator-name = "vdd_ldo2,vdd_rtc"; |
430 | regulator-min-microvolt = <1200000>; | |
431 | regulator-max-microvolt = <1200000>; | |
432 | }; | |
433 | ||
b9c665d7 | 434 | ldo3 { |
017a0104 SW |
435 | regulator-name = "vdd_ldo3,avdd_usb*"; |
436 | regulator-min-microvolt = <3300000>; | |
437 | regulator-max-microvolt = <3300000>; | |
438 | regulator-always-on; | |
439 | }; | |
440 | ||
b9c665d7 | 441 | ldo4 { |
017a0104 SW |
442 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; |
443 | regulator-min-microvolt = <1800000>; | |
444 | regulator-max-microvolt = <1800000>; | |
445 | regulator-always-on; | |
446 | }; | |
447 | ||
b9c665d7 | 448 | ldo5 { |
017a0104 SW |
449 | regulator-name = "vdd_ldo5,vcore_mmc"; |
450 | regulator-min-microvolt = <2850000>; | |
451 | regulator-max-microvolt = <2850000>; | |
452 | regulator-always-on; | |
453 | }; | |
454 | ||
b9c665d7 | 455 | ldo6 { |
017a0104 SW |
456 | regulator-name = "vdd_ldo6,avdd_vdac"; |
457 | regulator-min-microvolt = <1800000>; | |
458 | regulator-max-microvolt = <1800000>; | |
459 | }; | |
460 | ||
97d5520f | 461 | hdmi_vdd_reg: ldo7 { |
017a0104 SW |
462 | regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; |
463 | regulator-min-microvolt = <3300000>; | |
464 | regulator-max-microvolt = <3300000>; | |
465 | }; | |
466 | ||
97d5520f | 467 | hdmi_pll_reg: ldo8 { |
017a0104 SW |
468 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; |
469 | regulator-min-microvolt = <1800000>; | |
470 | regulator-max-microvolt = <1800000>; | |
471 | }; | |
472 | ||
b9c665d7 | 473 | ldo9 { |
017a0104 SW |
474 | regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; |
475 | regulator-min-microvolt = <2850000>; | |
476 | regulator-max-microvolt = <2850000>; | |
477 | regulator-always-on; | |
478 | }; | |
479 | ||
b9c665d7 | 480 | ldo_rtc { |
017a0104 SW |
481 | regulator-name = "vdd_rtc_out,vdd_cell"; |
482 | regulator-min-microvolt = <3300000>; | |
483 | regulator-max-microvolt = <3300000>; | |
484 | regulator-always-on; | |
485 | }; | |
486 | }; | |
487 | }; | |
ee9f7260 TR |
488 | |
489 | temperature-sensor@4c { | |
490 | compatible = "onnn,nct1008"; | |
491 | reg = <0x4c>; | |
492 | }; | |
017a0104 SW |
493 | }; |
494 | ||
495 | pmc { | |
496 | nvidia,invert-interrupt; | |
a44a019d JL |
497 | nvidia,suspend-mode = <2>; |
498 | nvidia,cpu-pwr-good-time = <2000>; | |
499 | nvidia,cpu-pwr-off-time = <100>; | |
500 | nvidia,core-pwr-good-time = <3845 3845>; | |
501 | nvidia,core-pwr-off-time = <458>; | |
502 | nvidia,sys-clock-req-active-high; | |
88950f3b SW |
503 | }; |
504 | ||
2a5fdc9a SW |
505 | usb@c5000000 { |
506 | status = "okay"; | |
c04abb3a SW |
507 | }; |
508 | ||
4c94c8b5 VB |
509 | usb-phy@c5000000 { |
510 | status = "okay"; | |
511 | }; | |
512 | ||
2a5fdc9a SW |
513 | usb@c5004000 { |
514 | status = "okay"; | |
3325f1bc SW |
515 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
516 | GPIO_ACTIVE_LOW>; | |
797acf70 SW |
517 | }; |
518 | ||
9dffe3be | 519 | usb-phy@c5004000 { |
4c94c8b5 | 520 | status = "okay"; |
3325f1bc SW |
521 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
522 | GPIO_ACTIVE_LOW>; | |
c04abb3a SW |
523 | }; |
524 | ||
9dffe3be VB |
525 | usb@c5008000 { |
526 | status = "okay"; | |
40e8b3a6 VB |
527 | }; |
528 | ||
4c94c8b5 VB |
529 | usb-phy@c5008000 { |
530 | status = "okay"; | |
531 | }; | |
532 | ||
c729429e WN |
533 | sdhci@c8000000 { |
534 | status = "okay"; | |
3325f1bc | 535 | power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; |
c729429e | 536 | bus-width = <4>; |
7a2617a6 | 537 | keep-power-in-suspend; |
c729429e WN |
538 | }; |
539 | ||
c04abb3a | 540 | sdhci@c8000400 { |
2a5fdc9a | 541 | status = "okay"; |
3325f1bc SW |
542 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
543 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; | |
544 | power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; | |
deb88cc3 | 545 | bus-width = <4>; |
c04abb3a SW |
546 | }; |
547 | ||
548 | sdhci@c8000600 { | |
2a5fdc9a | 549 | status = "okay"; |
deb88cc3 | 550 | bus-width = <8>; |
7a2617a6 | 551 | non-removable; |
c04abb3a SW |
552 | }; |
553 | ||
7021d122 JL |
554 | clocks { |
555 | compatible = "simple-bus"; | |
556 | #address-cells = <1>; | |
557 | #size-cells = <0>; | |
558 | ||
559 | clk32k_in: clock { | |
560 | compatible = "fixed-clock"; | |
561 | reg=<0>; | |
562 | #clock-cells = <0>; | |
563 | clock-frequency = <32768>; | |
564 | }; | |
565 | }; | |
566 | ||
5741a256 JL |
567 | gpio-keys { |
568 | compatible = "gpio-keys"; | |
569 | ||
570 | power { | |
571 | label = "Power"; | |
3325f1bc | 572 | gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
5741a256 JL |
573 | linux,code = <116>; /* KEY_POWER */ |
574 | gpio-key,wakeup; | |
575 | }; | |
576 | }; | |
577 | ||
017a0104 SW |
578 | regulators { |
579 | compatible = "simple-bus"; | |
580 | #address-cells = <1>; | |
581 | #size-cells = <0>; | |
582 | ||
583 | vdd_5v0_reg: regulator@0 { | |
584 | compatible = "regulator-fixed"; | |
585 | reg = <0>; | |
586 | regulator-name = "vdd_5v0"; | |
587 | regulator-min-microvolt = <5000000>; | |
588 | regulator-max-microvolt = <5000000>; | |
589 | regulator-always-on; | |
590 | }; | |
591 | ||
592 | regulator@1 { | |
593 | compatible = "regulator-fixed"; | |
594 | reg = <1>; | |
595 | regulator-name = "vdd_1v5"; | |
596 | regulator-min-microvolt = <1500000>; | |
597 | regulator-max-microvolt = <1500000>; | |
3325f1bc | 598 | gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
017a0104 SW |
599 | }; |
600 | ||
601 | regulator@2 { | |
602 | compatible = "regulator-fixed"; | |
603 | reg = <2>; | |
604 | regulator-name = "vdd_1v2"; | |
605 | regulator-min-microvolt = <1200000>; | |
606 | regulator-max-microvolt = <1200000>; | |
3325f1bc | 607 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
017a0104 SW |
608 | enable-active-high; |
609 | }; | |
610 | ||
611 | regulator@3 { | |
612 | compatible = "regulator-fixed"; | |
613 | reg = <3>; | |
614 | regulator-name = "vdd_pnl"; | |
615 | regulator-min-microvolt = <2800000>; | |
616 | regulator-max-microvolt = <2800000>; | |
3325f1bc | 617 | gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; |
017a0104 SW |
618 | enable-active-high; |
619 | }; | |
620 | ||
621 | regulator@4 { | |
622 | compatible = "regulator-fixed"; | |
623 | reg = <4>; | |
624 | regulator-name = "vdd_bl"; | |
625 | regulator-min-microvolt = <2800000>; | |
626 | regulator-max-microvolt = <2800000>; | |
3325f1bc | 627 | gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; |
017a0104 SW |
628 | enable-active-high; |
629 | }; | |
630 | }; | |
631 | ||
797acf70 SW |
632 | sound { |
633 | compatible = "nvidia,tegra-audio-wm8903-ventana", | |
634 | "nvidia,tegra-audio-wm8903"; | |
635 | nvidia,model = "NVIDIA Tegra Ventana"; | |
636 | ||
637 | nvidia,audio-routing = | |
638 | "Headphone Jack", "HPOUTR", | |
639 | "Headphone Jack", "HPOUTL", | |
640 | "Int Spk", "ROP", | |
641 | "Int Spk", "RON", | |
642 | "Int Spk", "LOP", | |
643 | "Int Spk", "LON", | |
644 | "Mic Jack", "MICBIAS", | |
645 | "IN1L", "Mic Jack"; | |
646 | ||
647 | nvidia,i2s-controller = <&tegra_i2s1>; | |
648 | nvidia,audio-codec = <&wm8903>; | |
649 | ||
3325f1bc SW |
650 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
651 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; | |
652 | nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) | |
653 | GPIO_ACTIVE_HIGH>; | |
654 | nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) | |
655 | GPIO_ACTIVE_HIGH>; | |
f9cd2b3b | 656 | |
1071b2df | 657 | clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; |
f9cd2b3b | 658 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
797acf70 | 659 | }; |
add29e61 | 660 | }; |