Commit | Line | Data |
---|---|---|
add29e61 PDS |
1 | /dts-v1/; |
2 | ||
add29e61 PDS |
3 | /include/ "tegra20.dtsi" |
4 | ||
5 | / { | |
6 | model = "NVIDIA Tegra2 Ventana evaluation board"; | |
7 | compatible = "nvidia,ventana", "nvidia,tegra20"; | |
8 | ||
add29e61 | 9 | memory { |
95decf84 | 10 | reg = <0x00000000 0x40000000>; |
add29e61 PDS |
11 | }; |
12 | ||
f9eb26a4 | 13 | pinmux { |
ecc295bb SW |
14 | pinctrl-names = "default"; |
15 | pinctrl-0 = <&state_default>; | |
16 | ||
17 | state_default: pinmux { | |
18 | ata { | |
19 | nvidia,pins = "ata"; | |
20 | nvidia,function = "ide"; | |
21 | }; | |
22 | atb { | |
23 | nvidia,pins = "atb", "gma", "gme"; | |
24 | nvidia,function = "sdio4"; | |
25 | }; | |
26 | atc { | |
27 | nvidia,pins = "atc"; | |
28 | nvidia,function = "nand"; | |
29 | }; | |
30 | atd { | |
31 | nvidia,pins = "atd", "ate", "gmb", "spia", | |
32 | "spib", "spic"; | |
33 | nvidia,function = "gmi"; | |
34 | }; | |
35 | cdev1 { | |
36 | nvidia,pins = "cdev1"; | |
37 | nvidia,function = "plla_out"; | |
38 | }; | |
39 | cdev2 { | |
40 | nvidia,pins = "cdev2"; | |
41 | nvidia,function = "pllp_out4"; | |
42 | }; | |
43 | crtp { | |
44 | nvidia,pins = "crtp", "lm1"; | |
45 | nvidia,function = "crt"; | |
46 | }; | |
47 | csus { | |
48 | nvidia,pins = "csus"; | |
49 | nvidia,function = "vi_sensor_clk"; | |
50 | }; | |
51 | dap1 { | |
52 | nvidia,pins = "dap1"; | |
53 | nvidia,function = "dap1"; | |
54 | }; | |
55 | dap2 { | |
56 | nvidia,pins = "dap2"; | |
57 | nvidia,function = "dap2"; | |
58 | }; | |
59 | dap3 { | |
60 | nvidia,pins = "dap3"; | |
61 | nvidia,function = "dap3"; | |
62 | }; | |
63 | dap4 { | |
64 | nvidia,pins = "dap4"; | |
65 | nvidia,function = "dap4"; | |
66 | }; | |
ecc295bb SW |
67 | dta { |
68 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; | |
69 | nvidia,function = "vi"; | |
70 | }; | |
71 | dtf { | |
72 | nvidia,pins = "dtf"; | |
73 | nvidia,function = "i2c3"; | |
74 | }; | |
75 | gmc { | |
76 | nvidia,pins = "gmc"; | |
77 | nvidia,function = "uartd"; | |
78 | }; | |
79 | gmd { | |
80 | nvidia,pins = "gmd"; | |
81 | nvidia,function = "sflash"; | |
82 | }; | |
83 | gpu { | |
84 | nvidia,pins = "gpu"; | |
85 | nvidia,function = "pwm"; | |
86 | }; | |
87 | gpu7 { | |
88 | nvidia,pins = "gpu7"; | |
89 | nvidia,function = "rtck"; | |
90 | }; | |
91 | gpv { | |
92 | nvidia,pins = "gpv", "slxa", "slxk"; | |
93 | nvidia,function = "pcie"; | |
94 | }; | |
95 | hdint { | |
cf633464 | 96 | nvidia,pins = "hdint"; |
ecc295bb SW |
97 | nvidia,function = "hdmi"; |
98 | }; | |
99 | i2cp { | |
100 | nvidia,pins = "i2cp"; | |
101 | nvidia,function = "i2cp"; | |
102 | }; | |
103 | irrx { | |
104 | nvidia,pins = "irrx", "irtx"; | |
105 | nvidia,function = "uartb"; | |
106 | }; | |
107 | kbca { | |
108 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
109 | "kbce", "kbcf"; | |
110 | nvidia,function = "kbc"; | |
111 | }; | |
112 | lcsn { | |
113 | nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", | |
114 | "lsdi", "lvp0"; | |
115 | nvidia,function = "rsvd4"; | |
116 | }; | |
117 | ld0 { | |
118 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
119 | "ld5", "ld6", "ld7", "ld8", "ld9", | |
120 | "ld10", "ld11", "ld12", "ld13", "ld14", | |
121 | "ld15", "ld16", "ld17", "ldi", "lhp0", | |
122 | "lhp1", "lhp2", "lhs", "lpp", "lpw0", | |
123 | "lpw2", "lsc0", "lsc1", "lsck", "lsda", | |
124 | "lspi", "lvp1", "lvs"; | |
125 | nvidia,function = "displaya"; | |
126 | }; | |
cf633464 MZ |
127 | owc { |
128 | nvidia,pins = "owc", "spdi", "spdo", "uac"; | |
129 | nvidia,function = "rsvd2"; | |
130 | }; | |
ecc295bb SW |
131 | pmc { |
132 | nvidia,pins = "pmc"; | |
133 | nvidia,function = "pwr_on"; | |
134 | }; | |
135 | rm { | |
136 | nvidia,pins = "rm"; | |
137 | nvidia,function = "i2c1"; | |
138 | }; | |
139 | sdb { | |
140 | nvidia,pins = "sdb", "sdc", "sdd", "slxc"; | |
141 | nvidia,function = "sdio3"; | |
142 | }; | |
143 | sdio1 { | |
144 | nvidia,pins = "sdio1"; | |
145 | nvidia,function = "sdio1"; | |
146 | }; | |
147 | slxd { | |
148 | nvidia,pins = "slxd"; | |
149 | nvidia,function = "spdif"; | |
150 | }; | |
151 | spid { | |
152 | nvidia,pins = "spid", "spie", "spif"; | |
153 | nvidia,function = "spi1"; | |
154 | }; | |
155 | spig { | |
156 | nvidia,pins = "spig", "spih"; | |
157 | nvidia,function = "spi2_alt"; | |
158 | }; | |
159 | uaa { | |
160 | nvidia,pins = "uaa", "uab", "uda"; | |
161 | nvidia,function = "ulpi"; | |
162 | }; | |
163 | uad { | |
164 | nvidia,pins = "uad"; | |
165 | nvidia,function = "irda"; | |
166 | }; | |
167 | uca { | |
168 | nvidia,pins = "uca", "ucb"; | |
169 | nvidia,function = "uartc"; | |
170 | }; | |
171 | conf_ata { | |
172 | nvidia,pins = "ata", "atb", "atc", "atd", | |
173 | "cdev1", "cdev2", "dap1", "dap2", | |
174 | "dap4", "ddc", "dtf", "gma", "gmc", | |
175 | "gme", "gpu", "gpu7", "i2cp", "irrx", | |
176 | "irtx", "pta", "rm", "sdc", "sdd", | |
177 | "slxc", "slxd", "slxk", "spdi", "spdo", | |
178 | "uac", "uad", "uca", "ucb", "uda"; | |
179 | nvidia,pull = <0>; | |
180 | nvidia,tristate = <0>; | |
181 | }; | |
182 | conf_ate { | |
183 | nvidia,pins = "ate", "csus", "dap3", "gmd", | |
184 | "gpv", "owc", "spia", "spib", "spic", | |
185 | "spid", "spie", "spig"; | |
186 | nvidia,pull = <0>; | |
187 | nvidia,tristate = <1>; | |
188 | }; | |
189 | conf_ck32 { | |
190 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | |
191 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | |
192 | nvidia,pull = <0>; | |
193 | }; | |
194 | conf_crtp { | |
195 | nvidia,pins = "crtp", "gmb", "slxa", "spih"; | |
196 | nvidia,pull = <2>; | |
197 | nvidia,tristate = <1>; | |
198 | }; | |
199 | conf_dta { | |
200 | nvidia,pins = "dta", "dtb", "dtc", "dtd"; | |
201 | nvidia,pull = <1>; | |
202 | nvidia,tristate = <0>; | |
203 | }; | |
204 | conf_dte { | |
205 | nvidia,pins = "dte", "spif"; | |
206 | nvidia,pull = <1>; | |
207 | nvidia,tristate = <1>; | |
208 | }; | |
209 | conf_hdint { | |
210 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", | |
211 | "lpw1", "lsck", "lsda", "lsdi", "lvp0"; | |
212 | nvidia,tristate = <1>; | |
213 | }; | |
214 | conf_kbca { | |
215 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
216 | "kbce", "kbcf", "sdio1", "uaa", "uab"; | |
217 | nvidia,pull = <2>; | |
218 | nvidia,tristate = <0>; | |
219 | }; | |
220 | conf_lc { | |
221 | nvidia,pins = "lc", "ls"; | |
222 | nvidia,pull = <2>; | |
223 | }; | |
224 | conf_ld0 { | |
225 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
226 | "ld5", "ld6", "ld7", "ld8", "ld9", | |
227 | "ld10", "ld11", "ld12", "ld13", "ld14", | |
228 | "ld15", "ld16", "ld17", "ldi", "lhp0", | |
229 | "lhp1", "lhp2", "lhs", "lm0", "lpp", | |
230 | "lpw0", "lpw2", "lsc0", "lsc1", "lspi", | |
231 | "lvp1", "lvs", "pmc", "sdb"; | |
232 | nvidia,tristate = <0>; | |
233 | }; | |
234 | conf_ld17_0 { | |
235 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | |
236 | "ld23_22"; | |
237 | nvidia,pull = <1>; | |
238 | }; | |
c729429e WN |
239 | drive_sdio1 { |
240 | nvidia,pins = "drive_sdio1"; | |
241 | nvidia,high-speed-mode = <0>; | |
242 | nvidia,schmitt = <1>; | |
243 | nvidia,low-power-mode = <3>; | |
244 | nvidia,pull-down-strength = <31>; | |
245 | nvidia,pull-up-strength = <31>; | |
246 | nvidia,slew-rate-rising = <3>; | |
247 | nvidia,slew-rate-falling = <3>; | |
248 | }; | |
ecc295bb | 249 | }; |
cf633464 MZ |
250 | |
251 | state_i2cmux_ddc: pinmux_i2cmux_ddc { | |
252 | ddc { | |
253 | nvidia,pins = "ddc"; | |
254 | nvidia,function = "i2c2"; | |
255 | }; | |
256 | pta { | |
257 | nvidia,pins = "pta"; | |
258 | nvidia,function = "rsvd4"; | |
259 | }; | |
260 | }; | |
261 | ||
262 | state_i2cmux_pta: pinmux_i2cmux_pta { | |
263 | ddc { | |
264 | nvidia,pins = "ddc"; | |
265 | nvidia,function = "rsvd4"; | |
266 | }; | |
267 | pta { | |
268 | nvidia,pins = "pta"; | |
269 | nvidia,function = "i2c2"; | |
270 | }; | |
271 | }; | |
272 | ||
273 | state_i2cmux_idle: pinmux_i2cmux_idle { | |
274 | ddc { | |
275 | nvidia,pins = "ddc"; | |
276 | nvidia,function = "rsvd4"; | |
277 | }; | |
278 | pta { | |
279 | nvidia,pins = "pta"; | |
280 | nvidia,function = "rsvd4"; | |
281 | }; | |
282 | }; | |
ecc295bb SW |
283 | }; |
284 | ||
2a5fdc9a SW |
285 | i2s@70002800 { |
286 | status = "okay"; | |
c04abb3a SW |
287 | }; |
288 | ||
289 | serial@70006300 { | |
2a5fdc9a | 290 | status = "okay"; |
c04abb3a SW |
291 | clock-frequency = <216000000>; |
292 | }; | |
293 | ||
88950f3b | 294 | i2c@7000c000 { |
2a5fdc9a | 295 | status = "okay"; |
88950f3b | 296 | clock-frequency = <400000>; |
797acf70 SW |
297 | |
298 | wm8903: wm8903@1a { | |
299 | compatible = "wlf,wm8903"; | |
300 | reg = <0x1a>; | |
301 | interrupt-parent = <&gpio>; | |
95decf84 | 302 | interrupts = <187 0x04>; |
797acf70 SW |
303 | |
304 | gpio-controller; | |
305 | #gpio-cells = <2>; | |
306 | ||
307 | micdet-cfg = <0>; | |
308 | micdet-delay = <100>; | |
95decf84 | 309 | gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; |
797acf70 | 310 | }; |
b46b0b54 LD |
311 | |
312 | /* ALS and proximity sensor */ | |
313 | isl29018@44 { | |
314 | compatible = "isil,isl29018"; | |
315 | reg = <0x44>; | |
316 | interrupt-parent = <&gpio>; | |
317 | interrupts = <202 0x04>; /*gpio PZ2 */ | |
318 | }; | |
88950f3b SW |
319 | }; |
320 | ||
321 | i2c@7000c400 { | |
2a5fdc9a | 322 | status = "okay"; |
88950f3b SW |
323 | clock-frequency = <400000>; |
324 | }; | |
325 | ||
cf633464 MZ |
326 | i2cmux { |
327 | compatible = "i2c-mux-pinctrl"; | |
328 | #address-cells = <1>; | |
329 | #size-cells = <0>; | |
330 | ||
331 | i2c-parent = <&{/i2c@7000c400}>; | |
332 | ||
333 | pinctrl-names = "ddc", "pta", "idle"; | |
334 | pinctrl-0 = <&state_i2cmux_ddc>; | |
335 | pinctrl-1 = <&state_i2cmux_pta>; | |
336 | pinctrl-2 = <&state_i2cmux_idle>; | |
337 | ||
338 | i2c@0 { | |
339 | reg = <0>; | |
340 | #address-cells = <1>; | |
341 | #size-cells = <0>; | |
342 | }; | |
343 | ||
344 | i2c@1 { | |
345 | reg = <1>; | |
346 | #address-cells = <1>; | |
347 | #size-cells = <0>; | |
348 | }; | |
349 | }; | |
350 | ||
88950f3b | 351 | i2c@7000c500 { |
2a5fdc9a | 352 | status = "okay"; |
88950f3b SW |
353 | clock-frequency = <400000>; |
354 | }; | |
355 | ||
356 | i2c@7000d000 { | |
2a5fdc9a | 357 | status = "okay"; |
88950f3b | 358 | clock-frequency = <400000>; |
017a0104 SW |
359 | |
360 | pmic: tps6586x@34 { | |
361 | compatible = "ti,tps6586x"; | |
362 | reg = <0x34>; | |
363 | interrupts = <0 86 0x4>; | |
364 | ||
44b12ef7 SW |
365 | ti,system-power-controller; |
366 | ||
017a0104 SW |
367 | #gpio-cells = <2>; |
368 | gpio-controller; | |
369 | ||
370 | sys-supply = <&vdd_5v0_reg>; | |
371 | vin-sm0-supply = <&sys_reg>; | |
372 | vin-sm1-supply = <&sys_reg>; | |
373 | vin-sm2-supply = <&sys_reg>; | |
374 | vinldo01-supply = <&sm2_reg>; | |
375 | vinldo23-supply = <&sm2_reg>; | |
376 | vinldo4-supply = <&sm2_reg>; | |
377 | vinldo678-supply = <&sm2_reg>; | |
378 | vinldo9-supply = <&sm2_reg>; | |
379 | ||
380 | regulators { | |
b9c665d7 | 381 | sys_reg: sys { |
017a0104 SW |
382 | regulator-name = "vdd_sys"; |
383 | regulator-always-on; | |
384 | }; | |
385 | ||
b9c665d7 | 386 | sm0 { |
017a0104 SW |
387 | regulator-name = "vdd_sm0,vdd_core"; |
388 | regulator-min-microvolt = <1200000>; | |
389 | regulator-max-microvolt = <1200000>; | |
390 | regulator-always-on; | |
391 | }; | |
392 | ||
b9c665d7 | 393 | sm1 { |
017a0104 SW |
394 | regulator-name = "vdd_sm1,vdd_cpu"; |
395 | regulator-min-microvolt = <1000000>; | |
396 | regulator-max-microvolt = <1000000>; | |
397 | regulator-always-on; | |
398 | }; | |
399 | ||
b9c665d7 | 400 | sm2_reg: sm2 { |
017a0104 SW |
401 | regulator-name = "vdd_sm2,vin_ldo*"; |
402 | regulator-min-microvolt = <3700000>; | |
403 | regulator-max-microvolt = <3700000>; | |
404 | regulator-always-on; | |
405 | }; | |
406 | ||
407 | /* LDO0 is not connected to anything */ | |
408 | ||
b9c665d7 | 409 | ldo1 { |
017a0104 SW |
410 | regulator-name = "vdd_ldo1,avdd_pll*"; |
411 | regulator-min-microvolt = <1100000>; | |
412 | regulator-max-microvolt = <1100000>; | |
413 | regulator-always-on; | |
414 | }; | |
415 | ||
b9c665d7 | 416 | ldo2 { |
017a0104 SW |
417 | regulator-name = "vdd_ldo2,vdd_rtc"; |
418 | regulator-min-microvolt = <1200000>; | |
419 | regulator-max-microvolt = <1200000>; | |
420 | }; | |
421 | ||
b9c665d7 | 422 | ldo3 { |
017a0104 SW |
423 | regulator-name = "vdd_ldo3,avdd_usb*"; |
424 | regulator-min-microvolt = <3300000>; | |
425 | regulator-max-microvolt = <3300000>; | |
426 | regulator-always-on; | |
427 | }; | |
428 | ||
b9c665d7 | 429 | ldo4 { |
017a0104 SW |
430 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; |
431 | regulator-min-microvolt = <1800000>; | |
432 | regulator-max-microvolt = <1800000>; | |
433 | regulator-always-on; | |
434 | }; | |
435 | ||
b9c665d7 | 436 | ldo5 { |
017a0104 SW |
437 | regulator-name = "vdd_ldo5,vcore_mmc"; |
438 | regulator-min-microvolt = <2850000>; | |
439 | regulator-max-microvolt = <2850000>; | |
440 | regulator-always-on; | |
441 | }; | |
442 | ||
b9c665d7 | 443 | ldo6 { |
017a0104 SW |
444 | regulator-name = "vdd_ldo6,avdd_vdac"; |
445 | regulator-min-microvolt = <1800000>; | |
446 | regulator-max-microvolt = <1800000>; | |
447 | }; | |
448 | ||
b9c665d7 | 449 | ldo7 { |
017a0104 SW |
450 | regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; |
451 | regulator-min-microvolt = <3300000>; | |
452 | regulator-max-microvolt = <3300000>; | |
453 | }; | |
454 | ||
b9c665d7 | 455 | ldo8 { |
017a0104 SW |
456 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; |
457 | regulator-min-microvolt = <1800000>; | |
458 | regulator-max-microvolt = <1800000>; | |
459 | }; | |
460 | ||
b9c665d7 | 461 | ldo9 { |
017a0104 SW |
462 | regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; |
463 | regulator-min-microvolt = <2850000>; | |
464 | regulator-max-microvolt = <2850000>; | |
465 | regulator-always-on; | |
466 | }; | |
467 | ||
b9c665d7 | 468 | ldo_rtc { |
017a0104 SW |
469 | regulator-name = "vdd_rtc_out,vdd_cell"; |
470 | regulator-min-microvolt = <3300000>; | |
471 | regulator-max-microvolt = <3300000>; | |
472 | regulator-always-on; | |
473 | }; | |
474 | }; | |
475 | }; | |
476 | }; | |
477 | ||
478 | pmc { | |
479 | nvidia,invert-interrupt; | |
88950f3b SW |
480 | }; |
481 | ||
2a5fdc9a SW |
482 | usb@c5000000 { |
483 | status = "okay"; | |
c04abb3a SW |
484 | }; |
485 | ||
2a5fdc9a SW |
486 | usb@c5004000 { |
487 | status = "okay"; | |
488 | nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ | |
797acf70 SW |
489 | }; |
490 | ||
2a5fdc9a SW |
491 | usb@c5008000 { |
492 | status = "okay"; | |
c04abb3a SW |
493 | }; |
494 | ||
c729429e WN |
495 | sdhci@c8000000 { |
496 | status = "okay"; | |
497 | power-gpios = <&gpio 86 0>; /* gpio PK6 */ | |
498 | bus-width = <4>; | |
499 | }; | |
500 | ||
c04abb3a | 501 | sdhci@c8000400 { |
2a5fdc9a | 502 | status = "okay"; |
c04abb3a SW |
503 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ |
504 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | |
505 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ | |
deb88cc3 | 506 | bus-width = <4>; |
c04abb3a SW |
507 | }; |
508 | ||
509 | sdhci@c8000600 { | |
2a5fdc9a | 510 | status = "okay"; |
deb88cc3 | 511 | bus-width = <8>; |
c04abb3a SW |
512 | }; |
513 | ||
017a0104 SW |
514 | regulators { |
515 | compatible = "simple-bus"; | |
516 | #address-cells = <1>; | |
517 | #size-cells = <0>; | |
518 | ||
519 | vdd_5v0_reg: regulator@0 { | |
520 | compatible = "regulator-fixed"; | |
521 | reg = <0>; | |
522 | regulator-name = "vdd_5v0"; | |
523 | regulator-min-microvolt = <5000000>; | |
524 | regulator-max-microvolt = <5000000>; | |
525 | regulator-always-on; | |
526 | }; | |
527 | ||
528 | regulator@1 { | |
529 | compatible = "regulator-fixed"; | |
530 | reg = <1>; | |
531 | regulator-name = "vdd_1v5"; | |
532 | regulator-min-microvolt = <1500000>; | |
533 | regulator-max-microvolt = <1500000>; | |
534 | gpio = <&pmic 0 0>; | |
535 | }; | |
536 | ||
537 | regulator@2 { | |
538 | compatible = "regulator-fixed"; | |
539 | reg = <2>; | |
540 | regulator-name = "vdd_1v2"; | |
541 | regulator-min-microvolt = <1200000>; | |
542 | regulator-max-microvolt = <1200000>; | |
543 | gpio = <&pmic 1 0>; | |
544 | enable-active-high; | |
545 | }; | |
546 | ||
547 | regulator@3 { | |
548 | compatible = "regulator-fixed"; | |
549 | reg = <3>; | |
550 | regulator-name = "vdd_pnl"; | |
551 | regulator-min-microvolt = <2800000>; | |
552 | regulator-max-microvolt = <2800000>; | |
553 | gpio = <&gpio 22 0>; /* gpio PC6 */ | |
554 | enable-active-high; | |
555 | }; | |
556 | ||
557 | regulator@4 { | |
558 | compatible = "regulator-fixed"; | |
559 | reg = <4>; | |
560 | regulator-name = "vdd_bl"; | |
561 | regulator-min-microvolt = <2800000>; | |
562 | regulator-max-microvolt = <2800000>; | |
563 | gpio = <&gpio 176 0>; /* gpio PW0 */ | |
564 | enable-active-high; | |
565 | }; | |
566 | }; | |
567 | ||
797acf70 SW |
568 | sound { |
569 | compatible = "nvidia,tegra-audio-wm8903-ventana", | |
570 | "nvidia,tegra-audio-wm8903"; | |
571 | nvidia,model = "NVIDIA Tegra Ventana"; | |
572 | ||
573 | nvidia,audio-routing = | |
574 | "Headphone Jack", "HPOUTR", | |
575 | "Headphone Jack", "HPOUTL", | |
576 | "Int Spk", "ROP", | |
577 | "Int Spk", "RON", | |
578 | "Int Spk", "LOP", | |
579 | "Int Spk", "LON", | |
580 | "Mic Jack", "MICBIAS", | |
581 | "IN1L", "Mic Jack"; | |
582 | ||
583 | nvidia,i2s-controller = <&tegra_i2s1>; | |
584 | nvidia,audio-codec = <&wm8903>; | |
585 | ||
586 | nvidia,spkr-en-gpios = <&wm8903 2 0>; | |
587 | nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ | |
c44e438a | 588 | nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */ |
797acf70 SW |
589 | nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ |
590 | }; | |
add29e61 | 591 | }; |