Commit | Line | Data |
---|---|---|
885a8cfa | 1 | #include <dt-bindings/clock/tegra20-car.h> |
3325f1bc | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
ba4104e7 | 3 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
6cecf916 | 4 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
3325f1bc | 5 | |
1bd0bd49 | 6 | #include "skeleton.dtsi" |
8e267f3d GL |
7 | |
8 | / { | |
9 | compatible = "nvidia,tegra20"; | |
870c81a4 | 10 | interrupt-parent = <&lic>; |
8e267f3d | 11 | |
58ecb23f | 12 | host1x@50000000 { |
ed821f07 TR |
13 | compatible = "nvidia,tegra20-host1x", "simple-bus"; |
14 | reg = <0x50000000 0x00024000>; | |
6cecf916 SW |
15 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
16 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ | |
885a8cfa | 17 | clocks = <&tegra_car TEGRA20_CLK_HOST1X>; |
3393d422 SW |
18 | resets = <&tegra_car 28>; |
19 | reset-names = "host1x"; | |
ed821f07 TR |
20 | |
21 | #address-cells = <1>; | |
22 | #size-cells = <1>; | |
23 | ||
24 | ranges = <0x54000000 0x54000000 0x04000000>; | |
25 | ||
58ecb23f | 26 | mpe@54040000 { |
ed821f07 TR |
27 | compatible = "nvidia,tegra20-mpe"; |
28 | reg = <0x54040000 0x00040000>; | |
6cecf916 | 29 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 30 | clocks = <&tegra_car TEGRA20_CLK_MPE>; |
3393d422 SW |
31 | resets = <&tegra_car 60>; |
32 | reset-names = "mpe"; | |
ed821f07 TR |
33 | }; |
34 | ||
58ecb23f | 35 | vi@54080000 { |
ed821f07 TR |
36 | compatible = "nvidia,tegra20-vi"; |
37 | reg = <0x54080000 0x00040000>; | |
6cecf916 | 38 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 39 | clocks = <&tegra_car TEGRA20_CLK_VI>; |
3393d422 SW |
40 | resets = <&tegra_car 20>; |
41 | reset-names = "vi"; | |
ed821f07 TR |
42 | }; |
43 | ||
58ecb23f | 44 | epp@540c0000 { |
ed821f07 TR |
45 | compatible = "nvidia,tegra20-epp"; |
46 | reg = <0x540c0000 0x00040000>; | |
6cecf916 | 47 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 48 | clocks = <&tegra_car TEGRA20_CLK_EPP>; |
3393d422 SW |
49 | resets = <&tegra_car 19>; |
50 | reset-names = "epp"; | |
ed821f07 TR |
51 | }; |
52 | ||
58ecb23f | 53 | isp@54100000 { |
ed821f07 TR |
54 | compatible = "nvidia,tegra20-isp"; |
55 | reg = <0x54100000 0x00040000>; | |
6cecf916 | 56 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 57 | clocks = <&tegra_car TEGRA20_CLK_ISP>; |
3393d422 SW |
58 | resets = <&tegra_car 23>; |
59 | reset-names = "isp"; | |
ed821f07 TR |
60 | }; |
61 | ||
58ecb23f | 62 | gr2d@54140000 { |
ed821f07 TR |
63 | compatible = "nvidia,tegra20-gr2d"; |
64 | reg = <0x54140000 0x00040000>; | |
6cecf916 | 65 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 66 | clocks = <&tegra_car TEGRA20_CLK_GR2D>; |
3393d422 SW |
67 | resets = <&tegra_car 21>; |
68 | reset-names = "2d"; | |
ed821f07 TR |
69 | }; |
70 | ||
de47699d | 71 | gr3d@54180000 { |
ed821f07 | 72 | compatible = "nvidia,tegra20-gr3d"; |
de47699d | 73 | reg = <0x54180000 0x00040000>; |
885a8cfa | 74 | clocks = <&tegra_car TEGRA20_CLK_GR3D>; |
3393d422 SW |
75 | resets = <&tegra_car 24>; |
76 | reset-names = "3d"; | |
ed821f07 TR |
77 | }; |
78 | ||
79 | dc@54200000 { | |
80 | compatible = "nvidia,tegra20-dc"; | |
81 | reg = <0x54200000 0x00040000>; | |
6cecf916 | 82 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa HD |
83 | clocks = <&tegra_car TEGRA20_CLK_DISP1>, |
84 | <&tegra_car TEGRA20_CLK_PLL_P>; | |
d8f64797 | 85 | clock-names = "dc", "parent"; |
3393d422 SW |
86 | resets = <&tegra_car 27>; |
87 | reset-names = "dc"; | |
ed821f07 | 88 | |
688b56b4 TR |
89 | nvidia,head = <0>; |
90 | ||
ed821f07 TR |
91 | rgb { |
92 | status = "disabled"; | |
93 | }; | |
94 | }; | |
95 | ||
96 | dc@54240000 { | |
97 | compatible = "nvidia,tegra20-dc"; | |
98 | reg = <0x54240000 0x00040000>; | |
6cecf916 | 99 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa HD |
100 | clocks = <&tegra_car TEGRA20_CLK_DISP2>, |
101 | <&tegra_car TEGRA20_CLK_PLL_P>; | |
d8f64797 | 102 | clock-names = "dc", "parent"; |
3393d422 SW |
103 | resets = <&tegra_car 26>; |
104 | reset-names = "dc"; | |
ed821f07 | 105 | |
688b56b4 TR |
106 | nvidia,head = <1>; |
107 | ||
ed821f07 TR |
108 | rgb { |
109 | status = "disabled"; | |
110 | }; | |
111 | }; | |
112 | ||
58ecb23f | 113 | hdmi@54280000 { |
ed821f07 TR |
114 | compatible = "nvidia,tegra20-hdmi"; |
115 | reg = <0x54280000 0x00040000>; | |
6cecf916 | 116 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa HD |
117 | clocks = <&tegra_car TEGRA20_CLK_HDMI>, |
118 | <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; | |
8d8b43da | 119 | clock-names = "hdmi", "parent"; |
3393d422 SW |
120 | resets = <&tegra_car 51>; |
121 | reset-names = "hdmi"; | |
ed821f07 TR |
122 | status = "disabled"; |
123 | }; | |
124 | ||
58ecb23f | 125 | tvo@542c0000 { |
ed821f07 TR |
126 | compatible = "nvidia,tegra20-tvo"; |
127 | reg = <0x542c0000 0x00040000>; | |
6cecf916 | 128 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 129 | clocks = <&tegra_car TEGRA20_CLK_TVO>; |
ed821f07 TR |
130 | status = "disabled"; |
131 | }; | |
132 | ||
de47699d | 133 | dsi@54300000 { |
ed821f07 | 134 | compatible = "nvidia,tegra20-dsi"; |
de47699d | 135 | reg = <0x54300000 0x00040000>; |
885a8cfa | 136 | clocks = <&tegra_car TEGRA20_CLK_DSI>; |
3393d422 SW |
137 | resets = <&tegra_car 48>; |
138 | reset-names = "dsi"; | |
ed821f07 TR |
139 | status = "disabled"; |
140 | }; | |
141 | }; | |
142 | ||
2cda1880 | 143 | timer@50040600 { |
73368ba0 | 144 | compatible = "arm,cortex-a9-twd-timer"; |
870c81a4 | 145 | interrupt-parent = <&intc>; |
73368ba0 | 146 | reg = <0x50040600 0x20>; |
6cecf916 | 147 | interrupts = <GIC_PPI 13 |
e7d9b270 | 148 | (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; |
885a8cfa | 149 | clocks = <&tegra_car TEGRA20_CLK_TWD>; |
73368ba0 SW |
150 | }; |
151 | ||
58ecb23f | 152 | intc: interrupt-controller@50041000 { |
0d4f7479 | 153 | compatible = "arm,cortex-a9-gic"; |
5ff48887 SW |
154 | reg = <0x50041000 0x1000 |
155 | 0x50040100 0x0100>; | |
2eaab06e SW |
156 | interrupt-controller; |
157 | #interrupt-cells = <3>; | |
870c81a4 | 158 | interrupt-parent = <&intc>; |
8e267f3d GL |
159 | }; |
160 | ||
58ecb23f | 161 | cache-controller@50043000 { |
bb2c1de9 SW |
162 | compatible = "arm,pl310-cache"; |
163 | reg = <0x50043000 0x1000>; | |
164 | arm,data-latency = <5 5 2>; | |
165 | arm,tag-latency = <4 4 2>; | |
166 | cache-unified; | |
167 | cache-level = <2>; | |
168 | }; | |
169 | ||
870c81a4 MZ |
170 | lic: interrupt-controller@60004000 { |
171 | compatible = "nvidia,tegra20-ictlr"; | |
172 | reg = <0x60004000 0x100>, | |
173 | <0x60004100 0x50>, | |
174 | <0x60004200 0x50>, | |
175 | <0x60004300 0x50>; | |
176 | interrupt-controller; | |
177 | #interrupt-cells = <3>; | |
178 | interrupt-parent = <&intc>; | |
179 | }; | |
180 | ||
2f2b7fb2 SW |
181 | timer@60005000 { |
182 | compatible = "nvidia,tegra20-timer"; | |
183 | reg = <0x60005000 0x60>; | |
6cecf916 SW |
184 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
185 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
186 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
187 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
885a8cfa | 188 | clocks = <&tegra_car TEGRA20_CLK_TIMER>; |
2f2b7fb2 SW |
189 | }; |
190 | ||
58ecb23f | 191 | tegra_car: clock@60006000 { |
270f8ce3 SW |
192 | compatible = "nvidia,tegra20-car"; |
193 | reg = <0x60006000 0x1000>; | |
194 | #clock-cells = <1>; | |
3393d422 | 195 | #reset-cells = <1>; |
270f8ce3 SW |
196 | }; |
197 | ||
b1023134 TR |
198 | flow-controller@60007000 { |
199 | compatible = "nvidia,tegra20-flowctrl"; | |
200 | reg = <0x60007000 0x1000>; | |
201 | }; | |
202 | ||
58ecb23f | 203 | apbdma: dma@6000a000 { |
8051b75a SW |
204 | compatible = "nvidia,tegra20-apbdma"; |
205 | reg = <0x6000a000 0x1200>; | |
6cecf916 SW |
206 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
207 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
208 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
209 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
210 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
211 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
212 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
213 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
214 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
215 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
216 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
217 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
218 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
219 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
220 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
221 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; | |
885a8cfa | 222 | clocks = <&tegra_car TEGRA20_CLK_APBDMA>; |
3393d422 SW |
223 | resets = <&tegra_car 34>; |
224 | reset-names = "dma"; | |
034d023f | 225 | #dma-cells = <1>; |
8051b75a SW |
226 | }; |
227 | ||
0d5ccb38 | 228 | ahb@6000c000 { |
c04abb3a | 229 | compatible = "nvidia,tegra20-ahb"; |
0d5ccb38 | 230 | reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ |
8e267f3d GL |
231 | }; |
232 | ||
58ecb23f | 233 | gpio: gpio@6000d000 { |
8e267f3d | 234 | compatible = "nvidia,tegra20-gpio"; |
95decf84 | 235 | reg = <0x6000d000 0x1000>; |
6cecf916 SW |
236 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
237 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
238 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
239 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
240 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
241 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
242 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
8e267f3d GL |
243 | #gpio-cells = <2>; |
244 | gpio-controller; | |
6f74dc9b SW |
245 | #interrupt-cells = <2>; |
246 | interrupt-controller; | |
4f1d8414 | 247 | /* |
17cdddf0 | 248 | gpio-ranges = <&pinmux 0 0 224>; |
4f1d8414 | 249 | */ |
8e267f3d GL |
250 | }; |
251 | ||
155dfc7b PDS |
252 | apbmisc@70000800 { |
253 | compatible = "nvidia,tegra20-apbmisc"; | |
254 | reg = <0x70000800 0x64 /* Chip revision */ | |
255 | 0x70000008 0x04>; /* Strapping options */ | |
256 | }; | |
257 | ||
58ecb23f | 258 | pinmux: pinmux@70000014 { |
f62f548c | 259 | compatible = "nvidia,tegra20-pinmux"; |
95decf84 SW |
260 | reg = <0x70000014 0x10 /* Tri-state registers */ |
261 | 0x70000080 0x20 /* Mux registers */ | |
262 | 0x700000a0 0x14 /* Pull-up/down registers */ | |
263 | 0x70000868 0xa8>; /* Pad control registers */ | |
f62f548c SW |
264 | }; |
265 | ||
58ecb23f | 266 | das@70000c00 { |
c04abb3a SW |
267 | compatible = "nvidia,tegra20-das"; |
268 | reg = <0x70000c00 0x80>; | |
269 | }; | |
fc5c306b | 270 | |
58ecb23f | 271 | tegra_ac97: ac97@70002000 { |
0698ed19 LS |
272 | compatible = "nvidia,tegra20-ac97"; |
273 | reg = <0x70002000 0x200>; | |
6cecf916 | 274 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 275 | clocks = <&tegra_car TEGRA20_CLK_AC97>; |
3393d422 SW |
276 | resets = <&tegra_car 3>; |
277 | reset-names = "ac97"; | |
034d023f SW |
278 | dmas = <&apbdma 12>, <&apbdma 12>; |
279 | dma-names = "rx", "tx"; | |
0698ed19 LS |
280 | status = "disabled"; |
281 | }; | |
c04abb3a SW |
282 | |
283 | tegra_i2s1: i2s@70002800 { | |
284 | compatible = "nvidia,tegra20-i2s"; | |
285 | reg = <0x70002800 0x200>; | |
6cecf916 | 286 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 287 | clocks = <&tegra_car TEGRA20_CLK_I2S1>; |
3393d422 SW |
288 | resets = <&tegra_car 11>; |
289 | reset-names = "i2s"; | |
034d023f SW |
290 | dmas = <&apbdma 2>, <&apbdma 2>; |
291 | dma-names = "rx", "tx"; | |
223ef78d | 292 | status = "disabled"; |
c04abb3a SW |
293 | }; |
294 | ||
295 | tegra_i2s2: i2s@70002a00 { | |
296 | compatible = "nvidia,tegra20-i2s"; | |
297 | reg = <0x70002a00 0x200>; | |
6cecf916 | 298 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 299 | clocks = <&tegra_car TEGRA20_CLK_I2S2>; |
3393d422 SW |
300 | resets = <&tegra_car 18>; |
301 | reset-names = "i2s"; | |
034d023f SW |
302 | dmas = <&apbdma 1>, <&apbdma 1>; |
303 | dma-names = "rx", "tx"; | |
223ef78d | 304 | status = "disabled"; |
c04abb3a SW |
305 | }; |
306 | ||
b6551bb9 LD |
307 | /* |
308 | * There are two serial driver i.e. 8250 based simple serial | |
309 | * driver and APB DMA based serial driver for higher baudrate | |
310 | * and performace. To enable the 8250 based driver, the compatible | |
311 | * is "nvidia,tegra20-uart" and to enable the APB DMA based serial | |
e1098248 | 312 | * driver, the compatible is "nvidia,tegra20-hsuart". |
b6551bb9 LD |
313 | */ |
314 | uarta: serial@70006000 { | |
8e267f3d GL |
315 | compatible = "nvidia,tegra20-uart"; |
316 | reg = <0x70006000 0x40>; | |
317 | reg-shift = <2>; | |
6cecf916 | 318 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 319 | clocks = <&tegra_car TEGRA20_CLK_UARTA>; |
3393d422 SW |
320 | resets = <&tegra_car 6>; |
321 | reset-names = "serial"; | |
034d023f SW |
322 | dmas = <&apbdma 8>, <&apbdma 8>; |
323 | dma-names = "rx", "tx"; | |
223ef78d | 324 | status = "disabled"; |
8e267f3d GL |
325 | }; |
326 | ||
b6551bb9 | 327 | uartb: serial@70006040 { |
8e267f3d GL |
328 | compatible = "nvidia,tegra20-uart"; |
329 | reg = <0x70006040 0x40>; | |
330 | reg-shift = <2>; | |
6cecf916 | 331 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 332 | clocks = <&tegra_car TEGRA20_CLK_UARTB>; |
3393d422 SW |
333 | resets = <&tegra_car 7>; |
334 | reset-names = "serial"; | |
034d023f SW |
335 | dmas = <&apbdma 9>, <&apbdma 9>; |
336 | dma-names = "rx", "tx"; | |
223ef78d | 337 | status = "disabled"; |
8e267f3d GL |
338 | }; |
339 | ||
b6551bb9 | 340 | uartc: serial@70006200 { |
8e267f3d GL |
341 | compatible = "nvidia,tegra20-uart"; |
342 | reg = <0x70006200 0x100>; | |
343 | reg-shift = <2>; | |
6cecf916 | 344 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 345 | clocks = <&tegra_car TEGRA20_CLK_UARTC>; |
3393d422 SW |
346 | resets = <&tegra_car 55>; |
347 | reset-names = "serial"; | |
034d023f SW |
348 | dmas = <&apbdma 10>, <&apbdma 10>; |
349 | dma-names = "rx", "tx"; | |
223ef78d | 350 | status = "disabled"; |
8e267f3d GL |
351 | }; |
352 | ||
b6551bb9 | 353 | uartd: serial@70006300 { |
8e267f3d GL |
354 | compatible = "nvidia,tegra20-uart"; |
355 | reg = <0x70006300 0x100>; | |
356 | reg-shift = <2>; | |
6cecf916 | 357 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 358 | clocks = <&tegra_car TEGRA20_CLK_UARTD>; |
3393d422 SW |
359 | resets = <&tegra_car 65>; |
360 | reset-names = "serial"; | |
034d023f SW |
361 | dmas = <&apbdma 19>, <&apbdma 19>; |
362 | dma-names = "rx", "tx"; | |
223ef78d | 363 | status = "disabled"; |
8e267f3d GL |
364 | }; |
365 | ||
b6551bb9 | 366 | uarte: serial@70006400 { |
8e267f3d GL |
367 | compatible = "nvidia,tegra20-uart"; |
368 | reg = <0x70006400 0x100>; | |
369 | reg-shift = <2>; | |
6cecf916 | 370 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 371 | clocks = <&tegra_car TEGRA20_CLK_UARTE>; |
3393d422 SW |
372 | resets = <&tegra_car 66>; |
373 | reset-names = "serial"; | |
034d023f SW |
374 | dmas = <&apbdma 20>, <&apbdma 20>; |
375 | dma-names = "rx", "tx"; | |
223ef78d | 376 | status = "disabled"; |
8e267f3d GL |
377 | }; |
378 | ||
58ecb23f | 379 | pwm: pwm@7000a000 { |
140fd977 TR |
380 | compatible = "nvidia,tegra20-pwm"; |
381 | reg = <0x7000a000 0x100>; | |
382 | #pwm-cells = <2>; | |
885a8cfa | 383 | clocks = <&tegra_car TEGRA20_CLK_PWM>; |
3393d422 SW |
384 | resets = <&tegra_car 17>; |
385 | reset-names = "pwm"; | |
b69cd984 | 386 | status = "disabled"; |
140fd977 TR |
387 | }; |
388 | ||
58ecb23f | 389 | rtc@7000e000 { |
380e04ac SW |
390 | compatible = "nvidia,tegra20-rtc"; |
391 | reg = <0x7000e000 0x100>; | |
6cecf916 | 392 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 393 | clocks = <&tegra_car TEGRA20_CLK_RTC>; |
380e04ac SW |
394 | }; |
395 | ||
c04abb3a | 396 | i2c@7000c000 { |
c04abb3a SW |
397 | compatible = "nvidia,tegra20-i2c"; |
398 | reg = <0x7000c000 0x100>; | |
6cecf916 | 399 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
400 | #address-cells = <1>; |
401 | #size-cells = <0>; | |
885a8cfa HD |
402 | clocks = <&tegra_car TEGRA20_CLK_I2C1>, |
403 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 404 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
405 | resets = <&tegra_car 12>; |
406 | reset-names = "i2c"; | |
034d023f SW |
407 | dmas = <&apbdma 21>, <&apbdma 21>; |
408 | dma-names = "rx", "tx"; | |
223ef78d | 409 | status = "disabled"; |
0c6700ab OJ |
410 | }; |
411 | ||
fa98a114 LD |
412 | spi@7000c380 { |
413 | compatible = "nvidia,tegra20-sflash"; | |
414 | reg = <0x7000c380 0x80>; | |
6cecf916 | 415 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
fa98a114 LD |
416 | #address-cells = <1>; |
417 | #size-cells = <0>; | |
885a8cfa | 418 | clocks = <&tegra_car TEGRA20_CLK_SPI>; |
3393d422 SW |
419 | resets = <&tegra_car 43>; |
420 | reset-names = "spi"; | |
034d023f SW |
421 | dmas = <&apbdma 11>, <&apbdma 11>; |
422 | dma-names = "rx", "tx"; | |
fa98a114 LD |
423 | status = "disabled"; |
424 | }; | |
425 | ||
c04abb3a | 426 | i2c@7000c400 { |
c04abb3a SW |
427 | compatible = "nvidia,tegra20-i2c"; |
428 | reg = <0x7000c400 0x100>; | |
6cecf916 | 429 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
430 | #address-cells = <1>; |
431 | #size-cells = <0>; | |
885a8cfa HD |
432 | clocks = <&tegra_car TEGRA20_CLK_I2C2>, |
433 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 434 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
435 | resets = <&tegra_car 54>; |
436 | reset-names = "i2c"; | |
034d023f SW |
437 | dmas = <&apbdma 22>, <&apbdma 22>; |
438 | dma-names = "rx", "tx"; | |
223ef78d | 439 | status = "disabled"; |
8e267f3d GL |
440 | }; |
441 | ||
c04abb3a | 442 | i2c@7000c500 { |
c04abb3a SW |
443 | compatible = "nvidia,tegra20-i2c"; |
444 | reg = <0x7000c500 0x100>; | |
6cecf916 | 445 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
446 | #address-cells = <1>; |
447 | #size-cells = <0>; | |
885a8cfa HD |
448 | clocks = <&tegra_car TEGRA20_CLK_I2C3>, |
449 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 450 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
451 | resets = <&tegra_car 67>; |
452 | reset-names = "i2c"; | |
034d023f SW |
453 | dmas = <&apbdma 23>, <&apbdma 23>; |
454 | dma-names = "rx", "tx"; | |
223ef78d | 455 | status = "disabled"; |
8e267f3d GL |
456 | }; |
457 | ||
c04abb3a | 458 | i2c@7000d000 { |
c04abb3a SW |
459 | compatible = "nvidia,tegra20-i2c-dvc"; |
460 | reg = <0x7000d000 0x200>; | |
6cecf916 | 461 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
462 | #address-cells = <1>; |
463 | #size-cells = <0>; | |
885a8cfa HD |
464 | clocks = <&tegra_car TEGRA20_CLK_DVC>, |
465 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 466 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
467 | resets = <&tegra_car 47>; |
468 | reset-names = "i2c"; | |
034d023f SW |
469 | dmas = <&apbdma 24>, <&apbdma 24>; |
470 | dma-names = "rx", "tx"; | |
223ef78d | 471 | status = "disabled"; |
8e267f3d GL |
472 | }; |
473 | ||
a86b0db3 LD |
474 | spi@7000d400 { |
475 | compatible = "nvidia,tegra20-slink"; | |
476 | reg = <0x7000d400 0x200>; | |
6cecf916 | 477 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
478 | #address-cells = <1>; |
479 | #size-cells = <0>; | |
885a8cfa | 480 | clocks = <&tegra_car TEGRA20_CLK_SBC1>; |
3393d422 SW |
481 | resets = <&tegra_car 41>; |
482 | reset-names = "spi"; | |
034d023f SW |
483 | dmas = <&apbdma 15>, <&apbdma 15>; |
484 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
485 | status = "disabled"; |
486 | }; | |
487 | ||
488 | spi@7000d600 { | |
489 | compatible = "nvidia,tegra20-slink"; | |
490 | reg = <0x7000d600 0x200>; | |
6cecf916 | 491 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
492 | #address-cells = <1>; |
493 | #size-cells = <0>; | |
885a8cfa | 494 | clocks = <&tegra_car TEGRA20_CLK_SBC2>; |
3393d422 SW |
495 | resets = <&tegra_car 44>; |
496 | reset-names = "spi"; | |
034d023f SW |
497 | dmas = <&apbdma 16>, <&apbdma 16>; |
498 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
499 | status = "disabled"; |
500 | }; | |
501 | ||
502 | spi@7000d800 { | |
503 | compatible = "nvidia,tegra20-slink"; | |
57471c8d | 504 | reg = <0x7000d800 0x200>; |
6cecf916 | 505 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
506 | #address-cells = <1>; |
507 | #size-cells = <0>; | |
885a8cfa | 508 | clocks = <&tegra_car TEGRA20_CLK_SBC3>; |
3393d422 SW |
509 | resets = <&tegra_car 46>; |
510 | reset-names = "spi"; | |
034d023f SW |
511 | dmas = <&apbdma 17>, <&apbdma 17>; |
512 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
513 | status = "disabled"; |
514 | }; | |
515 | ||
516 | spi@7000da00 { | |
517 | compatible = "nvidia,tegra20-slink"; | |
518 | reg = <0x7000da00 0x200>; | |
6cecf916 | 519 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
520 | #address-cells = <1>; |
521 | #size-cells = <0>; | |
885a8cfa | 522 | clocks = <&tegra_car TEGRA20_CLK_SBC4>; |
3393d422 SW |
523 | resets = <&tegra_car 68>; |
524 | reset-names = "spi"; | |
034d023f SW |
525 | dmas = <&apbdma 18>, <&apbdma 18>; |
526 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
527 | status = "disabled"; |
528 | }; | |
529 | ||
58ecb23f | 530 | kbc@7000e200 { |
699ed4b9 LD |
531 | compatible = "nvidia,tegra20-kbc"; |
532 | reg = <0x7000e200 0x100>; | |
6cecf916 | 533 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 534 | clocks = <&tegra_car TEGRA20_CLK_KBC>; |
3393d422 SW |
535 | resets = <&tegra_car 36>; |
536 | reset-names = "kbc"; | |
699ed4b9 LD |
537 | status = "disabled"; |
538 | }; | |
539 | ||
58ecb23f | 540 | pmc@7000e400 { |
c04abb3a SW |
541 | compatible = "nvidia,tegra20-pmc"; |
542 | reg = <0x7000e400 0x400>; | |
885a8cfa | 543 | clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; |
7021d122 | 544 | clock-names = "pclk", "clk32k_in"; |
c04abb3a SW |
545 | }; |
546 | ||
bbfc33bd | 547 | memory-controller@7000f000 { |
c04abb3a SW |
548 | compatible = "nvidia,tegra20-mc"; |
549 | reg = <0x7000f000 0x024 | |
550 | 0x7000f03c 0x3c4>; | |
6cecf916 | 551 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
c04abb3a SW |
552 | }; |
553 | ||
58ecb23f | 554 | iommu@7000f024 { |
c04abb3a SW |
555 | compatible = "nvidia,tegra20-gart"; |
556 | reg = <0x7000f024 0x00000018 /* controller registers */ | |
557 | 0x58000000 0x02000000>; /* GART aperture */ | |
558 | }; | |
559 | ||
bbfc33bd | 560 | memory-controller@7000f400 { |
c04abb3a SW |
561 | compatible = "nvidia,tegra20-emc"; |
562 | reg = <0x7000f400 0x200>; | |
2eaab06e SW |
563 | #address-cells = <1>; |
564 | #size-cells = <0>; | |
8e267f3d | 565 | }; |
c27317c0 | 566 | |
155dfc7b PDS |
567 | fuse@7000f800 { |
568 | compatible = "nvidia,tegra20-efuse"; | |
5431b0fd | 569 | reg = <0x7000f800 0x400>; |
155dfc7b PDS |
570 | clocks = <&tegra_car TEGRA20_CLK_FUSE>; |
571 | clock-names = "fuse"; | |
572 | resets = <&tegra_car 39>; | |
573 | reset-names = "fuse"; | |
574 | }; | |
575 | ||
58ecb23f | 576 | pcie-controller@80003000 { |
1b62b611 TR |
577 | compatible = "nvidia,tegra20-pcie"; |
578 | device_type = "pci"; | |
579 | reg = <0x80003000 0x00000800 /* PADS registers */ | |
580 | 0x80003800 0x00000200 /* AFI registers */ | |
581 | 0x90000000 0x10000000>; /* configuration space */ | |
582 | reg-names = "pads", "afi", "cs"; | |
583 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ | |
584 | GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ | |
585 | interrupt-names = "intr", "msi"; | |
586 | ||
97070bd4 LS |
587 | #interrupt-cells = <1>; |
588 | interrupt-map-mask = <0 0 0 0>; | |
589 | interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
590 | ||
1b62b611 TR |
591 | bus-range = <0x00 0xff>; |
592 | #address-cells = <3>; | |
593 | #size-cells = <2>; | |
594 | ||
595 | ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ | |
596 | 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ | |
597 | 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ | |
d7283c11 JA |
598 | 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ |
599 | 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ | |
1b62b611 TR |
600 | |
601 | clocks = <&tegra_car TEGRA20_CLK_PEX>, | |
602 | <&tegra_car TEGRA20_CLK_AFI>, | |
1b62b611 | 603 | <&tegra_car TEGRA20_CLK_PLL_E>; |
2bd541ff | 604 | clock-names = "pex", "afi", "pll_e"; |
3393d422 | 605 | resets = <&tegra_car 70>, |
d8b316b2 MZ |
606 | <&tegra_car 72>, |
607 | <&tegra_car 74>; | |
3393d422 | 608 | reset-names = "pex", "afi", "pcie_x"; |
1b62b611 TR |
609 | status = "disabled"; |
610 | ||
611 | pci@1,0 { | |
612 | device_type = "pci"; | |
613 | assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; | |
614 | reg = <0x000800 0 0 0 0>; | |
615 | status = "disabled"; | |
616 | ||
617 | #address-cells = <3>; | |
618 | #size-cells = <2>; | |
619 | ranges; | |
620 | ||
621 | nvidia,num-lanes = <2>; | |
622 | }; | |
623 | ||
624 | pci@2,0 { | |
625 | device_type = "pci"; | |
626 | assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; | |
627 | reg = <0x001000 0 0 0 0>; | |
628 | status = "disabled"; | |
629 | ||
630 | #address-cells = <3>; | |
631 | #size-cells = <2>; | |
632 | ranges; | |
633 | ||
634 | nvidia,num-lanes = <2>; | |
635 | }; | |
636 | }; | |
637 | ||
c27317c0 OJ |
638 | usb@c5000000 { |
639 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
640 | reg = <0xc5000000 0x4000>; | |
6cecf916 | 641 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
c27317c0 | 642 | phy_type = "utmi"; |
ba202f15 | 643 | nvidia,has-legacy-mode; |
885a8cfa | 644 | clocks = <&tegra_car TEGRA20_CLK_USBD>; |
3393d422 SW |
645 | resets = <&tegra_car 22>; |
646 | reset-names = "usb"; | |
b4e07478 | 647 | nvidia,needs-double-reset; |
e374b65c | 648 | nvidia,phy = <&phy1>; |
223ef78d | 649 | status = "disabled"; |
c27317c0 OJ |
650 | }; |
651 | ||
4c94c8b5 | 652 | phy1: usb-phy@c5000000 { |
5d324410 | 653 | compatible = "nvidia,tegra20-usb-phy"; |
4c94c8b5 | 654 | reg = <0xc5000000 0x4000 0xc5000000 0x4000>; |
5d324410 | 655 | phy_type = "utmi"; |
885a8cfa HD |
656 | clocks = <&tegra_car TEGRA20_CLK_USBD>, |
657 | <&tegra_car TEGRA20_CLK_PLL_U>, | |
658 | <&tegra_car TEGRA20_CLK_CLK_M>, | |
659 | <&tegra_car TEGRA20_CLK_USBD>; | |
4c94c8b5 | 660 | clock-names = "reg", "pll_u", "timer", "utmi-pads"; |
308efde2 TT |
661 | resets = <&tegra_car 22>, <&tegra_car 22>; |
662 | reset-names = "usb", "utmi-pads"; | |
5d324410 | 663 | nvidia,has-legacy-mode; |
c49667e5 MP |
664 | nvidia,hssync-start-delay = <9>; |
665 | nvidia,idle-wait-delay = <17>; | |
666 | nvidia,elastic-limit = <16>; | |
667 | nvidia,term-range-adj = <6>; | |
668 | nvidia,xcvr-setup = <9>; | |
669 | nvidia,xcvr-lsfslew = <1>; | |
670 | nvidia,xcvr-lsrslew = <1>; | |
308efde2 | 671 | nvidia,has-utmi-pad-registers; |
4c94c8b5 | 672 | status = "disabled"; |
5d324410 SW |
673 | }; |
674 | ||
c27317c0 OJ |
675 | usb@c5004000 { |
676 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
677 | reg = <0xc5004000 0x4000>; | |
6cecf916 | 678 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
c27317c0 | 679 | phy_type = "ulpi"; |
885a8cfa | 680 | clocks = <&tegra_car TEGRA20_CLK_USB2>; |
3393d422 SW |
681 | resets = <&tegra_car 58>; |
682 | reset-names = "usb"; | |
e374b65c | 683 | nvidia,phy = <&phy2>; |
223ef78d | 684 | status = "disabled"; |
c27317c0 OJ |
685 | }; |
686 | ||
4c94c8b5 | 687 | phy2: usb-phy@c5004000 { |
5d324410 | 688 | compatible = "nvidia,tegra20-usb-phy"; |
4c94c8b5 | 689 | reg = <0xc5004000 0x4000>; |
5d324410 | 690 | phy_type = "ulpi"; |
885a8cfa HD |
691 | clocks = <&tegra_car TEGRA20_CLK_USB2>, |
692 | <&tegra_car TEGRA20_CLK_PLL_U>, | |
693 | <&tegra_car TEGRA20_CLK_CDEV2>; | |
4c94c8b5 | 694 | clock-names = "reg", "pll_u", "ulpi-link"; |
308efde2 TT |
695 | resets = <&tegra_car 58>, <&tegra_car 22>; |
696 | reset-names = "usb", "utmi-pads"; | |
4c94c8b5 | 697 | status = "disabled"; |
5d324410 SW |
698 | }; |
699 | ||
c27317c0 OJ |
700 | usb@c5008000 { |
701 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
702 | reg = <0xc5008000 0x4000>; | |
6cecf916 | 703 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
c27317c0 | 704 | phy_type = "utmi"; |
885a8cfa | 705 | clocks = <&tegra_car TEGRA20_CLK_USB3>; |
3393d422 SW |
706 | resets = <&tegra_car 59>; |
707 | reset-names = "usb"; | |
e374b65c | 708 | nvidia,phy = <&phy3>; |
223ef78d | 709 | status = "disabled"; |
c27317c0 | 710 | }; |
7868a9bc | 711 | |
4c94c8b5 | 712 | phy3: usb-phy@c5008000 { |
5d324410 | 713 | compatible = "nvidia,tegra20-usb-phy"; |
4c94c8b5 | 714 | reg = <0xc5008000 0x4000 0xc5000000 0x4000>; |
5d324410 | 715 | phy_type = "utmi"; |
885a8cfa HD |
716 | clocks = <&tegra_car TEGRA20_CLK_USB3>, |
717 | <&tegra_car TEGRA20_CLK_PLL_U>, | |
718 | <&tegra_car TEGRA20_CLK_CLK_M>, | |
719 | <&tegra_car TEGRA20_CLK_USBD>; | |
4c94c8b5 | 720 | clock-names = "reg", "pll_u", "timer", "utmi-pads"; |
308efde2 TT |
721 | resets = <&tegra_car 59>, <&tegra_car 22>; |
722 | reset-names = "usb", "utmi-pads"; | |
c49667e5 MP |
723 | nvidia,hssync-start-delay = <9>; |
724 | nvidia,idle-wait-delay = <17>; | |
725 | nvidia,elastic-limit = <16>; | |
726 | nvidia,term-range-adj = <6>; | |
727 | nvidia,xcvr-setup = <9>; | |
728 | nvidia,xcvr-lsfslew = <2>; | |
729 | nvidia,xcvr-lsrslew = <2>; | |
4c94c8b5 | 730 | status = "disabled"; |
5d324410 SW |
731 | }; |
732 | ||
c04abb3a SW |
733 | sdhci@c8000000 { |
734 | compatible = "nvidia,tegra20-sdhci"; | |
735 | reg = <0xc8000000 0x200>; | |
6cecf916 | 736 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 737 | clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; |
3393d422 SW |
738 | resets = <&tegra_car 14>; |
739 | reset-names = "sdhci"; | |
223ef78d | 740 | status = "disabled"; |
7868a9bc | 741 | }; |
4a82f2b3 | 742 | |
c04abb3a SW |
743 | sdhci@c8000200 { |
744 | compatible = "nvidia,tegra20-sdhci"; | |
745 | reg = <0xc8000200 0x200>; | |
6cecf916 | 746 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 747 | clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; |
3393d422 SW |
748 | resets = <&tegra_car 9>; |
749 | reset-names = "sdhci"; | |
223ef78d | 750 | status = "disabled"; |
4a82f2b3 | 751 | }; |
6a943e0e | 752 | |
c04abb3a SW |
753 | sdhci@c8000400 { |
754 | compatible = "nvidia,tegra20-sdhci"; | |
755 | reg = <0xc8000400 0x200>; | |
6cecf916 | 756 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 757 | clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; |
3393d422 SW |
758 | resets = <&tegra_car 69>; |
759 | reset-names = "sdhci"; | |
223ef78d | 760 | status = "disabled"; |
c04abb3a SW |
761 | }; |
762 | ||
763 | sdhci@c8000600 { | |
764 | compatible = "nvidia,tegra20-sdhci"; | |
765 | reg = <0xc8000600 0x200>; | |
6cecf916 | 766 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 767 | clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; |
3393d422 SW |
768 | resets = <&tegra_car 15>; |
769 | reset-names = "sdhci"; | |
223ef78d | 770 | status = "disabled"; |
c04abb3a SW |
771 | }; |
772 | ||
4dd2bd37 HD |
773 | cpus { |
774 | #address-cells = <1>; | |
775 | #size-cells = <0>; | |
776 | ||
777 | cpu@0 { | |
778 | device_type = "cpu"; | |
779 | compatible = "arm,cortex-a9"; | |
780 | reg = <0>; | |
781 | }; | |
782 | ||
783 | cpu@1 { | |
784 | device_type = "cpu"; | |
785 | compatible = "arm,cortex-a9"; | |
786 | reg = <1>; | |
787 | }; | |
788 | }; | |
789 | ||
c04abb3a SW |
790 | pmu { |
791 | compatible = "arm,cortex-a9-pmu"; | |
6cecf916 SW |
792 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
793 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
6a943e0e | 794 | }; |
8e267f3d | 795 | }; |