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Merge remote-tracking branches 'regulator/fix/as3722', 'regulator/fix/ltc3589' and...
[deliverable/linux.git] / arch / arm / boot / dts / tegra20.dtsi
CommitLineData
885a8cfa 1#include <dt-bindings/clock/tegra20-car.h>
3325f1bc 2#include <dt-bindings/gpio/tegra-gpio.h>
ba4104e7 3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 4#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 5
1bd0bd49 6#include "skeleton.dtsi"
8e267f3d
GL		 7
8/ {
9 compatible = "nvidia,tegra20";
10 interrupt-parent = <&intc>;
11
b6551bb9
LD		 12 aliases {
13 serial0 = &uarta;
14 serial1 = &uartb;
15 serial2 = &uartc;
16 serial3 = &uartd;
17 serial4 = &uarte;
18 };
19
58ecb23f 20 host1x@50000000 {
ed821f07
TR		 21 compatible = "nvidia,tegra20-host1x", "simple-bus";
22 reg = <0x50000000 0x00024000>;
6cecf916
SW		 23 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
24 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
885a8cfa 25 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
3393d422
SW		 26 resets = <&tegra_car 28>;
27 reset-names = "host1x";
ed821f07
TR		 28
29 #address-cells = <1>;
30 #size-cells = <1>;
31
32 ranges = <0x54000000 0x54000000 0x04000000>;
33
58ecb23f 34 mpe@54040000 {
ed821f07
TR		 35 compatible = "nvidia,tegra20-mpe";
36 reg = <0x54040000 0x00040000>;
6cecf916 37 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 38 clocks = <&tegra_car TEGRA20_CLK_MPE>;
3393d422
SW		 39 resets = <&tegra_car 60>;
40 reset-names = "mpe";
ed821f07
TR		 41 };
42
58ecb23f 43 vi@54080000 {
ed821f07
TR		 44 compatible = "nvidia,tegra20-vi";
45 reg = <0x54080000 0x00040000>;
6cecf916 46 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 47 clocks = <&tegra_car TEGRA20_CLK_VI>;
3393d422
SW		 48 resets = <&tegra_car 20>;
49 reset-names = "vi";
ed821f07
TR		 50 };
51
58ecb23f 52 epp@540c0000 {
ed821f07
TR		 53 compatible = "nvidia,tegra20-epp";
54 reg = <0x540c0000 0x00040000>;
6cecf916 55 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 56 clocks = <&tegra_car TEGRA20_CLK_EPP>;
3393d422
SW		 57 resets = <&tegra_car 19>;
58 reset-names = "epp";
ed821f07
TR		 59 };
60
58ecb23f 61 isp@54100000 {
ed821f07
TR		 62 compatible = "nvidia,tegra20-isp";
63 reg = <0x54100000 0x00040000>;
6cecf916 64 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 65 clocks = <&tegra_car TEGRA20_CLK_ISP>;
3393d422
SW		 66 resets = <&tegra_car 23>;
67 reset-names = "isp";
ed821f07
TR		 68 };
69
58ecb23f 70 gr2d@54140000 {
ed821f07
TR		 71 compatible = "nvidia,tegra20-gr2d";
72 reg = <0x54140000 0x00040000>;
6cecf916 73 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 74 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
3393d422
SW		 75 resets = <&tegra_car 21>;
76 reset-names = "2d";
ed821f07
TR		 77 };
78
58ecb23f 79 gr3d@54140000 {
ed821f07 80 compatible = "nvidia,tegra20-gr3d";
58ecb23f 81 reg = <0x54140000 0x00040000>;
885a8cfa 82 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
3393d422
SW		 83 resets = <&tegra_car 24>;
84 reset-names = "3d";
ed821f07
TR		 85 };
86
87 dc@54200000 {
88 compatible = "nvidia,tegra20-dc";
89 reg = <0x54200000 0x00040000>;
6cecf916 90 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 91 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
92 <&tegra_car TEGRA20_CLK_PLL_P>;
d8f64797 93 clock-names = "dc", "parent";
3393d422
SW		 94 resets = <&tegra_car 27>;
95 reset-names = "dc";
ed821f07 96
688b56b4
TR		 97 nvidia,head = <0>;
98
ed821f07
TR		 99 rgb {
100 status = "disabled";
101 };
102 };
103
104 dc@54240000 {
105 compatible = "nvidia,tegra20-dc";
106 reg = <0x54240000 0x00040000>;
6cecf916 107 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 108 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
109 <&tegra_car TEGRA20_CLK_PLL_P>;
d8f64797 110 clock-names = "dc", "parent";
3393d422
SW		 111 resets = <&tegra_car 26>;
112 reset-names = "dc";
ed821f07 113
688b56b4
TR		 114 nvidia,head = <1>;
115
ed821f07
TR		 116 rgb {
117 status = "disabled";
118 };
119 };
120
58ecb23f 121 hdmi@54280000 {
ed821f07
TR		 122 compatible = "nvidia,tegra20-hdmi";
123 reg = <0x54280000 0x00040000>;
6cecf916 124 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 125 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
126 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
8d8b43da 127 clock-names = "hdmi", "parent";
3393d422
SW		 128 resets = <&tegra_car 51>;
129 reset-names = "hdmi";
ed821f07
TR		 130 status = "disabled";
131 };
132
58ecb23f 133 tvo@542c0000 {
ed821f07
TR		 134 compatible = "nvidia,tegra20-tvo";
135 reg = <0x542c0000 0x00040000>;
6cecf916 136 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 137 clocks = <&tegra_car TEGRA20_CLK_TVO>;
ed821f07
TR		 138 status = "disabled";
139 };
140
58ecb23f 141 dsi@542c0000 {
ed821f07 142 compatible = "nvidia,tegra20-dsi";
58ecb23f 143 reg = <0x542c0000 0x00040000>;
885a8cfa 144 clocks = <&tegra_car TEGRA20_CLK_DSI>;
3393d422
SW		 145 resets = <&tegra_car 48>;
146 reset-names = "dsi";
ed821f07
TR		 147 status = "disabled";
148 };
149 };
150
73368ba0
SW		 151 timer@50004600 {
152 compatible = "arm,cortex-a9-twd-timer";
153 reg = <0x50040600 0x20>;
6cecf916
SW		 154 interrupts = <GIC_PPI 13
155 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
885a8cfa 156 clocks = <&tegra_car TEGRA20_CLK_TWD>;
73368ba0
SW		 157 };
158
58ecb23f 159 intc: interrupt-controller@50041000 {
0d4f7479 160 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 161 reg = <0x50041000 0x1000
162 0x50040100 0x0100>;
2eaab06e
SW		 163 interrupt-controller;
164 #interrupt-cells = <3>;
8e267f3d
GL		 165 };
166
58ecb23f 167 cache-controller@50043000 {
bb2c1de9
SW		 168 compatible = "arm,pl310-cache";
169 reg = <0x50043000 0x1000>;
170 arm,data-latency = <5 5 2>;
171 arm,tag-latency = <4 4 2>;
172 cache-unified;
173 cache-level = <2>;
174 };
175
2f2b7fb2
SW		 176 timer@60005000 {
177 compatible = "nvidia,tegra20-timer";
178 reg = <0x60005000 0x60>;
6cecf916
SW		 179 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 183 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
2f2b7fb2
SW		 184 };
185
58ecb23f 186 tegra_car: clock@60006000 {
270f8ce3
SW		 187 compatible = "nvidia,tegra20-car";
188 reg = <0x60006000 0x1000>;
189 #clock-cells = <1>;
3393d422 190 #reset-cells = <1>;
270f8ce3
SW		 191 };
192
58ecb23f 193 apbdma: dma@6000a000 {
8051b75a
SW		 194 compatible = "nvidia,tegra20-apbdma";
195 reg = <0x6000a000 0x1200>;
6cecf916
SW		 196 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 212 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
3393d422
SW		 213 resets = <&tegra_car 34>;
214 reset-names = "dma";
034d023f 215 #dma-cells = <1>;
8051b75a
SW		 216 };
217
58ecb23f 218 ahb@6000c004 {
c04abb3a
SW		 219 compatible = "nvidia,tegra20-ahb";
220 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
8e267f3d
GL		 221 };
222
58ecb23f 223 gpio: gpio@6000d000 {
8e267f3d 224 compatible = "nvidia,tegra20-gpio";
95decf84 225 reg = <0x6000d000 0x1000>;
6cecf916
SW		 226 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
8e267f3d
GL		 233 #gpio-cells = <2>;
234 gpio-controller;
6f74dc9b
SW		 235 #interrupt-cells = <2>;
236 interrupt-controller;
8e267f3d
GL		 237 };
238
58ecb23f 239 pinmux: pinmux@70000014 {
f62f548c 240 compatible = "nvidia,tegra20-pinmux";
95decf84
SW		 241 reg = <0x70000014 0x10 /* Tri-state registers */
242 0x70000080 0x20 /* Mux registers */
243 0x700000a0 0x14 /* Pull-up/down registers */
244 0x70000868 0xa8>; /* Pad control registers */
f62f548c
SW		 245 };
246
58ecb23f 247 das@70000c00 {
c04abb3a
SW		 248 compatible = "nvidia,tegra20-das";
249 reg = <0x70000c00 0x80>;
250 };
fc5c306b 251
58ecb23f 252 tegra_ac97: ac97@70002000 {
0698ed19
LS		 253 compatible = "nvidia,tegra20-ac97";
254 reg = <0x70002000 0x200>;
6cecf916 255 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 256 clocks = <&tegra_car TEGRA20_CLK_AC97>;
3393d422
SW		 257 resets = <&tegra_car 3>;
258 reset-names = "ac97";
034d023f
SW		 259 dmas = <&apbdma 12>, <&apbdma 12>;
260 dma-names = "rx", "tx";
0698ed19
LS		 261 status = "disabled";
262 };
c04abb3a
SW		 263
264 tegra_i2s1: i2s@70002800 {
265 compatible = "nvidia,tegra20-i2s";
266 reg = <0x70002800 0x200>;
6cecf916 267 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 268 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
3393d422
SW		 269 resets = <&tegra_car 11>;
270 reset-names = "i2s";
034d023f
SW		 271 dmas = <&apbdma 2>, <&apbdma 2>;
272 dma-names = "rx", "tx";
223ef78d 273 status = "disabled";
c04abb3a
SW		 274 };
275
276 tegra_i2s2: i2s@70002a00 {
277 compatible = "nvidia,tegra20-i2s";
278 reg = <0x70002a00 0x200>;
6cecf916 279 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 280 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
3393d422
SW		 281 resets = <&tegra_car 18>;
282 reset-names = "i2s";
034d023f
SW		 283 dmas = <&apbdma 1>, <&apbdma 1>;
284 dma-names = "rx", "tx";
223ef78d 285 status = "disabled";
c04abb3a
SW		 286 };
287
b6551bb9
LD		 288 /*
289 * There are two serial driver i.e. 8250 based simple serial
290 * driver and APB DMA based serial driver for higher baudrate
291 * and performace. To enable the 8250 based driver, the compatible
292 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
293 * driver, the comptible is "nvidia,tegra20-hsuart".
294 */
295 uarta: serial@70006000 {
8e267f3d
GL		 296 compatible = "nvidia,tegra20-uart";
297 reg = <0x70006000 0x40>;
298 reg-shift = <2>;
6cecf916 299 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 300 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
3393d422
SW		 301 resets = <&tegra_car 6>;
302 reset-names = "serial";
034d023f
SW		 303 dmas = <&apbdma 8>, <&apbdma 8>;
304 dma-names = "rx", "tx";
223ef78d 305 status = "disabled";
8e267f3d
GL		 306 };
307
b6551bb9 308 uartb: serial@70006040 {
8e267f3d
GL		 309 compatible = "nvidia,tegra20-uart";
310 reg = <0x70006040 0x40>;
311 reg-shift = <2>;
6cecf916 312 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 313 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
3393d422
SW		 314 resets = <&tegra_car 7>;
315 reset-names = "serial";
034d023f
SW		 316 dmas = <&apbdma 9>, <&apbdma 9>;
317 dma-names = "rx", "tx";
223ef78d 318 status = "disabled";
8e267f3d
GL		 319 };
320
b6551bb9 321 uartc: serial@70006200 {
8e267f3d
GL		 322 compatible = "nvidia,tegra20-uart";
323 reg = <0x70006200 0x100>;
324 reg-shift = <2>;
6cecf916 325 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 326 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
3393d422
SW		 327 resets = <&tegra_car 55>;
328 reset-names = "serial";
034d023f
SW		 329 dmas = <&apbdma 10>, <&apbdma 10>;
330 dma-names = "rx", "tx";
223ef78d 331 status = "disabled";
8e267f3d
GL		 332 };
333
b6551bb9 334 uartd: serial@70006300 {
8e267f3d
GL		 335 compatible = "nvidia,tegra20-uart";
336 reg = <0x70006300 0x100>;
337 reg-shift = <2>;
6cecf916 338 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 339 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
3393d422
SW		 340 resets = <&tegra_car 65>;
341 reset-names = "serial";
034d023f
SW		 342 dmas = <&apbdma 19>, <&apbdma 19>;
343 dma-names = "rx", "tx";
223ef78d 344 status = "disabled";
8e267f3d
GL		 345 };
346
b6551bb9 347 uarte: serial@70006400 {
8e267f3d
GL		 348 compatible = "nvidia,tegra20-uart";
349 reg = <0x70006400 0x100>;
350 reg-shift = <2>;
6cecf916 351 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 352 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
3393d422
SW		 353 resets = <&tegra_car 66>;
354 reset-names = "serial";
034d023f
SW		 355 dmas = <&apbdma 20>, <&apbdma 20>;
356 dma-names = "rx", "tx";
223ef78d 357 status = "disabled";
8e267f3d
GL		 358 };
359
58ecb23f 360 pwm: pwm@7000a000 {
140fd977
TR		 361 compatible = "nvidia,tegra20-pwm";
362 reg = <0x7000a000 0x100>;
363 #pwm-cells = <2>;
885a8cfa 364 clocks = <&tegra_car TEGRA20_CLK_PWM>;
3393d422
SW		 365 resets = <&tegra_car 17>;
366 reset-names = "pwm";
b69cd984 367 status = "disabled";
140fd977
TR		 368 };
369
58ecb23f 370 rtc@7000e000 {
380e04ac
SW		 371 compatible = "nvidia,tegra20-rtc";
372 reg = <0x7000e000 0x100>;
6cecf916 373 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 374 clocks = <&tegra_car TEGRA20_CLK_RTC>;
380e04ac
SW		 375 };
376
c04abb3a 377 i2c@7000c000 {
c04abb3a
SW		 378 compatible = "nvidia,tegra20-i2c";
379 reg = <0x7000c000 0x100>;
6cecf916 380 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 381 #address-cells = <1>;
382 #size-cells = <0>;
885a8cfa
HD		 383 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
384 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 385 clock-names = "div-clk", "fast-clk";
3393d422
SW		 386 resets = <&tegra_car 12>;
387 reset-names = "i2c";
034d023f
SW		 388 dmas = <&apbdma 21>, <&apbdma 21>;
389 dma-names = "rx", "tx";
223ef78d 390 status = "disabled";
0c6700ab
OJ		 391 };
392
fa98a114
LD		 393 spi@7000c380 {
394 compatible = "nvidia,tegra20-sflash";
395 reg = <0x7000c380 0x80>;
6cecf916 396 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
fa98a114
LD		 397 #address-cells = <1>;
398 #size-cells = <0>;
885a8cfa 399 clocks = <&tegra_car TEGRA20_CLK_SPI>;
3393d422
SW		 400 resets = <&tegra_car 43>;
401 reset-names = "spi";
034d023f
SW		 402 dmas = <&apbdma 11>, <&apbdma 11>;
403 dma-names = "rx", "tx";
fa98a114
LD		 404 status = "disabled";
405 };
406
c04abb3a 407 i2c@7000c400 {
c04abb3a
SW		 408 compatible = "nvidia,tegra20-i2c";
409 reg = <0x7000c400 0x100>;
6cecf916 410 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 411 #address-cells = <1>;
412 #size-cells = <0>;
885a8cfa
HD		 413 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
414 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 415 clock-names = "div-clk", "fast-clk";
3393d422
SW		 416 resets = <&tegra_car 54>;
417 reset-names = "i2c";
034d023f
SW		 418 dmas = <&apbdma 22>, <&apbdma 22>;
419 dma-names = "rx", "tx";
223ef78d 420 status = "disabled";
8e267f3d
GL		 421 };
422
c04abb3a 423 i2c@7000c500 {
c04abb3a
SW		 424 compatible = "nvidia,tegra20-i2c";
425 reg = <0x7000c500 0x100>;
6cecf916 426 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 427 #address-cells = <1>;
428 #size-cells = <0>;
885a8cfa
HD		 429 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
430 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 431 clock-names = "div-clk", "fast-clk";
3393d422
SW		 432 resets = <&tegra_car 67>;
433 reset-names = "i2c";
034d023f
SW		 434 dmas = <&apbdma 23>, <&apbdma 23>;
435 dma-names = "rx", "tx";
223ef78d 436 status = "disabled";
8e267f3d
GL		 437 };
438
c04abb3a 439 i2c@7000d000 {
c04abb3a
SW		 440 compatible = "nvidia,tegra20-i2c-dvc";
441 reg = <0x7000d000 0x200>;
6cecf916 442 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 443 #address-cells = <1>;
444 #size-cells = <0>;
885a8cfa
HD		 445 clocks = <&tegra_car TEGRA20_CLK_DVC>,
446 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 447 clock-names = "div-clk", "fast-clk";
3393d422
SW		 448 resets = <&tegra_car 47>;
449 reset-names = "i2c";
034d023f
SW		 450 dmas = <&apbdma 24>, <&apbdma 24>;
451 dma-names = "rx", "tx";
223ef78d 452 status = "disabled";
8e267f3d
GL		 453 };
454
a86b0db3
LD		 455 spi@7000d400 {
456 compatible = "nvidia,tegra20-slink";
457 reg = <0x7000d400 0x200>;
6cecf916 458 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 459 #address-cells = <1>;
460 #size-cells = <0>;
885a8cfa 461 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
3393d422
SW		 462 resets = <&tegra_car 41>;
463 reset-names = "spi";
034d023f
SW		 464 dmas = <&apbdma 15>, <&apbdma 15>;
465 dma-names = "rx", "tx";
a86b0db3
LD		 466 status = "disabled";
467 };
468
469 spi@7000d600 {
470 compatible = "nvidia,tegra20-slink";
471 reg = <0x7000d600 0x200>;
6cecf916 472 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 473 #address-cells = <1>;
474 #size-cells = <0>;
885a8cfa 475 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
3393d422
SW		 476 resets = <&tegra_car 44>;
477 reset-names = "spi";
034d023f
SW		 478 dmas = <&apbdma 16>, <&apbdma 16>;
479 dma-names = "rx", "tx";
a86b0db3
LD		 480 status = "disabled";
481 };
482
483 spi@7000d800 {
484 compatible = "nvidia,tegra20-slink";
57471c8d 485 reg = <0x7000d800 0x200>;
6cecf916 486 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 487 #address-cells = <1>;
488 #size-cells = <0>;
885a8cfa 489 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
3393d422
SW		 490 resets = <&tegra_car 46>;
491 reset-names = "spi";
034d023f
SW		 492 dmas = <&apbdma 17>, <&apbdma 17>;
493 dma-names = "rx", "tx";
a86b0db3
LD		 494 status = "disabled";
495 };
496
497 spi@7000da00 {
498 compatible = "nvidia,tegra20-slink";
499 reg = <0x7000da00 0x200>;
6cecf916 500 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 501 #address-cells = <1>;
502 #size-cells = <0>;
885a8cfa 503 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
3393d422
SW		 504 resets = <&tegra_car 68>;
505 reset-names = "spi";
034d023f
SW		 506 dmas = <&apbdma 18>, <&apbdma 18>;
507 dma-names = "rx", "tx";
a86b0db3
LD		 508 status = "disabled";
509 };
510
58ecb23f 511 kbc@7000e200 {
699ed4b9
LD		 512 compatible = "nvidia,tegra20-kbc";
513 reg = <0x7000e200 0x100>;
6cecf916 514 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 515 clocks = <&tegra_car TEGRA20_CLK_KBC>;
3393d422
SW		 516 resets = <&tegra_car 36>;
517 reset-names = "kbc";
699ed4b9
LD		 518 status = "disabled";
519 };
520
58ecb23f 521 pmc@7000e400 {
c04abb3a
SW		 522 compatible = "nvidia,tegra20-pmc";
523 reg = <0x7000e400 0x400>;
885a8cfa 524 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
7021d122 525 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 526 };
527
bbfc33bd 528 memory-controller@7000f000 {
c04abb3a
SW		 529 compatible = "nvidia,tegra20-mc";
530 reg = <0x7000f000 0x024
531 0x7000f03c 0x3c4>;
6cecf916 532 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a
SW		 533 };
534
58ecb23f 535 iommu@7000f024 {
c04abb3a
SW		 536 compatible = "nvidia,tegra20-gart";
537 reg = <0x7000f024 0x00000018 /* controller registers */
538 0x58000000 0x02000000>; /* GART aperture */
539 };
540
bbfc33bd 541 memory-controller@7000f400 {
c04abb3a
SW		 542 compatible = "nvidia,tegra20-emc";
543 reg = <0x7000f400 0x200>;
2eaab06e
SW		 544 #address-cells = <1>;
545 #size-cells = <0>;
8e267f3d 546 };
c27317c0 547
58ecb23f 548 pcie-controller@80003000 {
1b62b611
TR		 549 compatible = "nvidia,tegra20-pcie";
550 device_type = "pci";
551 reg = <0x80003000 0x00000800 /* PADS registers */
552 0x80003800 0x00000200 /* AFI registers */
553 0x90000000 0x10000000>; /* configuration space */
554 reg-names = "pads", "afi", "cs";
555 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
556 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
557 interrupt-names = "intr", "msi";
558
97070bd4
LS		 559 #interrupt-cells = <1>;
560 interrupt-map-mask = <0 0 0 0>;
561 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
562
1b62b611
TR		 563 bus-range = <0x00 0xff>;
564 #address-cells = <3>;
565 #size-cells = <2>;
566
567 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
568 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
569 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 570 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
571 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
1b62b611
TR		 572
573 clocks = <&tegra_car TEGRA20_CLK_PEX>,
574 <&tegra_car TEGRA20_CLK_AFI>,
1b62b611 575 <&tegra_car TEGRA20_CLK_PLL_E>;
2bd541ff 576 clock-names = "pex", "afi", "pll_e";
3393d422
SW		 577 resets = <&tegra_car 70>,
578 <&tegra_car 72>,
579 <&tegra_car 74>;
580 reset-names = "pex", "afi", "pcie_x";
1b62b611
TR		 581 status = "disabled";
582
583 pci@1,0 {
584 device_type = "pci";
585 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
586 reg = <0x000800 0 0 0 0>;
587 status = "disabled";
588
589 #address-cells = <3>;
590 #size-cells = <2>;
591 ranges;
592
593 nvidia,num-lanes = <2>;
594 };
595
596 pci@2,0 {
597 device_type = "pci";
598 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
599 reg = <0x001000 0 0 0 0>;
600 status = "disabled";
601
602 #address-cells = <3>;
603 #size-cells = <2>;
604 ranges;
605
606 nvidia,num-lanes = <2>;
607 };
608 };
609
c27317c0
OJ		 610 usb@c5000000 {
611 compatible = "nvidia,tegra20-ehci", "usb-ehci";
612 reg = <0xc5000000 0x4000>;
6cecf916 613 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 614 phy_type = "utmi";
ba202f15 615 nvidia,has-legacy-mode;
885a8cfa 616 clocks = <&tegra_car TEGRA20_CLK_USBD>;
3393d422
SW		 617 resets = <&tegra_car 22>;
618 reset-names = "usb";
b4e07478 619 nvidia,needs-double-reset;
e374b65c 620 nvidia,phy = <&phy1>;
223ef78d 621 status = "disabled";
c27317c0
OJ		 622 };
623
4c94c8b5 624 phy1: usb-phy@c5000000 {
5d324410 625 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 626 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
5d324410 627 phy_type = "utmi";
885a8cfa
HD		 628 clocks = <&tegra_car TEGRA20_CLK_USBD>,
629 <&tegra_car TEGRA20_CLK_PLL_U>,
630 <&tegra_car TEGRA20_CLK_CLK_M>,
631 <&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5 632 clock-names = "reg", "pll_u", "timer", "utmi-pads";
5d324410 633 nvidia,has-legacy-mode;
c49667e5
MP		 634 nvidia,hssync-start-delay = <9>;
635 nvidia,idle-wait-delay = <17>;
636 nvidia,elastic-limit = <16>;
637 nvidia,term-range-adj = <6>;
638 nvidia,xcvr-setup = <9>;
639 nvidia,xcvr-lsfslew = <1>;
640 nvidia,xcvr-lsrslew = <1>;
4c94c8b5 641 status = "disabled";
5d324410
SW		 642 };
643
c27317c0
OJ		 644 usb@c5004000 {
645 compatible = "nvidia,tegra20-ehci", "usb-ehci";
646 reg = <0xc5004000 0x4000>;
6cecf916 647 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 648 phy_type = "ulpi";
885a8cfa 649 clocks = <&tegra_car TEGRA20_CLK_USB2>;
3393d422
SW		 650 resets = <&tegra_car 58>;
651 reset-names = "usb";
e374b65c 652 nvidia,phy = <&phy2>;
223ef78d 653 status = "disabled";
c27317c0
OJ		 654 };
655
4c94c8b5 656 phy2: usb-phy@c5004000 {
5d324410 657 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 658 reg = <0xc5004000 0x4000>;
5d324410 659 phy_type = "ulpi";
885a8cfa
HD		 660 clocks = <&tegra_car TEGRA20_CLK_USB2>,
661 <&tegra_car TEGRA20_CLK_PLL_U>,
662 <&tegra_car TEGRA20_CLK_CDEV2>;
4c94c8b5
VB		 663 clock-names = "reg", "pll_u", "ulpi-link";
664 status = "disabled";
5d324410
SW		 665 };
666
c27317c0
OJ		 667 usb@c5008000 {
668 compatible = "nvidia,tegra20-ehci", "usb-ehci";
669 reg = <0xc5008000 0x4000>;
6cecf916 670 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 671 phy_type = "utmi";
885a8cfa 672 clocks = <&tegra_car TEGRA20_CLK_USB3>;
3393d422
SW		 673 resets = <&tegra_car 59>;
674 reset-names = "usb";
e374b65c 675 nvidia,phy = <&phy3>;
223ef78d 676 status = "disabled";
c27317c0 677 };
7868a9bc 678
4c94c8b5 679 phy3: usb-phy@c5008000 {
5d324410 680 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 681 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
5d324410 682 phy_type = "utmi";
885a8cfa
HD		 683 clocks = <&tegra_car TEGRA20_CLK_USB3>,
684 <&tegra_car TEGRA20_CLK_PLL_U>,
685 <&tegra_car TEGRA20_CLK_CLK_M>,
686 <&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5 687 clock-names = "reg", "pll_u", "timer", "utmi-pads";
c49667e5
MP		 688 nvidia,hssync-start-delay = <9>;
689 nvidia,idle-wait-delay = <17>;
690 nvidia,elastic-limit = <16>;
691 nvidia,term-range-adj = <6>;
692 nvidia,xcvr-setup = <9>;
693 nvidia,xcvr-lsfslew = <2>;
694 nvidia,xcvr-lsrslew = <2>;
4c94c8b5 695 status = "disabled";
5d324410
SW		 696 };
697
c04abb3a
SW		 698 sdhci@c8000000 {
699 compatible = "nvidia,tegra20-sdhci";
700 reg = <0xc8000000 0x200>;
6cecf916 701 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 702 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
3393d422
SW		 703 resets = <&tegra_car 14>;
704 reset-names = "sdhci";
223ef78d 705 status = "disabled";
7868a9bc 706 };
4a82f2b3 707
c04abb3a
SW		 708 sdhci@c8000200 {
709 compatible = "nvidia,tegra20-sdhci";
710 reg = <0xc8000200 0x200>;
6cecf916 711 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 712 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
3393d422
SW		 713 resets = <&tegra_car 9>;
714 reset-names = "sdhci";
223ef78d 715 status = "disabled";
4a82f2b3 716 };
6a943e0e 717
c04abb3a
SW		 718 sdhci@c8000400 {
719 compatible = "nvidia,tegra20-sdhci";
720 reg = <0xc8000400 0x200>;
6cecf916 721 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 722 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
3393d422
SW		 723 resets = <&tegra_car 69>;
724 reset-names = "sdhci";
223ef78d 725 status = "disabled";
c04abb3a
SW		 726 };
727
728 sdhci@c8000600 {
729 compatible = "nvidia,tegra20-sdhci";
730 reg = <0xc8000600 0x200>;
6cecf916 731 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 732 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
3393d422
SW		 733 resets = <&tegra_car 15>;
734 reset-names = "sdhci";
223ef78d 735 status = "disabled";
c04abb3a
SW		 736 };
737
4dd2bd37
HD		 738 cpus {
739 #address-cells = <1>;
740 #size-cells = <0>;
741
742 cpu@0 {
743 device_type = "cpu";
744 compatible = "arm,cortex-a9";
745 reg = <0>;
746 };
747
748 cpu@1 {
749 device_type = "cpu";
750 compatible = "arm,cortex-a9";
751 reg = <1>;
752 };
753 };
754
c04abb3a
SW		 755 pmu {
756 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 757 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6a943e0e 759 };
8e267f3d 760};
Linux kernel - Deliverables
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