[deliverable/linux.git] / arch / arm / boot / dts / tegra20.dtsi

/include/ "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra20";
	interrupt-parent = <&intc>;

	pmc@7000f400 {
		compatible = "nvidia,tegra20-pmc";
		reg = <0x7000e400 0x400>;
	};

	intc: interrupt-controller@50041000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x50041000 0x1000>,
		      <0x50040100 0x0100>;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 56 0x04
			      0 57 0x04>;
	};

	apbdma: dma@6000a000 {
		compatible = "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1200>;
		interrupts = <0 104 0x04
			      0 105 0x04
			      0 106 0x04
			      0 107 0x04
			      0 108 0x04
			      0 109 0x04
			      0 110 0x04
			      0 111 0x04
			      0 112 0x04
			      0 113 0x04
			      0 114 0x04
			      0 115 0x04
			      0 116 0x04
			      0 117 0x04
			      0 118 0x04
			      0 119 0x04>;
	};

	i2c@7000c000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000C000 0x100>;
		interrupts = <0 38 0x04>;
	};

	i2c@7000c400 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000C400 0x100>;
		interrupts = <0 84 0x04>;
	};

	i2c@7000c500 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000C500 0x100>;
		interrupts = <0 92 0x04>;
	};

	i2c@7000d000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-i2c-dvc";
		reg = <0x7000D000 0x200>;
		interrupts = <0 53 0x04>;
	};

	tegra_i2s1: i2s@70002800 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002800 0x200>;
		interrupts = <0 13 0x04>;
		nvidia,dma-request-selector = <&apbdma 2>;
	};

	tegra_i2s2: i2s@70002a00 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002a00 0x200>;
		interrupts = <0 3 0x04>;
		nvidia,dma-request-selector = <&apbdma 1>;
	};

	das@70000c00 {
		compatible = "nvidia,tegra20-das";
		reg = <0x70000c00 0x80>;
	};

	gpio: gpio@6000d000 {
		compatible = "nvidia,tegra20-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <0 32 0x04
			      0 33 0x04
			      0 34 0x04
			      0 35 0x04
			      0 55 0x04
			      0 87 0x04
			      0 89 0x04>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux@70000000 {
		compatible = "nvidia,tegra20-pinmux";
		reg = <0x70000014 0x10   /* Tri-state registers */
		       0x70000080 0x20   /* Mux registers */
		       0x700000a0 0x14   /* Pull-up/down registers */
		       0x70000868 0xa8>; /* Pad control registers */
	};

	serial@70006000 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <0 36 0x04>;
	};

	serial@70006040 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <0 37 0x04>;
	};

	serial@70006200 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <0 46 0x04>;
	};

	serial@70006300 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <0 90 0x04>;
	};

	serial@70006400 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <0 91 0x04>;
	};

	emc@7000f400 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-emc";
		reg = <0x7000f400 0x200>;
	};

	sdhci@c8000000 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000000 0x200>;
		interrupts = <0 14 0x04>;
	};

	sdhci@c8000200 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000200 0x200>;
		interrupts = <0 15 0x04>;
	};

	sdhci@c8000400 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000400 0x200>;
		interrupts = <0 19 0x04>;
	};

	sdhci@c8000600 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000600 0x200>;
		interrupts = <0 31 0x04>;
	};

	usb@c5000000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5000000 0x4000>;
		interrupts = <0 20 0x04>;
		phy_type = "utmi";
		nvidia,has-legacy-mode;
	};

	usb@c5004000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5004000 0x4000>;
		interrupts = <0 21 0x04>;
		phy_type = "ulpi";
	};

	usb@c5008000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5008000 0x4000>;
		interrupts = <0 97 0x04>;
		phy_type = "utmi";
	};

	ahb: ahb@6000c004 {
		compatible = "nvidia,tegra20-ahb";
		reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
	};

	mc {
		compatible = "nvidia,tegra20-mc";
		reg = <0x7000f000 0x024
		       0x7000f03c 0x3c4>;
		interrupts = <0 77 0x04>;
	};

	gart {
		compatible = "nvidia,tegra20-gart";
		reg = <0x7000f024 0x00000018	/* controller registers */
		       0x58000000 0x02000000>;	/* GART aperture */
	};
};
Commit	Line	Data
8e267f3d GL	1	/include/ "skeleton.dtsi"
	2
	3	/ {
	4	compatible = "nvidia,tegra20";
	5	interrupt-parent = <&intc>;
	6
d17adfdb SW	7	pmc@7000f400 {
	8	compatible = "nvidia,tegra20-pmc";
	9	reg = <0x7000e400 0x400>;
	10	};
	11
8e267f3d	12	intc: interrupt-controller@50041000 {
0d4f7479	13	compatible = "arm,cortex-a9-gic";
8e267f3d	14	interrupt-controller;
0d4f7479	15	#interrupt-cells = <3>;
95decf84 SW	16	reg = <0x50041000 0x1000>,
95decf84 SW	17	<0x50040100 0x0100>;
8e267f3d GL	18	};
8e267f3d GL	19
583553b2 SW	20	pmu {
	21	compatible = "arm,cortex-a9-pmu";
	22	interrupts = <0 56 0x04
	23	0 57 0x04>;
	24	};
	25
8051b75a SW	26	apbdma: dma@6000a000 {
	27	compatible = "nvidia,tegra20-apbdma";
	28	reg = <0x6000a000 0x1200>;
95decf84 SW	29	interrupts = <0 104 0x04
	30	0 105 0x04
	31	0 106 0x04
	32	0 107 0x04
	33	0 108 0x04
	34	0 109 0x04
	35	0 110 0x04
	36	0 111 0x04
	37	0 112 0x04
	38	0 113 0x04
	39	0 114 0x04
	40	0 115 0x04
	41	0 116 0x04
	42	0 117 0x04
	43	0 118 0x04
	44	0 119 0x04>;
8051b75a SW	45	};
8051b75a SW	46
8e267f3d GL	47	i2c@7000c000 {
	48	#address-cells = <1>;
	49	#size-cells = <0>;
	50	compatible = "nvidia,tegra20-i2c";
	51	reg = <0x7000C000 0x100>;
95decf84	52	interrupts = <0 38 0x04>;
8e267f3d GL	53	};
	54
	55	i2c@7000c400 {
	56	#address-cells = <1>;
	57	#size-cells = <0>;
	58	compatible = "nvidia,tegra20-i2c";
	59	reg = <0x7000C400 0x100>;
95decf84	60	interrupts = <0 84 0x04>;
8e267f3d GL	61	};
	62
	63	i2c@7000c500 {
	64	#address-cells = <1>;
	65	#size-cells = <0>;
	66	compatible = "nvidia,tegra20-i2c";
	67	reg = <0x7000C500 0x100>;
95decf84	68	interrupts = <0 92 0x04>;
8e267f3d GL	69	};
	70
	71	i2c@7000d000 {
	72	#address-cells = <1>;
	73	#size-cells = <0>;
0bc2ecb6	74	compatible = "nvidia,tegra20-i2c-dvc";
8e267f3d	75	reg = <0x7000D000 0x200>;
95decf84	76	interrupts = <0 53 0x04>;
8e267f3d GL	77	};
8e267f3d GL	78
c404af0a	79	tegra_i2s1: i2s@70002800 {
8e267f3d GL	80	compatible = "nvidia,tegra20-i2s";
8e267f3d GL	81	reg = <0x70002800 0x200>;
95decf84 SW	82	interrupts = <0 13 0x04>;
95decf84 SW	83	nvidia,dma-request-selector = <&apbdma 2>;
8e267f3d GL	84	};
8e267f3d GL	85
c404af0a	86	tegra_i2s2: i2s@70002a00 {
8e267f3d GL	87	compatible = "nvidia,tegra20-i2s";
8e267f3d GL	88	reg = <0x70002a00 0x200>;
95decf84 SW	89	interrupts = <0 3 0x04>;
95decf84 SW	90	nvidia,dma-request-selector = <&apbdma 1>;
8e267f3d GL	91	};
	92
	93	das@70000c00 {
8e267f3d GL	94	compatible = "nvidia,tegra20-das";
	95	reg = <0x70000c00 0x80>;
	96	};
	97
	98	gpio: gpio@6000d000 {
	99	compatible = "nvidia,tegra20-gpio";
95decf84 SW	100	reg = <0x6000d000 0x1000>;
	101	interrupts = <0 32 0x04
	102	0 33 0x04
	103	0 34 0x04
	104	0 35 0x04
	105	0 55 0x04
	106	0 87 0x04
	107	0 89 0x04>;
8e267f3d GL	108	#gpio-cells = <2>;
8e267f3d GL	109	gpio-controller;
6f74dc9b SW	110	#interrupt-cells = <2>;
6f74dc9b SW	111	interrupt-controller;
8e267f3d GL	112	};
8e267f3d GL	113
f62f548c SW	114	pinmux: pinmux@70000000 {
f62f548c SW	115	compatible = "nvidia,tegra20-pinmux";
95decf84 SW	116	reg = <0x70000014 0x10 /* Tri-state registers */
	117	0x70000080 0x20 /* Mux registers */
	118	0x700000a0 0x14 /* Pull-up/down registers */
	119	0x70000868 0xa8>; /* Pad control registers */
f62f548c SW	120	};
f62f548c SW	121
8e267f3d GL	122	serial@70006000 {
	123	compatible = "nvidia,tegra20-uart";
	124	reg = <0x70006000 0x40>;
	125	reg-shift = <2>;
95decf84	126	interrupts = <0 36 0x04>;
8e267f3d GL	127	};
	128
	129	serial@70006040 {
	130	compatible = "nvidia,tegra20-uart";
	131	reg = <0x70006040 0x40>;
	132	reg-shift = <2>;
95decf84	133	interrupts = <0 37 0x04>;
8e267f3d GL	134	};
	135
	136	serial@70006200 {
	137	compatible = "nvidia,tegra20-uart";
	138	reg = <0x70006200 0x100>;
	139	reg-shift = <2>;
95decf84	140	interrupts = <0 46 0x04>;
8e267f3d GL	141	};
	142
	143	serial@70006300 {
	144	compatible = "nvidia,tegra20-uart";
	145	reg = <0x70006300 0x100>;
	146	reg-shift = <2>;
95decf84	147	interrupts = <0 90 0x04>;
8e267f3d GL	148	};
	149
	150	serial@70006400 {
	151	compatible = "nvidia,tegra20-uart";
	152	reg = <0x70006400 0x100>;
	153	reg-shift = <2>;
95decf84	154	interrupts = <0 91 0x04>;
8e267f3d GL	155	};
8e267f3d GL	156
0c6700ab OJ	157	emc@7000f400 {
	158	#address-cells = <1>;
	159	#size-cells = <0>;
	160	compatible = "nvidia,tegra20-emc";
	161	reg = <0x7000f400 0x200>;
	162	};
	163
8e267f3d GL	164	sdhci@c8000000 {
	165	compatible = "nvidia,tegra20-sdhci";
	166	reg = <0xc8000000 0x200>;
95decf84	167	interrupts = <0 14 0x04>;
8e267f3d GL	168	};
	169
	170	sdhci@c8000200 {
	171	compatible = "nvidia,tegra20-sdhci";
	172	reg = <0xc8000200 0x200>;
95decf84	173	interrupts = <0 15 0x04>;
8e267f3d GL	174	};
	175
	176	sdhci@c8000400 {
	177	compatible = "nvidia,tegra20-sdhci";
	178	reg = <0xc8000400 0x200>;
95decf84	179	interrupts = <0 19 0x04>;
8e267f3d GL	180	};
	181
	182	sdhci@c8000600 {
	183	compatible = "nvidia,tegra20-sdhci";
	184	reg = <0xc8000600 0x200>;
95decf84	185	interrupts = <0 31 0x04>;
8e267f3d	186	};
c27317c0 OJ	187
	188	usb@c5000000 {
	189	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	190	reg = <0xc5000000 0x4000>;
95decf84	191	interrupts = <0 20 0x04>;
c27317c0	192	phy_type = "utmi";
ba202f15	193	nvidia,has-legacy-mode;
c27317c0 OJ	194	};
	195
	196	usb@c5004000 {
	197	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	198	reg = <0xc5004000 0x4000>;
95decf84	199	interrupts = <0 21 0x04>;
c27317c0 OJ	200	phy_type = "ulpi";
	201	};
	202
	203	usb@c5008000 {
	204	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	205	reg = <0xc5008000 0x4000>;
95decf84	206	interrupts = <0 97 0x04>;
c27317c0 OJ	207	phy_type = "utmi";
c27317c0 OJ	208	};
7868a9bc HD	209
	210	ahb: ahb@6000c004 {
	211	compatible = "nvidia,tegra20-ahb";
	212	reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
	213	};
4a82f2b3	214
	215	mc {
	216	compatible = "nvidia,tegra20-mc";
	217	reg = <0x7000f000 0x024
	218	0x7000f03c 0x3c4>;
	219	interrupts = <0 77 0x04>;
	220	};
6a943e0e	221
	222	gart {
	223	compatible = "nvidia,tegra20-gart";
	224	reg = <0x7000f024 0x00000018 /* controller registers */
	225	0x58000000 0x02000000>; /* GART aperture */
	226	};
8e267f3d	227	};