Commit | Line | Data |
---|---|---|
885a8cfa | 1 | #include <dt-bindings/clock/tegra20-car.h> |
3325f1bc | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
ba4104e7 | 3 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
6cecf916 | 4 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
3325f1bc | 5 | |
1bd0bd49 | 6 | #include "skeleton.dtsi" |
8e267f3d GL |
7 | |
8 | / { | |
9 | compatible = "nvidia,tegra20"; | |
10 | interrupt-parent = <&intc>; | |
11 | ||
58ecb23f | 12 | host1x@50000000 { |
ed821f07 TR |
13 | compatible = "nvidia,tegra20-host1x", "simple-bus"; |
14 | reg = <0x50000000 0x00024000>; | |
6cecf916 SW |
15 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
16 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ | |
885a8cfa | 17 | clocks = <&tegra_car TEGRA20_CLK_HOST1X>; |
3393d422 SW |
18 | resets = <&tegra_car 28>; |
19 | reset-names = "host1x"; | |
ed821f07 TR |
20 | |
21 | #address-cells = <1>; | |
22 | #size-cells = <1>; | |
23 | ||
24 | ranges = <0x54000000 0x54000000 0x04000000>; | |
25 | ||
58ecb23f | 26 | mpe@54040000 { |
ed821f07 TR |
27 | compatible = "nvidia,tegra20-mpe"; |
28 | reg = <0x54040000 0x00040000>; | |
6cecf916 | 29 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 30 | clocks = <&tegra_car TEGRA20_CLK_MPE>; |
3393d422 SW |
31 | resets = <&tegra_car 60>; |
32 | reset-names = "mpe"; | |
ed821f07 TR |
33 | }; |
34 | ||
58ecb23f | 35 | vi@54080000 { |
ed821f07 TR |
36 | compatible = "nvidia,tegra20-vi"; |
37 | reg = <0x54080000 0x00040000>; | |
6cecf916 | 38 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 39 | clocks = <&tegra_car TEGRA20_CLK_VI>; |
3393d422 SW |
40 | resets = <&tegra_car 20>; |
41 | reset-names = "vi"; | |
ed821f07 TR |
42 | }; |
43 | ||
58ecb23f | 44 | epp@540c0000 { |
ed821f07 TR |
45 | compatible = "nvidia,tegra20-epp"; |
46 | reg = <0x540c0000 0x00040000>; | |
6cecf916 | 47 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 48 | clocks = <&tegra_car TEGRA20_CLK_EPP>; |
3393d422 SW |
49 | resets = <&tegra_car 19>; |
50 | reset-names = "epp"; | |
ed821f07 TR |
51 | }; |
52 | ||
58ecb23f | 53 | isp@54100000 { |
ed821f07 TR |
54 | compatible = "nvidia,tegra20-isp"; |
55 | reg = <0x54100000 0x00040000>; | |
6cecf916 | 56 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 57 | clocks = <&tegra_car TEGRA20_CLK_ISP>; |
3393d422 SW |
58 | resets = <&tegra_car 23>; |
59 | reset-names = "isp"; | |
ed821f07 TR |
60 | }; |
61 | ||
58ecb23f | 62 | gr2d@54140000 { |
ed821f07 TR |
63 | compatible = "nvidia,tegra20-gr2d"; |
64 | reg = <0x54140000 0x00040000>; | |
6cecf916 | 65 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 66 | clocks = <&tegra_car TEGRA20_CLK_GR2D>; |
3393d422 SW |
67 | resets = <&tegra_car 21>; |
68 | reset-names = "2d"; | |
ed821f07 TR |
69 | }; |
70 | ||
de47699d | 71 | gr3d@54180000 { |
ed821f07 | 72 | compatible = "nvidia,tegra20-gr3d"; |
de47699d | 73 | reg = <0x54180000 0x00040000>; |
885a8cfa | 74 | clocks = <&tegra_car TEGRA20_CLK_GR3D>; |
3393d422 SW |
75 | resets = <&tegra_car 24>; |
76 | reset-names = "3d"; | |
ed821f07 TR |
77 | }; |
78 | ||
79 | dc@54200000 { | |
80 | compatible = "nvidia,tegra20-dc"; | |
81 | reg = <0x54200000 0x00040000>; | |
6cecf916 | 82 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa HD |
83 | clocks = <&tegra_car TEGRA20_CLK_DISP1>, |
84 | <&tegra_car TEGRA20_CLK_PLL_P>; | |
d8f64797 | 85 | clock-names = "dc", "parent"; |
3393d422 SW |
86 | resets = <&tegra_car 27>; |
87 | reset-names = "dc"; | |
ed821f07 | 88 | |
688b56b4 TR |
89 | nvidia,head = <0>; |
90 | ||
ed821f07 TR |
91 | rgb { |
92 | status = "disabled"; | |
93 | }; | |
94 | }; | |
95 | ||
96 | dc@54240000 { | |
97 | compatible = "nvidia,tegra20-dc"; | |
98 | reg = <0x54240000 0x00040000>; | |
6cecf916 | 99 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa HD |
100 | clocks = <&tegra_car TEGRA20_CLK_DISP2>, |
101 | <&tegra_car TEGRA20_CLK_PLL_P>; | |
d8f64797 | 102 | clock-names = "dc", "parent"; |
3393d422 SW |
103 | resets = <&tegra_car 26>; |
104 | reset-names = "dc"; | |
ed821f07 | 105 | |
688b56b4 TR |
106 | nvidia,head = <1>; |
107 | ||
ed821f07 TR |
108 | rgb { |
109 | status = "disabled"; | |
110 | }; | |
111 | }; | |
112 | ||
58ecb23f | 113 | hdmi@54280000 { |
ed821f07 TR |
114 | compatible = "nvidia,tegra20-hdmi"; |
115 | reg = <0x54280000 0x00040000>; | |
6cecf916 | 116 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa HD |
117 | clocks = <&tegra_car TEGRA20_CLK_HDMI>, |
118 | <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; | |
8d8b43da | 119 | clock-names = "hdmi", "parent"; |
3393d422 SW |
120 | resets = <&tegra_car 51>; |
121 | reset-names = "hdmi"; | |
ed821f07 TR |
122 | status = "disabled"; |
123 | }; | |
124 | ||
58ecb23f | 125 | tvo@542c0000 { |
ed821f07 TR |
126 | compatible = "nvidia,tegra20-tvo"; |
127 | reg = <0x542c0000 0x00040000>; | |
6cecf916 | 128 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 129 | clocks = <&tegra_car TEGRA20_CLK_TVO>; |
ed821f07 TR |
130 | status = "disabled"; |
131 | }; | |
132 | ||
de47699d | 133 | dsi@54300000 { |
ed821f07 | 134 | compatible = "nvidia,tegra20-dsi"; |
de47699d | 135 | reg = <0x54300000 0x00040000>; |
885a8cfa | 136 | clocks = <&tegra_car TEGRA20_CLK_DSI>; |
3393d422 SW |
137 | resets = <&tegra_car 48>; |
138 | reset-names = "dsi"; | |
ed821f07 TR |
139 | status = "disabled"; |
140 | }; | |
141 | }; | |
142 | ||
2cda1880 | 143 | timer@50040600 { |
73368ba0 SW |
144 | compatible = "arm,cortex-a9-twd-timer"; |
145 | reg = <0x50040600 0x20>; | |
6cecf916 SW |
146 | interrupts = <GIC_PPI 13 |
147 | (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
885a8cfa | 148 | clocks = <&tegra_car TEGRA20_CLK_TWD>; |
73368ba0 SW |
149 | }; |
150 | ||
58ecb23f | 151 | intc: interrupt-controller@50041000 { |
0d4f7479 | 152 | compatible = "arm,cortex-a9-gic"; |
5ff48887 SW |
153 | reg = <0x50041000 0x1000 |
154 | 0x50040100 0x0100>; | |
2eaab06e SW |
155 | interrupt-controller; |
156 | #interrupt-cells = <3>; | |
8e267f3d GL |
157 | }; |
158 | ||
58ecb23f | 159 | cache-controller@50043000 { |
bb2c1de9 SW |
160 | compatible = "arm,pl310-cache"; |
161 | reg = <0x50043000 0x1000>; | |
162 | arm,data-latency = <5 5 2>; | |
163 | arm,tag-latency = <4 4 2>; | |
164 | cache-unified; | |
165 | cache-level = <2>; | |
166 | }; | |
167 | ||
2f2b7fb2 SW |
168 | timer@60005000 { |
169 | compatible = "nvidia,tegra20-timer"; | |
170 | reg = <0x60005000 0x60>; | |
6cecf916 SW |
171 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
172 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
173 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
174 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
885a8cfa | 175 | clocks = <&tegra_car TEGRA20_CLK_TIMER>; |
2f2b7fb2 SW |
176 | }; |
177 | ||
58ecb23f | 178 | tegra_car: clock@60006000 { |
270f8ce3 SW |
179 | compatible = "nvidia,tegra20-car"; |
180 | reg = <0x60006000 0x1000>; | |
181 | #clock-cells = <1>; | |
3393d422 | 182 | #reset-cells = <1>; |
270f8ce3 SW |
183 | }; |
184 | ||
b1023134 TR |
185 | flow-controller@60007000 { |
186 | compatible = "nvidia,tegra20-flowctrl"; | |
187 | reg = <0x60007000 0x1000>; | |
188 | }; | |
189 | ||
58ecb23f | 190 | apbdma: dma@6000a000 { |
8051b75a SW |
191 | compatible = "nvidia,tegra20-apbdma"; |
192 | reg = <0x6000a000 0x1200>; | |
6cecf916 SW |
193 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
194 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
195 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
196 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
197 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
198 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
199 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
200 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
201 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
202 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
203 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
204 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
205 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
206 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
207 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
208 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; | |
885a8cfa | 209 | clocks = <&tegra_car TEGRA20_CLK_APBDMA>; |
3393d422 SW |
210 | resets = <&tegra_car 34>; |
211 | reset-names = "dma"; | |
034d023f | 212 | #dma-cells = <1>; |
8051b75a SW |
213 | }; |
214 | ||
58ecb23f | 215 | ahb@6000c004 { |
c04abb3a SW |
216 | compatible = "nvidia,tegra20-ahb"; |
217 | reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ | |
8e267f3d GL |
218 | }; |
219 | ||
58ecb23f | 220 | gpio: gpio@6000d000 { |
8e267f3d | 221 | compatible = "nvidia,tegra20-gpio"; |
95decf84 | 222 | reg = <0x6000d000 0x1000>; |
6cecf916 SW |
223 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
224 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
225 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
226 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
227 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
228 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
229 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
8e267f3d GL |
230 | #gpio-cells = <2>; |
231 | gpio-controller; | |
6f74dc9b SW |
232 | #interrupt-cells = <2>; |
233 | interrupt-controller; | |
8e267f3d GL |
234 | }; |
235 | ||
155dfc7b PDS |
236 | apbmisc@70000800 { |
237 | compatible = "nvidia,tegra20-apbmisc"; | |
238 | reg = <0x70000800 0x64 /* Chip revision */ | |
239 | 0x70000008 0x04>; /* Strapping options */ | |
240 | }; | |
241 | ||
58ecb23f | 242 | pinmux: pinmux@70000014 { |
f62f548c | 243 | compatible = "nvidia,tegra20-pinmux"; |
95decf84 SW |
244 | reg = <0x70000014 0x10 /* Tri-state registers */ |
245 | 0x70000080 0x20 /* Mux registers */ | |
246 | 0x700000a0 0x14 /* Pull-up/down registers */ | |
247 | 0x70000868 0xa8>; /* Pad control registers */ | |
f62f548c SW |
248 | }; |
249 | ||
58ecb23f | 250 | das@70000c00 { |
c04abb3a SW |
251 | compatible = "nvidia,tegra20-das"; |
252 | reg = <0x70000c00 0x80>; | |
253 | }; | |
fc5c306b | 254 | |
58ecb23f | 255 | tegra_ac97: ac97@70002000 { |
0698ed19 LS |
256 | compatible = "nvidia,tegra20-ac97"; |
257 | reg = <0x70002000 0x200>; | |
6cecf916 | 258 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 259 | clocks = <&tegra_car TEGRA20_CLK_AC97>; |
3393d422 SW |
260 | resets = <&tegra_car 3>; |
261 | reset-names = "ac97"; | |
034d023f SW |
262 | dmas = <&apbdma 12>, <&apbdma 12>; |
263 | dma-names = "rx", "tx"; | |
0698ed19 LS |
264 | status = "disabled"; |
265 | }; | |
c04abb3a SW |
266 | |
267 | tegra_i2s1: i2s@70002800 { | |
268 | compatible = "nvidia,tegra20-i2s"; | |
269 | reg = <0x70002800 0x200>; | |
6cecf916 | 270 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 271 | clocks = <&tegra_car TEGRA20_CLK_I2S1>; |
3393d422 SW |
272 | resets = <&tegra_car 11>; |
273 | reset-names = "i2s"; | |
034d023f SW |
274 | dmas = <&apbdma 2>, <&apbdma 2>; |
275 | dma-names = "rx", "tx"; | |
223ef78d | 276 | status = "disabled"; |
c04abb3a SW |
277 | }; |
278 | ||
279 | tegra_i2s2: i2s@70002a00 { | |
280 | compatible = "nvidia,tegra20-i2s"; | |
281 | reg = <0x70002a00 0x200>; | |
6cecf916 | 282 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 283 | clocks = <&tegra_car TEGRA20_CLK_I2S2>; |
3393d422 SW |
284 | resets = <&tegra_car 18>; |
285 | reset-names = "i2s"; | |
034d023f SW |
286 | dmas = <&apbdma 1>, <&apbdma 1>; |
287 | dma-names = "rx", "tx"; | |
223ef78d | 288 | status = "disabled"; |
c04abb3a SW |
289 | }; |
290 | ||
b6551bb9 LD |
291 | /* |
292 | * There are two serial driver i.e. 8250 based simple serial | |
293 | * driver and APB DMA based serial driver for higher baudrate | |
294 | * and performace. To enable the 8250 based driver, the compatible | |
295 | * is "nvidia,tegra20-uart" and to enable the APB DMA based serial | |
296 | * driver, the comptible is "nvidia,tegra20-hsuart". | |
297 | */ | |
298 | uarta: serial@70006000 { | |
8e267f3d GL |
299 | compatible = "nvidia,tegra20-uart"; |
300 | reg = <0x70006000 0x40>; | |
301 | reg-shift = <2>; | |
6cecf916 | 302 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 303 | clocks = <&tegra_car TEGRA20_CLK_UARTA>; |
3393d422 SW |
304 | resets = <&tegra_car 6>; |
305 | reset-names = "serial"; | |
034d023f SW |
306 | dmas = <&apbdma 8>, <&apbdma 8>; |
307 | dma-names = "rx", "tx"; | |
223ef78d | 308 | status = "disabled"; |
8e267f3d GL |
309 | }; |
310 | ||
b6551bb9 | 311 | uartb: serial@70006040 { |
8e267f3d GL |
312 | compatible = "nvidia,tegra20-uart"; |
313 | reg = <0x70006040 0x40>; | |
314 | reg-shift = <2>; | |
6cecf916 | 315 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 316 | clocks = <&tegra_car TEGRA20_CLK_UARTB>; |
3393d422 SW |
317 | resets = <&tegra_car 7>; |
318 | reset-names = "serial"; | |
034d023f SW |
319 | dmas = <&apbdma 9>, <&apbdma 9>; |
320 | dma-names = "rx", "tx"; | |
223ef78d | 321 | status = "disabled"; |
8e267f3d GL |
322 | }; |
323 | ||
b6551bb9 | 324 | uartc: serial@70006200 { |
8e267f3d GL |
325 | compatible = "nvidia,tegra20-uart"; |
326 | reg = <0x70006200 0x100>; | |
327 | reg-shift = <2>; | |
6cecf916 | 328 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 329 | clocks = <&tegra_car TEGRA20_CLK_UARTC>; |
3393d422 SW |
330 | resets = <&tegra_car 55>; |
331 | reset-names = "serial"; | |
034d023f SW |
332 | dmas = <&apbdma 10>, <&apbdma 10>; |
333 | dma-names = "rx", "tx"; | |
223ef78d | 334 | status = "disabled"; |
8e267f3d GL |
335 | }; |
336 | ||
b6551bb9 | 337 | uartd: serial@70006300 { |
8e267f3d GL |
338 | compatible = "nvidia,tegra20-uart"; |
339 | reg = <0x70006300 0x100>; | |
340 | reg-shift = <2>; | |
6cecf916 | 341 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 342 | clocks = <&tegra_car TEGRA20_CLK_UARTD>; |
3393d422 SW |
343 | resets = <&tegra_car 65>; |
344 | reset-names = "serial"; | |
034d023f SW |
345 | dmas = <&apbdma 19>, <&apbdma 19>; |
346 | dma-names = "rx", "tx"; | |
223ef78d | 347 | status = "disabled"; |
8e267f3d GL |
348 | }; |
349 | ||
b6551bb9 | 350 | uarte: serial@70006400 { |
8e267f3d GL |
351 | compatible = "nvidia,tegra20-uart"; |
352 | reg = <0x70006400 0x100>; | |
353 | reg-shift = <2>; | |
6cecf916 | 354 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 355 | clocks = <&tegra_car TEGRA20_CLK_UARTE>; |
3393d422 SW |
356 | resets = <&tegra_car 66>; |
357 | reset-names = "serial"; | |
034d023f SW |
358 | dmas = <&apbdma 20>, <&apbdma 20>; |
359 | dma-names = "rx", "tx"; | |
223ef78d | 360 | status = "disabled"; |
8e267f3d GL |
361 | }; |
362 | ||
58ecb23f | 363 | pwm: pwm@7000a000 { |
140fd977 TR |
364 | compatible = "nvidia,tegra20-pwm"; |
365 | reg = <0x7000a000 0x100>; | |
366 | #pwm-cells = <2>; | |
885a8cfa | 367 | clocks = <&tegra_car TEGRA20_CLK_PWM>; |
3393d422 SW |
368 | resets = <&tegra_car 17>; |
369 | reset-names = "pwm"; | |
b69cd984 | 370 | status = "disabled"; |
140fd977 TR |
371 | }; |
372 | ||
58ecb23f | 373 | rtc@7000e000 { |
380e04ac SW |
374 | compatible = "nvidia,tegra20-rtc"; |
375 | reg = <0x7000e000 0x100>; | |
6cecf916 | 376 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 377 | clocks = <&tegra_car TEGRA20_CLK_RTC>; |
380e04ac SW |
378 | }; |
379 | ||
c04abb3a | 380 | i2c@7000c000 { |
c04abb3a SW |
381 | compatible = "nvidia,tegra20-i2c"; |
382 | reg = <0x7000c000 0x100>; | |
6cecf916 | 383 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
384 | #address-cells = <1>; |
385 | #size-cells = <0>; | |
885a8cfa HD |
386 | clocks = <&tegra_car TEGRA20_CLK_I2C1>, |
387 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 388 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
389 | resets = <&tegra_car 12>; |
390 | reset-names = "i2c"; | |
034d023f SW |
391 | dmas = <&apbdma 21>, <&apbdma 21>; |
392 | dma-names = "rx", "tx"; | |
223ef78d | 393 | status = "disabled"; |
0c6700ab OJ |
394 | }; |
395 | ||
fa98a114 LD |
396 | spi@7000c380 { |
397 | compatible = "nvidia,tegra20-sflash"; | |
398 | reg = <0x7000c380 0x80>; | |
6cecf916 | 399 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
fa98a114 LD |
400 | #address-cells = <1>; |
401 | #size-cells = <0>; | |
885a8cfa | 402 | clocks = <&tegra_car TEGRA20_CLK_SPI>; |
3393d422 SW |
403 | resets = <&tegra_car 43>; |
404 | reset-names = "spi"; | |
034d023f SW |
405 | dmas = <&apbdma 11>, <&apbdma 11>; |
406 | dma-names = "rx", "tx"; | |
fa98a114 LD |
407 | status = "disabled"; |
408 | }; | |
409 | ||
c04abb3a | 410 | i2c@7000c400 { |
c04abb3a SW |
411 | compatible = "nvidia,tegra20-i2c"; |
412 | reg = <0x7000c400 0x100>; | |
6cecf916 | 413 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
414 | #address-cells = <1>; |
415 | #size-cells = <0>; | |
885a8cfa HD |
416 | clocks = <&tegra_car TEGRA20_CLK_I2C2>, |
417 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 418 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
419 | resets = <&tegra_car 54>; |
420 | reset-names = "i2c"; | |
034d023f SW |
421 | dmas = <&apbdma 22>, <&apbdma 22>; |
422 | dma-names = "rx", "tx"; | |
223ef78d | 423 | status = "disabled"; |
8e267f3d GL |
424 | }; |
425 | ||
c04abb3a | 426 | i2c@7000c500 { |
c04abb3a SW |
427 | compatible = "nvidia,tegra20-i2c"; |
428 | reg = <0x7000c500 0x100>; | |
6cecf916 | 429 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
430 | #address-cells = <1>; |
431 | #size-cells = <0>; | |
885a8cfa HD |
432 | clocks = <&tegra_car TEGRA20_CLK_I2C3>, |
433 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 434 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
435 | resets = <&tegra_car 67>; |
436 | reset-names = "i2c"; | |
034d023f SW |
437 | dmas = <&apbdma 23>, <&apbdma 23>; |
438 | dma-names = "rx", "tx"; | |
223ef78d | 439 | status = "disabled"; |
8e267f3d GL |
440 | }; |
441 | ||
c04abb3a | 442 | i2c@7000d000 { |
c04abb3a SW |
443 | compatible = "nvidia,tegra20-i2c-dvc"; |
444 | reg = <0x7000d000 0x200>; | |
6cecf916 | 445 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
446 | #address-cells = <1>; |
447 | #size-cells = <0>; | |
885a8cfa HD |
448 | clocks = <&tegra_car TEGRA20_CLK_DVC>, |
449 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | |
8d8b43da | 450 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
451 | resets = <&tegra_car 47>; |
452 | reset-names = "i2c"; | |
034d023f SW |
453 | dmas = <&apbdma 24>, <&apbdma 24>; |
454 | dma-names = "rx", "tx"; | |
223ef78d | 455 | status = "disabled"; |
8e267f3d GL |
456 | }; |
457 | ||
a86b0db3 LD |
458 | spi@7000d400 { |
459 | compatible = "nvidia,tegra20-slink"; | |
460 | reg = <0x7000d400 0x200>; | |
6cecf916 | 461 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
462 | #address-cells = <1>; |
463 | #size-cells = <0>; | |
885a8cfa | 464 | clocks = <&tegra_car TEGRA20_CLK_SBC1>; |
3393d422 SW |
465 | resets = <&tegra_car 41>; |
466 | reset-names = "spi"; | |
034d023f SW |
467 | dmas = <&apbdma 15>, <&apbdma 15>; |
468 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
469 | status = "disabled"; |
470 | }; | |
471 | ||
472 | spi@7000d600 { | |
473 | compatible = "nvidia,tegra20-slink"; | |
474 | reg = <0x7000d600 0x200>; | |
6cecf916 | 475 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
476 | #address-cells = <1>; |
477 | #size-cells = <0>; | |
885a8cfa | 478 | clocks = <&tegra_car TEGRA20_CLK_SBC2>; |
3393d422 SW |
479 | resets = <&tegra_car 44>; |
480 | reset-names = "spi"; | |
034d023f SW |
481 | dmas = <&apbdma 16>, <&apbdma 16>; |
482 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
483 | status = "disabled"; |
484 | }; | |
485 | ||
486 | spi@7000d800 { | |
487 | compatible = "nvidia,tegra20-slink"; | |
57471c8d | 488 | reg = <0x7000d800 0x200>; |
6cecf916 | 489 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
490 | #address-cells = <1>; |
491 | #size-cells = <0>; | |
885a8cfa | 492 | clocks = <&tegra_car TEGRA20_CLK_SBC3>; |
3393d422 SW |
493 | resets = <&tegra_car 46>; |
494 | reset-names = "spi"; | |
034d023f SW |
495 | dmas = <&apbdma 17>, <&apbdma 17>; |
496 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
497 | status = "disabled"; |
498 | }; | |
499 | ||
500 | spi@7000da00 { | |
501 | compatible = "nvidia,tegra20-slink"; | |
502 | reg = <0x7000da00 0x200>; | |
6cecf916 | 503 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
504 | #address-cells = <1>; |
505 | #size-cells = <0>; | |
885a8cfa | 506 | clocks = <&tegra_car TEGRA20_CLK_SBC4>; |
3393d422 SW |
507 | resets = <&tegra_car 68>; |
508 | reset-names = "spi"; | |
034d023f SW |
509 | dmas = <&apbdma 18>, <&apbdma 18>; |
510 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
511 | status = "disabled"; |
512 | }; | |
513 | ||
58ecb23f | 514 | kbc@7000e200 { |
699ed4b9 LD |
515 | compatible = "nvidia,tegra20-kbc"; |
516 | reg = <0x7000e200 0x100>; | |
6cecf916 | 517 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 518 | clocks = <&tegra_car TEGRA20_CLK_KBC>; |
3393d422 SW |
519 | resets = <&tegra_car 36>; |
520 | reset-names = "kbc"; | |
699ed4b9 LD |
521 | status = "disabled"; |
522 | }; | |
523 | ||
58ecb23f | 524 | pmc@7000e400 { |
c04abb3a SW |
525 | compatible = "nvidia,tegra20-pmc"; |
526 | reg = <0x7000e400 0x400>; | |
885a8cfa | 527 | clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; |
7021d122 | 528 | clock-names = "pclk", "clk32k_in"; |
c04abb3a SW |
529 | }; |
530 | ||
bbfc33bd | 531 | memory-controller@7000f000 { |
c04abb3a SW |
532 | compatible = "nvidia,tegra20-mc"; |
533 | reg = <0x7000f000 0x024 | |
534 | 0x7000f03c 0x3c4>; | |
6cecf916 | 535 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
c04abb3a SW |
536 | }; |
537 | ||
58ecb23f | 538 | iommu@7000f024 { |
c04abb3a SW |
539 | compatible = "nvidia,tegra20-gart"; |
540 | reg = <0x7000f024 0x00000018 /* controller registers */ | |
541 | 0x58000000 0x02000000>; /* GART aperture */ | |
542 | }; | |
543 | ||
bbfc33bd | 544 | memory-controller@7000f400 { |
c04abb3a SW |
545 | compatible = "nvidia,tegra20-emc"; |
546 | reg = <0x7000f400 0x200>; | |
2eaab06e SW |
547 | #address-cells = <1>; |
548 | #size-cells = <0>; | |
8e267f3d | 549 | }; |
c27317c0 | 550 | |
155dfc7b PDS |
551 | fuse@7000f800 { |
552 | compatible = "nvidia,tegra20-efuse"; | |
553 | reg = <0x7000F800 0x400>; | |
554 | clocks = <&tegra_car TEGRA20_CLK_FUSE>; | |
555 | clock-names = "fuse"; | |
556 | resets = <&tegra_car 39>; | |
557 | reset-names = "fuse"; | |
558 | }; | |
559 | ||
58ecb23f | 560 | pcie-controller@80003000 { |
1b62b611 TR |
561 | compatible = "nvidia,tegra20-pcie"; |
562 | device_type = "pci"; | |
563 | reg = <0x80003000 0x00000800 /* PADS registers */ | |
564 | 0x80003800 0x00000200 /* AFI registers */ | |
565 | 0x90000000 0x10000000>; /* configuration space */ | |
566 | reg-names = "pads", "afi", "cs"; | |
567 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ | |
568 | GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ | |
569 | interrupt-names = "intr", "msi"; | |
570 | ||
97070bd4 LS |
571 | #interrupt-cells = <1>; |
572 | interrupt-map-mask = <0 0 0 0>; | |
573 | interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
574 | ||
1b62b611 TR |
575 | bus-range = <0x00 0xff>; |
576 | #address-cells = <3>; | |
577 | #size-cells = <2>; | |
578 | ||
579 | ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ | |
580 | 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ | |
581 | 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ | |
d7283c11 JA |
582 | 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ |
583 | 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ | |
1b62b611 TR |
584 | |
585 | clocks = <&tegra_car TEGRA20_CLK_PEX>, | |
586 | <&tegra_car TEGRA20_CLK_AFI>, | |
1b62b611 | 587 | <&tegra_car TEGRA20_CLK_PLL_E>; |
2bd541ff | 588 | clock-names = "pex", "afi", "pll_e"; |
3393d422 SW |
589 | resets = <&tegra_car 70>, |
590 | <&tegra_car 72>, | |
591 | <&tegra_car 74>; | |
592 | reset-names = "pex", "afi", "pcie_x"; | |
1b62b611 TR |
593 | status = "disabled"; |
594 | ||
595 | pci@1,0 { | |
596 | device_type = "pci"; | |
597 | assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; | |
598 | reg = <0x000800 0 0 0 0>; | |
599 | status = "disabled"; | |
600 | ||
601 | #address-cells = <3>; | |
602 | #size-cells = <2>; | |
603 | ranges; | |
604 | ||
605 | nvidia,num-lanes = <2>; | |
606 | }; | |
607 | ||
608 | pci@2,0 { | |
609 | device_type = "pci"; | |
610 | assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; | |
611 | reg = <0x001000 0 0 0 0>; | |
612 | status = "disabled"; | |
613 | ||
614 | #address-cells = <3>; | |
615 | #size-cells = <2>; | |
616 | ranges; | |
617 | ||
618 | nvidia,num-lanes = <2>; | |
619 | }; | |
620 | }; | |
621 | ||
c27317c0 OJ |
622 | usb@c5000000 { |
623 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
624 | reg = <0xc5000000 0x4000>; | |
6cecf916 | 625 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
c27317c0 | 626 | phy_type = "utmi"; |
ba202f15 | 627 | nvidia,has-legacy-mode; |
885a8cfa | 628 | clocks = <&tegra_car TEGRA20_CLK_USBD>; |
3393d422 SW |
629 | resets = <&tegra_car 22>; |
630 | reset-names = "usb"; | |
b4e07478 | 631 | nvidia,needs-double-reset; |
e374b65c | 632 | nvidia,phy = <&phy1>; |
223ef78d | 633 | status = "disabled"; |
c27317c0 OJ |
634 | }; |
635 | ||
4c94c8b5 | 636 | phy1: usb-phy@c5000000 { |
5d324410 | 637 | compatible = "nvidia,tegra20-usb-phy"; |
4c94c8b5 | 638 | reg = <0xc5000000 0x4000 0xc5000000 0x4000>; |
5d324410 | 639 | phy_type = "utmi"; |
885a8cfa HD |
640 | clocks = <&tegra_car TEGRA20_CLK_USBD>, |
641 | <&tegra_car TEGRA20_CLK_PLL_U>, | |
642 | <&tegra_car TEGRA20_CLK_CLK_M>, | |
643 | <&tegra_car TEGRA20_CLK_USBD>; | |
4c94c8b5 | 644 | clock-names = "reg", "pll_u", "timer", "utmi-pads"; |
308efde2 TT |
645 | resets = <&tegra_car 22>, <&tegra_car 22>; |
646 | reset-names = "usb", "utmi-pads"; | |
5d324410 | 647 | nvidia,has-legacy-mode; |
c49667e5 MP |
648 | nvidia,hssync-start-delay = <9>; |
649 | nvidia,idle-wait-delay = <17>; | |
650 | nvidia,elastic-limit = <16>; | |
651 | nvidia,term-range-adj = <6>; | |
652 | nvidia,xcvr-setup = <9>; | |
653 | nvidia,xcvr-lsfslew = <1>; | |
654 | nvidia,xcvr-lsrslew = <1>; | |
308efde2 | 655 | nvidia,has-utmi-pad-registers; |
4c94c8b5 | 656 | status = "disabled"; |
5d324410 SW |
657 | }; |
658 | ||
c27317c0 OJ |
659 | usb@c5004000 { |
660 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
661 | reg = <0xc5004000 0x4000>; | |
6cecf916 | 662 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
c27317c0 | 663 | phy_type = "ulpi"; |
885a8cfa | 664 | clocks = <&tegra_car TEGRA20_CLK_USB2>; |
3393d422 SW |
665 | resets = <&tegra_car 58>; |
666 | reset-names = "usb"; | |
e374b65c | 667 | nvidia,phy = <&phy2>; |
223ef78d | 668 | status = "disabled"; |
c27317c0 OJ |
669 | }; |
670 | ||
4c94c8b5 | 671 | phy2: usb-phy@c5004000 { |
5d324410 | 672 | compatible = "nvidia,tegra20-usb-phy"; |
4c94c8b5 | 673 | reg = <0xc5004000 0x4000>; |
5d324410 | 674 | phy_type = "ulpi"; |
885a8cfa HD |
675 | clocks = <&tegra_car TEGRA20_CLK_USB2>, |
676 | <&tegra_car TEGRA20_CLK_PLL_U>, | |
677 | <&tegra_car TEGRA20_CLK_CDEV2>; | |
4c94c8b5 | 678 | clock-names = "reg", "pll_u", "ulpi-link"; |
308efde2 TT |
679 | resets = <&tegra_car 58>, <&tegra_car 22>; |
680 | reset-names = "usb", "utmi-pads"; | |
4c94c8b5 | 681 | status = "disabled"; |
5d324410 SW |
682 | }; |
683 | ||
c27317c0 OJ |
684 | usb@c5008000 { |
685 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
686 | reg = <0xc5008000 0x4000>; | |
6cecf916 | 687 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
c27317c0 | 688 | phy_type = "utmi"; |
885a8cfa | 689 | clocks = <&tegra_car TEGRA20_CLK_USB3>; |
3393d422 SW |
690 | resets = <&tegra_car 59>; |
691 | reset-names = "usb"; | |
e374b65c | 692 | nvidia,phy = <&phy3>; |
223ef78d | 693 | status = "disabled"; |
c27317c0 | 694 | }; |
7868a9bc | 695 | |
4c94c8b5 | 696 | phy3: usb-phy@c5008000 { |
5d324410 | 697 | compatible = "nvidia,tegra20-usb-phy"; |
4c94c8b5 | 698 | reg = <0xc5008000 0x4000 0xc5000000 0x4000>; |
5d324410 | 699 | phy_type = "utmi"; |
885a8cfa HD |
700 | clocks = <&tegra_car TEGRA20_CLK_USB3>, |
701 | <&tegra_car TEGRA20_CLK_PLL_U>, | |
702 | <&tegra_car TEGRA20_CLK_CLK_M>, | |
703 | <&tegra_car TEGRA20_CLK_USBD>; | |
4c94c8b5 | 704 | clock-names = "reg", "pll_u", "timer", "utmi-pads"; |
308efde2 TT |
705 | resets = <&tegra_car 59>, <&tegra_car 22>; |
706 | reset-names = "usb", "utmi-pads"; | |
c49667e5 MP |
707 | nvidia,hssync-start-delay = <9>; |
708 | nvidia,idle-wait-delay = <17>; | |
709 | nvidia,elastic-limit = <16>; | |
710 | nvidia,term-range-adj = <6>; | |
711 | nvidia,xcvr-setup = <9>; | |
712 | nvidia,xcvr-lsfslew = <2>; | |
713 | nvidia,xcvr-lsrslew = <2>; | |
4c94c8b5 | 714 | status = "disabled"; |
5d324410 SW |
715 | }; |
716 | ||
c04abb3a SW |
717 | sdhci@c8000000 { |
718 | compatible = "nvidia,tegra20-sdhci"; | |
719 | reg = <0xc8000000 0x200>; | |
6cecf916 | 720 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 721 | clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; |
3393d422 SW |
722 | resets = <&tegra_car 14>; |
723 | reset-names = "sdhci"; | |
223ef78d | 724 | status = "disabled"; |
7868a9bc | 725 | }; |
4a82f2b3 | 726 | |
c04abb3a SW |
727 | sdhci@c8000200 { |
728 | compatible = "nvidia,tegra20-sdhci"; | |
729 | reg = <0xc8000200 0x200>; | |
6cecf916 | 730 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 731 | clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; |
3393d422 SW |
732 | resets = <&tegra_car 9>; |
733 | reset-names = "sdhci"; | |
223ef78d | 734 | status = "disabled"; |
4a82f2b3 | 735 | }; |
6a943e0e | 736 | |
c04abb3a SW |
737 | sdhci@c8000400 { |
738 | compatible = "nvidia,tegra20-sdhci"; | |
739 | reg = <0xc8000400 0x200>; | |
6cecf916 | 740 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 741 | clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; |
3393d422 SW |
742 | resets = <&tegra_car 69>; |
743 | reset-names = "sdhci"; | |
223ef78d | 744 | status = "disabled"; |
c04abb3a SW |
745 | }; |
746 | ||
747 | sdhci@c8000600 { | |
748 | compatible = "nvidia,tegra20-sdhci"; | |
749 | reg = <0xc8000600 0x200>; | |
6cecf916 | 750 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
885a8cfa | 751 | clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; |
3393d422 SW |
752 | resets = <&tegra_car 15>; |
753 | reset-names = "sdhci"; | |
223ef78d | 754 | status = "disabled"; |
c04abb3a SW |
755 | }; |
756 | ||
4dd2bd37 HD |
757 | cpus { |
758 | #address-cells = <1>; | |
759 | #size-cells = <0>; | |
760 | ||
761 | cpu@0 { | |
762 | device_type = "cpu"; | |
763 | compatible = "arm,cortex-a9"; | |
764 | reg = <0>; | |
765 | }; | |
766 | ||
767 | cpu@1 { | |
768 | device_type = "cpu"; | |
769 | compatible = "arm,cortex-a9"; | |
770 | reg = <1>; | |
771 | }; | |
772 | }; | |
773 | ||
c04abb3a SW |
774 | pmu { |
775 | compatible = "arm,cortex-a9-pmu"; | |
6cecf916 SW |
776 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
777 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
6a943e0e | 778 | }; |
8e267f3d | 779 | }; |