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6d0a067f MZ |
1 | #include "tegra30.dtsi" |
2 | ||
3 | /* | |
a5e27206 MZ |
4 | * Toradex Apalis T30 Module Device Tree |
5 | * Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A; | |
6 | * 2GB: V1.0B, V1.0C, V1.0E, V1.1A | |
6d0a067f MZ |
7 | */ |
8 | / { | |
9 | model = "Toradex Apalis T30"; | |
10 | compatible = "toradex,apalis_t30", "nvidia,tegra30"; | |
11 | ||
12 | pcie-controller@00003000 { | |
b607b19a MZ |
13 | avdd-pexa-supply = <&vdd2_reg>; |
14 | vdd-pexa-supply = <&vdd2_reg>; | |
15 | avdd-pexb-supply = <&vdd2_reg>; | |
16 | vdd-pexb-supply = <&vdd2_reg>; | |
17 | avdd-pex-pll-supply = <&vdd2_reg>; | |
18 | avdd-plle-supply = <&ldo6_reg>; | |
19 | vddio-pex-ctl-supply = <&sys_3v3_reg>; | |
20 | hvdd-pex-supply = <&sys_3v3_reg>; | |
6d0a067f MZ |
21 | |
22 | pci@1,0 { | |
23 | nvidia,num-lanes = <4>; | |
24 | }; | |
25 | ||
26 | pci@2,0 { | |
27 | nvidia,num-lanes = <1>; | |
28 | }; | |
29 | ||
30 | pci@3,0 { | |
31 | nvidia,num-lanes = <1>; | |
32 | }; | |
33 | }; | |
34 | ||
35 | host1x@50000000 { | |
36 | hdmi@54280000 { | |
654b7d6a MZ |
37 | vdd-supply = <&avdd_hdmi_3v3_reg>; |
38 | pll-supply = <&avdd_hdmi_pll_1v8_reg>; | |
6d0a067f MZ |
39 | |
40 | nvidia,hpd-gpio = | |
41 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | |
42 | nvidia,ddc-i2c-bus = <&hdmiddc>; | |
43 | }; | |
44 | }; | |
45 | ||
46 | pinmux@70000868 { | |
47 | pinctrl-names = "default"; | |
48 | pinctrl-0 = <&state_default>; | |
49 | ||
50 | state_default: pinmux { | |
51 | /* Apalis BKL1_ON */ | |
52 | pv2 { | |
53 | nvidia,pins = "pv2"; | |
54 | nvidia,function = "rsvd4"; | |
55 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
56 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
57 | }; | |
58 | ||
59 | /* Apalis BKL1_PWM */ | |
60 | uart3_rts_n_pc0 { | |
61 | nvidia,pins = "uart3_rts_n_pc0"; | |
62 | nvidia,function = "pwm0"; | |
63 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
64 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
65 | }; | |
66 | /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ | |
67 | uart3_cts_n_pa1 { | |
68 | nvidia,pins = "uart3_cts_n_pa1"; | |
0f44de6c | 69 | nvidia,function = "rsvd2"; |
6d0a067f MZ |
70 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
71 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
72 | }; | |
73 | ||
74 | /* Apalis CAN1 on SPI6 */ | |
75 | spi2_cs0_n_px3 { | |
76 | nvidia,pins = "spi2_cs0_n_px3", | |
77 | "spi2_miso_px1", | |
78 | "spi2_mosi_px0", | |
79 | "spi2_sck_px2"; | |
80 | nvidia,function = "spi6"; | |
81 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
82 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
83 | }; | |
84 | /* CAN_INT1 */ | |
85 | spi2_cs1_n_pw2 { | |
86 | nvidia,pins = "spi2_cs1_n_pw2"; | |
87 | nvidia,function = "spi3"; | |
88 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
89 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
90 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
91 | }; | |
92 | ||
93 | /* Apalis CAN2 on SPI4 */ | |
94 | gmi_a16_pj7 { | |
95 | nvidia,pins = "gmi_a16_pj7", | |
96 | "gmi_a17_pb0", | |
97 | "gmi_a18_pb1", | |
98 | "gmi_a19_pk7"; | |
99 | nvidia,function = "spi4"; | |
100 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
101 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
102 | }; | |
103 | /* CAN_INT2 */ | |
104 | spi2_cs2_n_pw3 { | |
105 | nvidia,pins = "spi2_cs2_n_pw3"; | |
106 | nvidia,function = "spi3"; | |
107 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
108 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
109 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
110 | }; | |
111 | ||
112 | /* Apalis I2C3 */ | |
113 | cam_i2c_scl_pbb1 { | |
114 | nvidia,pins = "cam_i2c_scl_pbb1", | |
115 | "cam_i2c_sda_pbb2"; | |
116 | nvidia,function = "i2c3"; | |
117 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
118 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
119 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
120 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
121 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
122 | }; | |
123 | ||
124 | /* Apalis MMC1 */ | |
125 | sdmmc3_clk_pa6 { | |
126 | nvidia,pins = "sdmmc3_clk_pa6", | |
127 | "sdmmc3_cmd_pa7"; | |
128 | nvidia,function = "sdmmc3"; | |
129 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
130 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
131 | }; | |
132 | sdmmc3_dat0_pb7 { | |
133 | nvidia,pins = "sdmmc3_dat0_pb7", | |
134 | "sdmmc3_dat1_pb6", | |
135 | "sdmmc3_dat2_pb5", | |
136 | "sdmmc3_dat3_pb4", | |
137 | "sdmmc3_dat4_pd1", | |
138 | "sdmmc3_dat5_pd0", | |
139 | "sdmmc3_dat6_pd3", | |
140 | "sdmmc3_dat7_pd4"; | |
141 | nvidia,function = "sdmmc3"; | |
142 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
143 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
144 | }; | |
145 | /* Apalis MMC1_CD# */ | |
146 | pv3 { | |
147 | nvidia,pins = "pv3"; | |
148 | nvidia,function = "rsvd2"; | |
149 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
150 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
151 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
152 | }; | |
153 | ||
154 | /* Apalis PWM1 */ | |
0f44de6c MZ |
155 | pu6 { |
156 | nvidia,pins = "pu6"; | |
6d0a067f MZ |
157 | nvidia,function = "pwm3"; |
158 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
159 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
160 | }; | |
161 | ||
162 | /* Apalis PWM2 */ | |
0f44de6c MZ |
163 | pu5 { |
164 | nvidia,pins = "pu5"; | |
6d0a067f MZ |
165 | nvidia,function = "pwm2"; |
166 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
167 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
168 | }; | |
169 | ||
170 | /* Apalis PWM3 */ | |
0f44de6c MZ |
171 | pu4 { |
172 | nvidia,pins = "pu4"; | |
6d0a067f MZ |
173 | nvidia,function = "pwm1"; |
174 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
175 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
176 | }; | |
177 | ||
178 | /* Apalis PWM4 */ | |
0f44de6c MZ |
179 | pu3 { |
180 | nvidia,pins = "pu3"; | |
6d0a067f MZ |
181 | nvidia,function = "pwm0"; |
182 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
183 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
184 | }; | |
185 | ||
186 | /* Apalis RESET_MOCI# */ | |
187 | gmi_rst_n_pi4 { | |
188 | nvidia,pins = "gmi_rst_n_pi4"; | |
189 | nvidia,function = "gmi"; | |
190 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
191 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
192 | }; | |
193 | ||
194 | /* Apalis SD1 */ | |
195 | sdmmc1_clk_pz0 { | |
196 | nvidia,pins = "sdmmc1_clk_pz0"; | |
197 | nvidia,function = "sdmmc1"; | |
198 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
199 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
200 | }; | |
201 | sdmmc1_cmd_pz1 { | |
202 | nvidia,pins = "sdmmc1_cmd_pz1", | |
203 | "sdmmc1_dat0_py7", | |
204 | "sdmmc1_dat1_py6", | |
205 | "sdmmc1_dat2_py5", | |
206 | "sdmmc1_dat3_py4"; | |
207 | nvidia,function = "sdmmc1"; | |
208 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
209 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
210 | }; | |
211 | /* Apalis SD1_CD# */ | |
212 | clk2_req_pcc5 { | |
213 | nvidia,pins = "clk2_req_pcc5"; | |
214 | nvidia,function = "rsvd2"; | |
215 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
216 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
217 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
218 | }; | |
219 | ||
220 | /* Apalis SPI1 */ | |
221 | spi1_sck_px5 { | |
222 | nvidia,pins = "spi1_sck_px5", | |
223 | "spi1_mosi_px4", | |
224 | "spi1_miso_px7", | |
225 | "spi1_cs0_n_px6"; | |
226 | nvidia,function = "spi1"; | |
227 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
228 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
229 | }; | |
230 | ||
231 | /* Apalis SPI2 */ | |
232 | lcd_sck_pz4 { | |
233 | nvidia,pins = "lcd_sck_pz4", | |
234 | "lcd_sdout_pn5", | |
235 | "lcd_sdin_pz2", | |
236 | "lcd_cs0_n_pn4"; | |
237 | nvidia,function = "spi5"; | |
238 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
239 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
240 | }; | |
241 | ||
242 | /* Apalis UART1 */ | |
243 | ulpi_data0 { | |
244 | nvidia,pins = "ulpi_data0_po1", | |
245 | "ulpi_data1_po2", | |
246 | "ulpi_data2_po3", | |
247 | "ulpi_data3_po4", | |
248 | "ulpi_data4_po5", | |
249 | "ulpi_data5_po6", | |
250 | "ulpi_data6_po7", | |
251 | "ulpi_data7_po0"; | |
252 | nvidia,function = "uarta"; | |
253 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
254 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
255 | }; | |
256 | ||
257 | /* Apalis UART2 */ | |
258 | ulpi_clk_py0 { | |
259 | nvidia,pins = "ulpi_clk_py0", | |
260 | "ulpi_dir_py1", | |
261 | "ulpi_nxt_py2", | |
262 | "ulpi_stp_py3"; | |
263 | nvidia,function = "uartd"; | |
264 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
265 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
266 | }; | |
267 | ||
268 | /* Apalis UART3 */ | |
269 | uart2_rxd_pc3 { | |
270 | nvidia,pins = "uart2_rxd_pc3", | |
271 | "uart2_txd_pc2"; | |
272 | nvidia,function = "uartb"; | |
273 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
274 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
275 | }; | |
276 | ||
277 | /* Apalis UART4 */ | |
278 | uart3_rxd_pw7 { | |
279 | nvidia,pins = "uart3_rxd_pw7", | |
280 | "uart3_txd_pw6"; | |
281 | nvidia,function = "uartc"; | |
282 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
283 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
284 | }; | |
285 | ||
286 | /* Apalis USBO1_EN */ | |
287 | gen2_i2c_scl_pt5 { | |
288 | nvidia,pins = "gen2_i2c_scl_pt5"; | |
289 | nvidia,function = "rsvd4"; | |
290 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
291 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
292 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
293 | }; | |
294 | ||
295 | /* Apalis USBO1_OC# */ | |
296 | gen2_i2c_sda_pt6 { | |
297 | nvidia,pins = "gen2_i2c_sda_pt6"; | |
298 | nvidia,function = "rsvd4"; | |
299 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
300 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
301 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
302 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
303 | }; | |
304 | ||
305 | /* Apalis WAKE1_MICO */ | |
306 | pv1 { | |
307 | nvidia,pins = "pv1"; | |
308 | nvidia,function = "rsvd1"; | |
309 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
310 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
311 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
312 | }; | |
313 | ||
314 | /* eMMC (On-module) */ | |
315 | sdmmc4_clk_pcc4 { | |
316 | nvidia,pins = "sdmmc4_clk_pcc4", | |
317 | "sdmmc4_rst_n_pcc3"; | |
318 | nvidia,function = "sdmmc4"; | |
319 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
320 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
321 | }; | |
322 | sdmmc4_dat0_paa0 { | |
323 | nvidia,pins = "sdmmc4_dat0_paa0", | |
324 | "sdmmc4_dat1_paa1", | |
325 | "sdmmc4_dat2_paa2", | |
326 | "sdmmc4_dat3_paa3", | |
327 | "sdmmc4_dat4_paa4", | |
328 | "sdmmc4_dat5_paa5", | |
329 | "sdmmc4_dat6_paa6", | |
330 | "sdmmc4_dat7_paa7"; | |
331 | nvidia,function = "sdmmc4"; | |
332 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
333 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
334 | }; | |
335 | ||
336 | /* LVDS Transceiver Configuration */ | |
337 | pbb0 { | |
338 | nvidia,pins = "pbb0", | |
339 | "pbb7", | |
340 | "pcc1", | |
341 | "pcc2"; | |
342 | nvidia,function = "rsvd2"; | |
343 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
344 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
345 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
346 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
347 | }; | |
348 | pbb3 { | |
349 | nvidia,pins = "pbb3", | |
350 | "pbb4", | |
351 | "pbb5", | |
352 | "pbb6"; | |
353 | nvidia,function = "displayb"; | |
354 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
355 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
356 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
357 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
358 | }; | |
359 | ||
360 | /* Power I2C (On-module) */ | |
361 | pwr_i2c_scl_pz6 { | |
362 | nvidia,pins = "pwr_i2c_scl_pz6", | |
363 | "pwr_i2c_sda_pz7"; | |
364 | nvidia,function = "i2cpwr"; | |
365 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
366 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
367 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
368 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
369 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
370 | }; | |
371 | ||
372 | /* | |
373 | * THERMD_ALERT#, unlatched I2C address pin of LM95245 | |
374 | * temperature sensor therefore requires disabling for | |
375 | * now | |
376 | */ | |
377 | lcd_dc1_pd2 { | |
378 | nvidia,pins = "lcd_dc1_pd2"; | |
379 | nvidia,function = "rsvd3"; | |
380 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
381 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
382 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
383 | }; | |
384 | ||
385 | /* TOUCH_PEN_INT# */ | |
386 | pv0 { | |
387 | nvidia,pins = "pv0"; | |
388 | nvidia,function = "rsvd1"; | |
389 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
390 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
391 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
392 | }; | |
393 | }; | |
394 | }; | |
395 | ||
396 | hdmiddc: i2c@7000c700 { | |
397 | clock-frequency = <100000>; | |
398 | }; | |
399 | ||
400 | /* | |
401 | * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and | |
402 | * touch screen controller | |
403 | */ | |
404 | i2c@7000d000 { | |
405 | status = "okay"; | |
406 | clock-frequency = <100000>; | |
407 | ||
408 | pmic: tps65911@2d { | |
409 | compatible = "ti,tps65911"; | |
410 | reg = <0x2d>; | |
411 | ||
412 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
413 | #interrupt-cells = <2>; | |
414 | interrupt-controller; | |
415 | ||
416 | ti,system-power-controller; | |
417 | ||
418 | #gpio-cells = <2>; | |
419 | gpio-controller; | |
420 | ||
421 | vcc1-supply = <&sys_3v3_reg>; | |
422 | vcc2-supply = <&sys_3v3_reg>; | |
423 | vcc3-supply = <&vio_reg>; | |
424 | vcc4-supply = <&sys_3v3_reg>; | |
425 | vcc5-supply = <&sys_3v3_reg>; | |
426 | vcc6-supply = <&vio_reg>; | |
caa9eac5 | 427 | vcc7-supply = <&charge_pump_5v0_reg>; |
6d0a067f MZ |
428 | vccio-supply = <&sys_3v3_reg>; |
429 | ||
430 | regulators { | |
431 | /* SW1: +V1.35_VDDIO_DDR */ | |
432 | vdd1_reg: vdd1 { | |
433 | regulator-name = "vddio_ddr_1v35"; | |
434 | regulator-min-microvolt = <1350000>; | |
435 | regulator-max-microvolt = <1350000>; | |
436 | regulator-always-on; | |
437 | }; | |
438 | ||
439 | /* SW2: +V1.05 */ | |
440 | vdd2_reg: vdd2 { | |
441 | regulator-name = | |
442 | "vdd_pexa,vdd_pexb,vdd_sata"; | |
443 | regulator-min-microvolt = <1050000>; | |
444 | regulator-max-microvolt = <1050000>; | |
445 | }; | |
446 | ||
447 | /* SW CTRL: +V1.0_VDD_CPU */ | |
448 | vddctrl_reg: vddctrl { | |
449 | regulator-name = "vdd_cpu,vdd_sys"; | |
450 | regulator-min-microvolt = <1150000>; | |
451 | regulator-max-microvolt = <1150000>; | |
452 | regulator-always-on; | |
453 | }; | |
454 | ||
455 | /* SWIO: +V1.8 */ | |
456 | vio_reg: vio { | |
457 | regulator-name = "vdd_1v8_gen"; | |
458 | regulator-min-microvolt = <1800000>; | |
459 | regulator-max-microvolt = <1800000>; | |
460 | regulator-always-on; | |
461 | }; | |
462 | ||
463 | /* LDO1: unused */ | |
464 | ||
465 | /* | |
466 | * EN_+V3.3 switching via FET: | |
467 | * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN | |
468 | * see also v3_3 fixed supply | |
469 | */ | |
470 | ldo2_reg: ldo2 { | |
471 | regulator-name = "en_3v3"; | |
472 | regulator-min-microvolt = <3300000>; | |
473 | regulator-max-microvolt = <3300000>; | |
474 | regulator-always-on; | |
475 | }; | |
476 | ||
477 | /* +V1.2_CSI */ | |
478 | ldo3_reg: ldo3 { | |
479 | regulator-name = | |
480 | "avdd_dsi_csi,pwrdet_mipi"; | |
481 | regulator-min-microvolt = <1200000>; | |
482 | regulator-max-microvolt = <1200000>; | |
483 | }; | |
484 | ||
485 | /* +V1.2_VDD_RTC */ | |
486 | ldo4_reg: ldo4 { | |
487 | regulator-name = "vdd_rtc"; | |
488 | regulator-min-microvolt = <1200000>; | |
489 | regulator-max-microvolt = <1200000>; | |
490 | regulator-always-on; | |
491 | }; | |
492 | ||
493 | /* | |
494 | * +V2.8_AVDD_VDAC: | |
495 | * only required for analog RGB | |
496 | */ | |
497 | ldo5_reg: ldo5 { | |
498 | regulator-name = "avdd_vdac"; | |
499 | regulator-min-microvolt = <2800000>; | |
500 | regulator-max-microvolt = <2800000>; | |
501 | regulator-always-on; | |
502 | }; | |
503 | ||
504 | /* | |
505 | * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V | |
506 | * but LDO6 can't set voltage in 50mV | |
507 | * granularity | |
508 | */ | |
509 | ldo6_reg: ldo6 { | |
510 | regulator-name = "avdd_plle"; | |
511 | regulator-min-microvolt = <1100000>; | |
512 | regulator-max-microvolt = <1100000>; | |
513 | }; | |
514 | ||
515 | /* +V1.2_AVDD_PLL */ | |
516 | ldo7_reg: ldo7 { | |
517 | regulator-name = "avdd_pll"; | |
518 | regulator-min-microvolt = <1200000>; | |
519 | regulator-max-microvolt = <1200000>; | |
520 | regulator-always-on; | |
521 | }; | |
522 | ||
523 | /* +V1.0_VDD_DDR_HS */ | |
524 | ldo8_reg: ldo8 { | |
525 | regulator-name = "vdd_ddr_hs"; | |
526 | regulator-min-microvolt = <1000000>; | |
527 | regulator-max-microvolt = <1000000>; | |
528 | regulator-always-on; | |
529 | }; | |
530 | }; | |
531 | }; | |
532 | ||
533 | /* STMPE811 touch screen controller */ | |
534 | stmpe811@41 { | |
535 | compatible = "st,stmpe811"; | |
536 | #address-cells = <1>; | |
537 | #size-cells = <0>; | |
538 | reg = <0x41>; | |
539 | interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; | |
540 | interrupt-parent = <&gpio>; | |
541 | interrupt-controller; | |
542 | id = <0>; | |
543 | blocks = <0x5>; | |
544 | irq-trigger = <0x1>; | |
545 | ||
546 | stmpe_touchscreen { | |
547 | compatible = "st,stmpe-ts"; | |
548 | reg = <0>; | |
549 | /* 3.25 MHz ADC clock speed */ | |
550 | st,adc-freq = <1>; | |
551 | /* 8 sample average control */ | |
552 | st,ave-ctrl = <3>; | |
553 | /* 7 length fractional part in z */ | |
554 | st,fraction-z = <7>; | |
555 | /* | |
556 | * 50 mA typical 80 mA max touchscreen drivers | |
557 | * current limit value | |
558 | */ | |
559 | st,i-drive = <1>; | |
560 | /* 12-bit ADC */ | |
561 | st,mod-12b = <1>; | |
562 | /* internal ADC reference */ | |
563 | st,ref-sel = <0>; | |
564 | /* ADC converstion time: 80 clocks */ | |
565 | st,sample-time = <4>; | |
566 | /* 1 ms panel driver settling time */ | |
567 | st,settling = <3>; | |
568 | /* 5 ms touch detect interrupt delay */ | |
569 | st,touch-det-delay = <5>; | |
570 | }; | |
571 | }; | |
572 | ||
573 | /* | |
574 | * LM95245 temperature sensor | |
575 | * Note: OVERT_N directly connected to PMIC PWRDN | |
576 | */ | |
577 | temp-sensor@4c { | |
578 | compatible = "national,lm95245"; | |
579 | reg = <0x4c>; | |
580 | }; | |
581 | ||
582 | /* SW: +V1.2_VDD_CORE */ | |
583 | tps62362@60 { | |
584 | compatible = "ti,tps62362"; | |
585 | reg = <0x60>; | |
586 | ||
587 | regulator-name = "tps62362-vout"; | |
588 | regulator-min-microvolt = <900000>; | |
589 | regulator-max-microvolt = <1400000>; | |
590 | regulator-boot-on; | |
591 | regulator-always-on; | |
592 | ti,vsel0-state-low; | |
593 | /* VSEL1: EN_CORE_DVFS_N low for DVFS */ | |
594 | ti,vsel1-state-low; | |
595 | }; | |
596 | }; | |
597 | ||
598 | /* SPI4: CAN2 */ | |
599 | spi@7000da00 { | |
600 | status = "okay"; | |
601 | spi-max-frequency = <10000000>; | |
602 | ||
603 | can@1 { | |
604 | compatible = "microchip,mcp2515"; | |
605 | reg = <1>; | |
606 | clocks = <&clk16m>; | |
607 | interrupt-parent = <&gpio>; | |
608 | interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>; | |
609 | spi-max-frequency = <10000000>; | |
610 | }; | |
611 | }; | |
612 | ||
613 | /* SPI6: CAN1 */ | |
614 | spi@7000de00 { | |
615 | status = "okay"; | |
616 | spi-max-frequency = <10000000>; | |
617 | ||
618 | can@0 { | |
619 | compatible = "microchip,mcp2515"; | |
620 | reg = <0>; | |
621 | clocks = <&clk16m>; | |
622 | interrupt-parent = <&gpio>; | |
623 | interrupts = <TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; | |
624 | spi-max-frequency = <10000000>; | |
625 | }; | |
626 | }; | |
627 | ||
628 | pmc@7000e400 { | |
629 | nvidia,invert-interrupt; | |
630 | nvidia,suspend-mode = <1>; | |
631 | nvidia,cpu-pwr-good-time = <5000>; | |
632 | nvidia,cpu-pwr-off-time = <5000>; | |
633 | nvidia,core-pwr-good-time = <3845 3845>; | |
634 | nvidia,core-pwr-off-time = <0>; | |
635 | nvidia,core-power-req-active-high; | |
636 | nvidia,sys-clock-req-active-high; | |
637 | }; | |
638 | ||
639 | sdhci@78000600 { | |
640 | status = "okay"; | |
641 | bus-width = <8>; | |
642 | non-removable; | |
643 | }; | |
644 | ||
645 | clocks { | |
646 | compatible = "simple-bus"; | |
647 | #address-cells = <1>; | |
648 | #size-cells = <0>; | |
649 | ||
650 | clk32k_in: clk@0 { | |
651 | compatible = "fixed-clock"; | |
652 | reg=<0>; | |
653 | #clock-cells = <0>; | |
654 | clock-frequency = <32768>; | |
655 | }; | |
656 | clk16m: clk@1 { | |
657 | compatible = "fixed-clock"; | |
658 | reg=<1>; | |
659 | #clock-cells = <0>; | |
660 | clock-frequency = <16000000>; | |
661 | clock-output-names = "clk16m"; | |
662 | }; | |
663 | }; | |
664 | ||
665 | regulators { | |
666 | compatible = "simple-bus"; | |
667 | #address-cells = <1>; | |
668 | #size-cells = <0>; | |
669 | ||
654b7d6a | 670 | avdd_hdmi_pll_1v8_reg: regulator@100 { |
6d0a067f MZ |
671 | compatible = "regulator-fixed"; |
672 | reg = <100>; | |
654b7d6a MZ |
673 | regulator-name = "+V1.8_AVDD_HDMI_PLL"; |
674 | regulator-min-microvolt = <1800000>; | |
675 | regulator-max-microvolt = <1800000>; | |
676 | enable-active-high; | |
677 | gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; | |
678 | vin-supply = <&vio_reg>; | |
679 | }; | |
680 | ||
681 | sys_3v3_reg: regulator@101 { | |
682 | compatible = "regulator-fixed"; | |
683 | reg = <101>; | |
6d0a067f MZ |
684 | regulator-name = "3v3"; |
685 | regulator-min-microvolt = <3300000>; | |
686 | regulator-max-microvolt = <3300000>; | |
687 | regulator-always-on; | |
688 | }; | |
caa9eac5 | 689 | |
654b7d6a | 690 | avdd_hdmi_3v3_reg: regulator@102 { |
caa9eac5 | 691 | compatible = "regulator-fixed"; |
654b7d6a MZ |
692 | reg = <102>; |
693 | regulator-name = "+V3.3_AVDD_HDMI"; | |
694 | regulator-min-microvolt = <3300000>; | |
695 | regulator-max-microvolt = <3300000>; | |
696 | enable-active-high; | |
697 | gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; | |
698 | vin-supply = <&sys_3v3_reg>; | |
699 | }; | |
700 | ||
701 | charge_pump_5v0_reg: regulator@103 { | |
702 | compatible = "regulator-fixed"; | |
703 | reg = <103>; | |
caa9eac5 MZ |
704 | regulator-name = "5v0"; |
705 | regulator-min-microvolt = <5000000>; | |
706 | regulator-max-microvolt = <5000000>; | |
707 | regulator-always-on; | |
708 | }; | |
6d0a067f MZ |
709 | }; |
710 | }; |