Commit | Line | Data |
---|---|---|
05849c93 | 1 | #include <dt-bindings/clock/tegra30-car.h> |
3325f1bc | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
6d9adf6f | 3 | #include <dt-bindings/memory/tegra30-mc.h> |
a47c662a | 4 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
6cecf916 | 5 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
3325f1bc | 6 | |
1bd0bd49 | 7 | #include "skeleton.dtsi" |
c3e00a0e PDS |
8 | |
9 | / { | |
10 | compatible = "nvidia,tegra30"; | |
870c81a4 | 11 | interrupt-parent = <&lic>; |
c3e00a0e | 12 | |
58ecb23f | 13 | pcie-controller@00003000 { |
e07e3dbd TR |
14 | compatible = "nvidia,tegra30-pcie"; |
15 | device_type = "pci"; | |
16 | reg = <0x00003000 0x00000800 /* PADS registers */ | |
17 | 0x00003800 0x00000200 /* AFI registers */ | |
18 | 0x10000000 0x10000000>; /* configuration space */ | |
19 | reg-names = "pads", "afi", "cs"; | |
20 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ | |
21 | GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ | |
22 | interrupt-names = "intr", "msi"; | |
23 | ||
97070bd4 LS |
24 | #interrupt-cells = <1>; |
25 | interrupt-map-mask = <0 0 0 0>; | |
26 | interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
27 | ||
e07e3dbd TR |
28 | bus-range = <0x00 0xff>; |
29 | #address-cells = <3>; | |
30 | #size-cells = <2>; | |
31 | ||
32 | ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ | |
33 | 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ | |
34 | 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ | |
35 | 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ | |
d7283c11 JA |
36 | 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ |
37 | 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ | |
e07e3dbd TR |
38 | |
39 | clocks = <&tegra_car TEGRA30_CLK_PCIE>, | |
40 | <&tegra_car TEGRA30_CLK_AFI>, | |
e07e3dbd TR |
41 | <&tegra_car TEGRA30_CLK_PLL_E>, |
42 | <&tegra_car TEGRA30_CLK_CML0>; | |
2bd541ff | 43 | clock-names = "pex", "afi", "pll_e", "cml"; |
3393d422 | 44 | resets = <&tegra_car 70>, |
d8b316b2 MZ |
45 | <&tegra_car 72>, |
46 | <&tegra_car 74>; | |
3393d422 | 47 | reset-names = "pex", "afi", "pcie_x"; |
e07e3dbd TR |
48 | status = "disabled"; |
49 | ||
50 | pci@1,0 { | |
51 | device_type = "pci"; | |
52 | assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; | |
53 | reg = <0x000800 0 0 0 0>; | |
54 | status = "disabled"; | |
55 | ||
56 | #address-cells = <3>; | |
57 | #size-cells = <2>; | |
58 | ranges; | |
59 | ||
60 | nvidia,num-lanes = <2>; | |
61 | }; | |
62 | ||
63 | pci@2,0 { | |
64 | device_type = "pci"; | |
65 | assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; | |
66 | reg = <0x001000 0 0 0 0>; | |
67 | status = "disabled"; | |
68 | ||
69 | #address-cells = <3>; | |
70 | #size-cells = <2>; | |
71 | ranges; | |
72 | ||
73 | nvidia,num-lanes = <2>; | |
74 | }; | |
75 | ||
76 | pci@3,0 { | |
77 | device_type = "pci"; | |
78 | assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; | |
79 | reg = <0x001800 0 0 0 0>; | |
80 | status = "disabled"; | |
81 | ||
82 | #address-cells = <3>; | |
83 | #size-cells = <2>; | |
84 | ranges; | |
85 | ||
86 | nvidia,num-lanes = <2>; | |
87 | }; | |
88 | }; | |
89 | ||
58ecb23f | 90 | host1x@50000000 { |
ed39097c TR |
91 | compatible = "nvidia,tegra30-host1x", "simple-bus"; |
92 | reg = <0x50000000 0x00024000>; | |
6cecf916 SW |
93 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
94 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ | |
05849c93 | 95 | clocks = <&tegra_car TEGRA30_CLK_HOST1X>; |
3393d422 SW |
96 | resets = <&tegra_car 28>; |
97 | reset-names = "host1x"; | |
ed39097c TR |
98 | |
99 | #address-cells = <1>; | |
100 | #size-cells = <1>; | |
101 | ||
102 | ranges = <0x54000000 0x54000000 0x04000000>; | |
103 | ||
58ecb23f | 104 | mpe@54040000 { |
ed39097c TR |
105 | compatible = "nvidia,tegra30-mpe"; |
106 | reg = <0x54040000 0x00040000>; | |
6cecf916 | 107 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 108 | clocks = <&tegra_car TEGRA30_CLK_MPE>; |
3393d422 SW |
109 | resets = <&tegra_car 60>; |
110 | reset-names = "mpe"; | |
ed39097c TR |
111 | }; |
112 | ||
58ecb23f | 113 | vi@54080000 { |
ed39097c TR |
114 | compatible = "nvidia,tegra30-vi"; |
115 | reg = <0x54080000 0x00040000>; | |
6cecf916 | 116 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 117 | clocks = <&tegra_car TEGRA30_CLK_VI>; |
3393d422 SW |
118 | resets = <&tegra_car 20>; |
119 | reset-names = "vi"; | |
ed39097c TR |
120 | }; |
121 | ||
58ecb23f | 122 | epp@540c0000 { |
ed39097c TR |
123 | compatible = "nvidia,tegra30-epp"; |
124 | reg = <0x540c0000 0x00040000>; | |
6cecf916 | 125 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 126 | clocks = <&tegra_car TEGRA30_CLK_EPP>; |
3393d422 SW |
127 | resets = <&tegra_car 19>; |
128 | reset-names = "epp"; | |
ed39097c TR |
129 | }; |
130 | ||
58ecb23f | 131 | isp@54100000 { |
ed39097c TR |
132 | compatible = "nvidia,tegra30-isp"; |
133 | reg = <0x54100000 0x00040000>; | |
6cecf916 | 134 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 135 | clocks = <&tegra_car TEGRA30_CLK_ISP>; |
3393d422 SW |
136 | resets = <&tegra_car 23>; |
137 | reset-names = "isp"; | |
ed39097c TR |
138 | }; |
139 | ||
58ecb23f | 140 | gr2d@54140000 { |
ed39097c TR |
141 | compatible = "nvidia,tegra30-gr2d"; |
142 | reg = <0x54140000 0x00040000>; | |
6cecf916 | 143 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
da45d738 | 144 | clocks = <&tegra_car TEGRA30_CLK_GR2D>; |
3393d422 SW |
145 | resets = <&tegra_car 21>; |
146 | reset-names = "2d"; | |
ed39097c TR |
147 | }; |
148 | ||
58ecb23f | 149 | gr3d@54180000 { |
ed39097c TR |
150 | compatible = "nvidia,tegra30-gr3d"; |
151 | reg = <0x54180000 0x00040000>; | |
c71d3909 TR |
152 | clocks = <&tegra_car TEGRA30_CLK_GR3D |
153 | &tegra_car TEGRA30_CLK_GR3D2>; | |
1cbc733d | 154 | clock-names = "3d", "3d2"; |
3393d422 | 155 | resets = <&tegra_car 24>, |
d8b316b2 | 156 | <&tegra_car 98>; |
3393d422 | 157 | reset-names = "3d", "3d2"; |
ed39097c TR |
158 | }; |
159 | ||
160 | dc@54200000 { | |
05465f4e | 161 | compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; |
ed39097c | 162 | reg = <0x54200000 0x00040000>; |
6cecf916 | 163 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 HD |
164 | clocks = <&tegra_car TEGRA30_CLK_DISP1>, |
165 | <&tegra_car TEGRA30_CLK_PLL_P>; | |
d8f64797 | 166 | clock-names = "dc", "parent"; |
3393d422 SW |
167 | resets = <&tegra_car 27>; |
168 | reset-names = "dc"; | |
ed39097c | 169 | |
6d9adf6f TR |
170 | iommus = <&mc TEGRA_SWGROUP_DC>; |
171 | ||
688b56b4 TR |
172 | nvidia,head = <0>; |
173 | ||
ed39097c TR |
174 | rgb { |
175 | status = "disabled"; | |
176 | }; | |
177 | }; | |
178 | ||
179 | dc@54240000 { | |
180 | compatible = "nvidia,tegra30-dc"; | |
181 | reg = <0x54240000 0x00040000>; | |
6cecf916 | 182 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 HD |
183 | clocks = <&tegra_car TEGRA30_CLK_DISP2>, |
184 | <&tegra_car TEGRA30_CLK_PLL_P>; | |
d8f64797 | 185 | clock-names = "dc", "parent"; |
3393d422 SW |
186 | resets = <&tegra_car 26>; |
187 | reset-names = "dc"; | |
ed39097c | 188 | |
6d9adf6f TR |
189 | iommus = <&mc TEGRA_SWGROUP_DCB>; |
190 | ||
688b56b4 TR |
191 | nvidia,head = <1>; |
192 | ||
ed39097c TR |
193 | rgb { |
194 | status = "disabled"; | |
195 | }; | |
196 | }; | |
197 | ||
58ecb23f | 198 | hdmi@54280000 { |
ed39097c TR |
199 | compatible = "nvidia,tegra30-hdmi"; |
200 | reg = <0x54280000 0x00040000>; | |
6cecf916 | 201 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 HD |
202 | clocks = <&tegra_car TEGRA30_CLK_HDMI>, |
203 | <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; | |
1cbc733d | 204 | clock-names = "hdmi", "parent"; |
3393d422 SW |
205 | resets = <&tegra_car 51>; |
206 | reset-names = "hdmi"; | |
ed39097c TR |
207 | status = "disabled"; |
208 | }; | |
209 | ||
58ecb23f | 210 | tvo@542c0000 { |
ed39097c TR |
211 | compatible = "nvidia,tegra30-tvo"; |
212 | reg = <0x542c0000 0x00040000>; | |
6cecf916 | 213 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 214 | clocks = <&tegra_car TEGRA30_CLK_TVO>; |
ed39097c TR |
215 | status = "disabled"; |
216 | }; | |
217 | ||
58ecb23f | 218 | dsi@54300000 { |
ed39097c TR |
219 | compatible = "nvidia,tegra30-dsi"; |
220 | reg = <0x54300000 0x00040000>; | |
05849c93 | 221 | clocks = <&tegra_car TEGRA30_CLK_DSIA>; |
3393d422 SW |
222 | resets = <&tegra_car 48>; |
223 | reset-names = "dsi"; | |
ed39097c TR |
224 | status = "disabled"; |
225 | }; | |
226 | }; | |
227 | ||
2cda1880 | 228 | timer@50040600 { |
73368ba0 SW |
229 | compatible = "arm,cortex-a9-twd-timer"; |
230 | reg = <0x50040600 0x20>; | |
870c81a4 | 231 | interrupt-parent = <&intc>; |
6cecf916 SW |
232 | interrupts = <GIC_PPI 13 |
233 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
05849c93 | 234 | clocks = <&tegra_car TEGRA30_CLK_TWD>; |
73368ba0 SW |
235 | }; |
236 | ||
58ecb23f | 237 | intc: interrupt-controller@50041000 { |
c3e00a0e | 238 | compatible = "arm,cortex-a9-gic"; |
5ff48887 SW |
239 | reg = <0x50041000 0x1000 |
240 | 0x50040100 0x0100>; | |
2eaab06e SW |
241 | interrupt-controller; |
242 | #interrupt-cells = <3>; | |
870c81a4 | 243 | interrupt-parent = <&intc>; |
c3e00a0e PDS |
244 | }; |
245 | ||
58ecb23f | 246 | cache-controller@50043000 { |
bb2c1de9 SW |
247 | compatible = "arm,pl310-cache"; |
248 | reg = <0x50043000 0x1000>; | |
249 | arm,data-latency = <6 6 2>; | |
250 | arm,tag-latency = <5 5 2>; | |
251 | cache-unified; | |
252 | cache-level = <2>; | |
253 | }; | |
254 | ||
870c81a4 MZ |
255 | lic: interrupt-controller@60004000 { |
256 | compatible = "nvidia,tegra30-ictlr"; | |
257 | reg = <0x60004000 0x100>, | |
258 | <0x60004100 0x50>, | |
259 | <0x60004200 0x50>, | |
260 | <0x60004300 0x50>, | |
261 | <0x60004400 0x50>; | |
262 | interrupt-controller; | |
263 | #interrupt-cells = <3>; | |
264 | interrupt-parent = <&intc>; | |
265 | }; | |
266 | ||
2f2b7fb2 SW |
267 | timer@60005000 { |
268 | compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; | |
269 | reg = <0x60005000 0x400>; | |
6cecf916 SW |
270 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
271 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
272 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
273 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
274 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
275 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; | |
05849c93 | 276 | clocks = <&tegra_car TEGRA30_CLK_TIMER>; |
2f2b7fb2 SW |
277 | }; |
278 | ||
58ecb23f | 279 | tegra_car: clock@60006000 { |
95985667 PG |
280 | compatible = "nvidia,tegra30-car"; |
281 | reg = <0x60006000 0x1000>; | |
282 | #clock-cells = <1>; | |
3393d422 | 283 | #reset-cells = <1>; |
95985667 PG |
284 | }; |
285 | ||
b1023134 TR |
286 | flow-controller@60007000 { |
287 | compatible = "nvidia,tegra30-flowctrl"; | |
288 | reg = <0x60007000 0x1000>; | |
289 | }; | |
290 | ||
58ecb23f | 291 | apbdma: dma@6000a000 { |
8051b75a SW |
292 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
293 | reg = <0x6000a000 0x1400>; | |
6cecf916 SW |
294 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
295 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
296 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
297 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
298 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
299 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
300 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
301 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
302 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
303 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
304 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
305 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
306 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
307 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
308 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
309 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, | |
310 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
311 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | |
312 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | |
313 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
314 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, | |
315 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, | |
316 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
317 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
318 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
319 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
320 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
321 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, | |
322 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, | |
323 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, | |
324 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
325 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
05849c93 | 326 | clocks = <&tegra_car TEGRA30_CLK_APBDMA>; |
3393d422 SW |
327 | resets = <&tegra_car 34>; |
328 | reset-names = "dma"; | |
034d023f | 329 | #dma-cells = <1>; |
8051b75a SW |
330 | }; |
331 | ||
0d5ccb38 | 332 | ahb: ahb@6000c000 { |
c04abb3a | 333 | compatible = "nvidia,tegra30-ahb"; |
0d5ccb38 | 334 | reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ |
c3e00a0e PDS |
335 | }; |
336 | ||
58ecb23f | 337 | gpio: gpio@6000d000 { |
35f210ec | 338 | compatible = "nvidia,tegra30-gpio"; |
95decf84 | 339 | reg = <0x6000d000 0x1000>; |
6cecf916 SW |
340 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
341 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
342 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
343 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
344 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
345 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
346 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, | |
347 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; | |
c3e00a0e PDS |
348 | #gpio-cells = <2>; |
349 | gpio-controller; | |
6f74dc9b SW |
350 | #interrupt-cells = <2>; |
351 | interrupt-controller; | |
4f1d8414 | 352 | /* |
17cdddf0 | 353 | gpio-ranges = <&pinmux 0 0 248>; |
4f1d8414 | 354 | */ |
c3e00a0e PDS |
355 | }; |
356 | ||
155dfc7b PDS |
357 | apbmisc@70000800 { |
358 | compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; | |
359 | reg = <0x70000800 0x64 /* Chip revision */ | |
360 | 0x70000008 0x04>; /* Strapping options */ | |
361 | }; | |
362 | ||
58ecb23f | 363 | pinmux: pinmux@70000868 { |
c04abb3a | 364 | compatible = "nvidia,tegra30-pinmux"; |
322337b8 PR |
365 | reg = <0x70000868 0xd4 /* Pad control registers */ |
366 | 0x70003000 0x3e4>; /* Mux registers */ | |
c04abb3a SW |
367 | }; |
368 | ||
b6551bb9 LD |
369 | /* |
370 | * There are two serial driver i.e. 8250 based simple serial | |
371 | * driver and APB DMA based serial driver for higher baudrate | |
372 | * and performace. To enable the 8250 based driver, the compatible | |
373 | * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable | |
374 | * the APB DMA based serial driver, the comptible is | |
375 | * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". | |
376 | */ | |
377 | uarta: serial@70006000 { | |
c3e00a0e PDS |
378 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
379 | reg = <0x70006000 0x40>; | |
380 | reg-shift = <2>; | |
6cecf916 | 381 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 382 | clocks = <&tegra_car TEGRA30_CLK_UARTA>; |
3393d422 SW |
383 | resets = <&tegra_car 6>; |
384 | reset-names = "serial"; | |
034d023f SW |
385 | dmas = <&apbdma 8>, <&apbdma 8>; |
386 | dma-names = "rx", "tx"; | |
223ef78d | 387 | status = "disabled"; |
c3e00a0e PDS |
388 | }; |
389 | ||
b6551bb9 | 390 | uartb: serial@70006040 { |
c3e00a0e PDS |
391 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
392 | reg = <0x70006040 0x40>; | |
393 | reg-shift = <2>; | |
6cecf916 | 394 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 395 | clocks = <&tegra_car TEGRA30_CLK_UARTB>; |
3393d422 SW |
396 | resets = <&tegra_car 7>; |
397 | reset-names = "serial"; | |
034d023f SW |
398 | dmas = <&apbdma 9>, <&apbdma 9>; |
399 | dma-names = "rx", "tx"; | |
223ef78d | 400 | status = "disabled"; |
c3e00a0e PDS |
401 | }; |
402 | ||
b6551bb9 | 403 | uartc: serial@70006200 { |
c3e00a0e PDS |
404 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
405 | reg = <0x70006200 0x100>; | |
406 | reg-shift = <2>; | |
6cecf916 | 407 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 408 | clocks = <&tegra_car TEGRA30_CLK_UARTC>; |
3393d422 SW |
409 | resets = <&tegra_car 55>; |
410 | reset-names = "serial"; | |
034d023f SW |
411 | dmas = <&apbdma 10>, <&apbdma 10>; |
412 | dma-names = "rx", "tx"; | |
223ef78d | 413 | status = "disabled"; |
c3e00a0e PDS |
414 | }; |
415 | ||
b6551bb9 | 416 | uartd: serial@70006300 { |
c3e00a0e PDS |
417 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
418 | reg = <0x70006300 0x100>; | |
419 | reg-shift = <2>; | |
6cecf916 | 420 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 421 | clocks = <&tegra_car TEGRA30_CLK_UARTD>; |
3393d422 SW |
422 | resets = <&tegra_car 65>; |
423 | reset-names = "serial"; | |
034d023f SW |
424 | dmas = <&apbdma 19>, <&apbdma 19>; |
425 | dma-names = "rx", "tx"; | |
223ef78d | 426 | status = "disabled"; |
c3e00a0e PDS |
427 | }; |
428 | ||
b6551bb9 | 429 | uarte: serial@70006400 { |
c3e00a0e PDS |
430 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
431 | reg = <0x70006400 0x100>; | |
432 | reg-shift = <2>; | |
6cecf916 | 433 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 434 | clocks = <&tegra_car TEGRA30_CLK_UARTE>; |
3393d422 SW |
435 | resets = <&tegra_car 66>; |
436 | reset-names = "serial"; | |
034d023f SW |
437 | dmas = <&apbdma 20>, <&apbdma 20>; |
438 | dma-names = "rx", "tx"; | |
223ef78d | 439 | status = "disabled"; |
c3e00a0e PDS |
440 | }; |
441 | ||
58ecb23f | 442 | pwm: pwm@7000a000 { |
140fd977 TR |
443 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; |
444 | reg = <0x7000a000 0x100>; | |
445 | #pwm-cells = <2>; | |
05849c93 | 446 | clocks = <&tegra_car TEGRA30_CLK_PWM>; |
3393d422 SW |
447 | resets = <&tegra_car 17>; |
448 | reset-names = "pwm"; | |
b69cd984 | 449 | status = "disabled"; |
140fd977 TR |
450 | }; |
451 | ||
58ecb23f | 452 | rtc@7000e000 { |
380e04ac SW |
453 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; |
454 | reg = <0x7000e000 0x100>; | |
6cecf916 | 455 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 456 | clocks = <&tegra_car TEGRA30_CLK_RTC>; |
380e04ac SW |
457 | }; |
458 | ||
c04abb3a | 459 | i2c@7000c000 { |
d8b316b2 | 460 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
c04abb3a | 461 | reg = <0x7000c000 0x100>; |
6cecf916 | 462 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
463 | #address-cells = <1>; |
464 | #size-cells = <0>; | |
05849c93 HD |
465 | clocks = <&tegra_car TEGRA30_CLK_I2C1>, |
466 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 467 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
468 | resets = <&tegra_car 12>; |
469 | reset-names = "i2c"; | |
034d023f SW |
470 | dmas = <&apbdma 21>, <&apbdma 21>; |
471 | dma-names = "rx", "tx"; | |
223ef78d | 472 | status = "disabled"; |
c3e00a0e PDS |
473 | }; |
474 | ||
c04abb3a | 475 | i2c@7000c400 { |
c04abb3a SW |
476 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
477 | reg = <0x7000c400 0x100>; | |
6cecf916 | 478 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
479 | #address-cells = <1>; |
480 | #size-cells = <0>; | |
05849c93 HD |
481 | clocks = <&tegra_car TEGRA30_CLK_I2C2>, |
482 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 483 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
484 | resets = <&tegra_car 54>; |
485 | reset-names = "i2c"; | |
034d023f SW |
486 | dmas = <&apbdma 22>, <&apbdma 22>; |
487 | dma-names = "rx", "tx"; | |
223ef78d | 488 | status = "disabled"; |
c3e00a0e PDS |
489 | }; |
490 | ||
c04abb3a | 491 | i2c@7000c500 { |
c04abb3a SW |
492 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
493 | reg = <0x7000c500 0x100>; | |
6cecf916 | 494 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
495 | #address-cells = <1>; |
496 | #size-cells = <0>; | |
05849c93 HD |
497 | clocks = <&tegra_car TEGRA30_CLK_I2C3>, |
498 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 499 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
500 | resets = <&tegra_car 67>; |
501 | reset-names = "i2c"; | |
034d023f SW |
502 | dmas = <&apbdma 23>, <&apbdma 23>; |
503 | dma-names = "rx", "tx"; | |
223ef78d | 504 | status = "disabled"; |
c3e00a0e PDS |
505 | }; |
506 | ||
c04abb3a | 507 | i2c@7000c700 { |
c04abb3a SW |
508 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
509 | reg = <0x7000c700 0x100>; | |
6cecf916 | 510 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
511 | #address-cells = <1>; |
512 | #size-cells = <0>; | |
05849c93 HD |
513 | clocks = <&tegra_car TEGRA30_CLK_I2C4>, |
514 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
3393d422 SW |
515 | resets = <&tegra_car 103>; |
516 | reset-names = "i2c"; | |
1cbc733d | 517 | clock-names = "div-clk", "fast-clk"; |
034d023f SW |
518 | dmas = <&apbdma 26>, <&apbdma 26>; |
519 | dma-names = "rx", "tx"; | |
223ef78d | 520 | status = "disabled"; |
c3e00a0e PDS |
521 | }; |
522 | ||
c04abb3a | 523 | i2c@7000d000 { |
c04abb3a SW |
524 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
525 | reg = <0x7000d000 0x100>; | |
6cecf916 | 526 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
527 | #address-cells = <1>; |
528 | #size-cells = <0>; | |
05849c93 HD |
529 | clocks = <&tegra_car TEGRA30_CLK_I2C5>, |
530 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 531 | clock-names = "div-clk", "fast-clk"; |
3393d422 SW |
532 | resets = <&tegra_car 47>; |
533 | reset-names = "i2c"; | |
034d023f SW |
534 | dmas = <&apbdma 24>, <&apbdma 24>; |
535 | dma-names = "rx", "tx"; | |
223ef78d | 536 | status = "disabled"; |
c04abb3a SW |
537 | }; |
538 | ||
a86b0db3 LD |
539 | spi@7000d400 { |
540 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
541 | reg = <0x7000d400 0x200>; | |
6cecf916 | 542 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
543 | #address-cells = <1>; |
544 | #size-cells = <0>; | |
05849c93 | 545 | clocks = <&tegra_car TEGRA30_CLK_SBC1>; |
3393d422 SW |
546 | resets = <&tegra_car 41>; |
547 | reset-names = "spi"; | |
034d023f SW |
548 | dmas = <&apbdma 15>, <&apbdma 15>; |
549 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
550 | status = "disabled"; |
551 | }; | |
552 | ||
553 | spi@7000d600 { | |
554 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
555 | reg = <0x7000d600 0x200>; | |
6cecf916 | 556 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
557 | #address-cells = <1>; |
558 | #size-cells = <0>; | |
05849c93 | 559 | clocks = <&tegra_car TEGRA30_CLK_SBC2>; |
3393d422 SW |
560 | resets = <&tegra_car 44>; |
561 | reset-names = "spi"; | |
034d023f SW |
562 | dmas = <&apbdma 16>, <&apbdma 16>; |
563 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
564 | status = "disabled"; |
565 | }; | |
566 | ||
567 | spi@7000d800 { | |
568 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
57471c8d | 569 | reg = <0x7000d800 0x200>; |
6cecf916 | 570 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
571 | #address-cells = <1>; |
572 | #size-cells = <0>; | |
05849c93 | 573 | clocks = <&tegra_car TEGRA30_CLK_SBC3>; |
3393d422 SW |
574 | resets = <&tegra_car 46>; |
575 | reset-names = "spi"; | |
034d023f SW |
576 | dmas = <&apbdma 17>, <&apbdma 17>; |
577 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
578 | status = "disabled"; |
579 | }; | |
580 | ||
581 | spi@7000da00 { | |
582 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
583 | reg = <0x7000da00 0x200>; | |
6cecf916 | 584 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
585 | #address-cells = <1>; |
586 | #size-cells = <0>; | |
05849c93 | 587 | clocks = <&tegra_car TEGRA30_CLK_SBC4>; |
3393d422 SW |
588 | resets = <&tegra_car 68>; |
589 | reset-names = "spi"; | |
034d023f SW |
590 | dmas = <&apbdma 18>, <&apbdma 18>; |
591 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
592 | status = "disabled"; |
593 | }; | |
594 | ||
595 | spi@7000dc00 { | |
596 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
597 | reg = <0x7000dc00 0x200>; | |
6cecf916 | 598 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
599 | #address-cells = <1>; |
600 | #size-cells = <0>; | |
05849c93 | 601 | clocks = <&tegra_car TEGRA30_CLK_SBC5>; |
3393d422 SW |
602 | resets = <&tegra_car 104>; |
603 | reset-names = "spi"; | |
034d023f SW |
604 | dmas = <&apbdma 27>, <&apbdma 27>; |
605 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
606 | status = "disabled"; |
607 | }; | |
608 | ||
609 | spi@7000de00 { | |
610 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
611 | reg = <0x7000de00 0x200>; | |
6cecf916 | 612 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
613 | #address-cells = <1>; |
614 | #size-cells = <0>; | |
05849c93 | 615 | clocks = <&tegra_car TEGRA30_CLK_SBC6>; |
3393d422 SW |
616 | resets = <&tegra_car 106>; |
617 | reset-names = "spi"; | |
034d023f SW |
618 | dmas = <&apbdma 28>, <&apbdma 28>; |
619 | dma-names = "rx", "tx"; | |
a86b0db3 LD |
620 | status = "disabled"; |
621 | }; | |
622 | ||
58ecb23f | 623 | kbc@7000e200 { |
699ed4b9 LD |
624 | compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; |
625 | reg = <0x7000e200 0x100>; | |
6cecf916 | 626 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 627 | clocks = <&tegra_car TEGRA30_CLK_KBC>; |
3393d422 SW |
628 | resets = <&tegra_car 36>; |
629 | reset-names = "kbc"; | |
699ed4b9 LD |
630 | status = "disabled"; |
631 | }; | |
632 | ||
58ecb23f | 633 | pmc@7000e400 { |
2b84e53b | 634 | compatible = "nvidia,tegra30-pmc"; |
c04abb3a | 635 | reg = <0x7000e400 0x400>; |
05849c93 | 636 | clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; |
7021d122 | 637 | clock-names = "pclk", "clk32k_in"; |
c04abb3a SW |
638 | }; |
639 | ||
a9fe468f | 640 | mc: memory-controller@7000f000 { |
c04abb3a | 641 | compatible = "nvidia,tegra30-mc"; |
a9fe468f TR |
642 | reg = <0x7000f000 0x400>; |
643 | clocks = <&tegra_car TEGRA30_CLK_MC>; | |
644 | clock-names = "mc"; | |
645 | ||
6cecf916 | 646 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
c04abb3a | 647 | |
a9fe468f | 648 | #iommu-cells = <1>; |
c3e00a0e | 649 | }; |
9ee6a5c4 | 650 | |
155dfc7b PDS |
651 | fuse@7000f800 { |
652 | compatible = "nvidia,tegra30-efuse"; | |
653 | reg = <0x7000f800 0x400>; | |
654 | clocks = <&tegra_car TEGRA30_CLK_FUSE>; | |
655 | clock-names = "fuse"; | |
656 | resets = <&tegra_car 39>; | |
657 | reset-names = "fuse"; | |
658 | }; | |
659 | ||
cbee2613 MZ |
660 | hda@70030000 { |
661 | compatible = "nvidia,tegra30-hda"; | |
662 | reg = <0x70030000 0x10000>; | |
663 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
664 | clocks = <&tegra_car TEGRA30_CLK_HDA>, | |
d8b316b2 | 665 | <&tegra_car TEGRA30_CLK_HDA2HDMI>, |
cbee2613 MZ |
666 | <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; |
667 | clock-names = "hda", "hda2hdmi", "hda2codec_2x"; | |
668 | resets = <&tegra_car 125>, /* hda */ | |
669 | <&tegra_car 128>, /* hda2hdmi */ | |
670 | <&tegra_car 111>; /* hda2codec_2x */ | |
671 | reset-names = "hda", "hda2hdmi", "hda2codec_2x"; | |
672 | status = "disabled"; | |
673 | }; | |
674 | ||
58ecb23f | 675 | ahub@70080000 { |
9ee6a5c4 | 676 | compatible = "nvidia,tegra30-ahub"; |
5ff48887 SW |
677 | reg = <0x70080000 0x200 |
678 | 0x70080200 0x100>; | |
6cecf916 | 679 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 680 | clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, |
2bd541ff SW |
681 | <&tegra_car TEGRA30_CLK_APBIF>; |
682 | clock-names = "d_audio", "apbif"; | |
3393d422 SW |
683 | resets = <&tegra_car 106>, /* d_audio */ |
684 | <&tegra_car 107>, /* apbif */ | |
685 | <&tegra_car 30>, /* i2s0 */ | |
686 | <&tegra_car 11>, /* i2s1 */ | |
687 | <&tegra_car 18>, /* i2s2 */ | |
688 | <&tegra_car 101>, /* i2s3 */ | |
689 | <&tegra_car 102>, /* i2s4 */ | |
690 | <&tegra_car 108>, /* dam0 */ | |
691 | <&tegra_car 109>, /* dam1 */ | |
692 | <&tegra_car 110>, /* dam2 */ | |
693 | <&tegra_car 10>; /* spdif */ | |
694 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", | |
695 | "i2s3", "i2s4", "dam0", "dam1", "dam2", | |
696 | "spdif"; | |
034d023f SW |
697 | dmas = <&apbdma 1>, <&apbdma 1>, |
698 | <&apbdma 2>, <&apbdma 2>, | |
699 | <&apbdma 3>, <&apbdma 3>, | |
700 | <&apbdma 4>, <&apbdma 4>; | |
701 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", | |
702 | "rx3", "tx3"; | |
9ee6a5c4 SW |
703 | ranges; |
704 | #address-cells = <1>; | |
705 | #size-cells = <1>; | |
706 | ||
707 | tegra_i2s0: i2s@70080300 { | |
708 | compatible = "nvidia,tegra30-i2s"; | |
709 | reg = <0x70080300 0x100>; | |
710 | nvidia,ahub-cif-ids = <4 4>; | |
05849c93 | 711 | clocks = <&tegra_car TEGRA30_CLK_I2S0>; |
3393d422 SW |
712 | resets = <&tegra_car 30>; |
713 | reset-names = "i2s"; | |
223ef78d | 714 | status = "disabled"; |
9ee6a5c4 SW |
715 | }; |
716 | ||
717 | tegra_i2s1: i2s@70080400 { | |
718 | compatible = "nvidia,tegra30-i2s"; | |
719 | reg = <0x70080400 0x100>; | |
720 | nvidia,ahub-cif-ids = <5 5>; | |
05849c93 | 721 | clocks = <&tegra_car TEGRA30_CLK_I2S1>; |
3393d422 SW |
722 | resets = <&tegra_car 11>; |
723 | reset-names = "i2s"; | |
223ef78d | 724 | status = "disabled"; |
9ee6a5c4 SW |
725 | }; |
726 | ||
727 | tegra_i2s2: i2s@70080500 { | |
728 | compatible = "nvidia,tegra30-i2s"; | |
729 | reg = <0x70080500 0x100>; | |
730 | nvidia,ahub-cif-ids = <6 6>; | |
05849c93 | 731 | clocks = <&tegra_car TEGRA30_CLK_I2S2>; |
3393d422 SW |
732 | resets = <&tegra_car 18>; |
733 | reset-names = "i2s"; | |
223ef78d | 734 | status = "disabled"; |
9ee6a5c4 SW |
735 | }; |
736 | ||
737 | tegra_i2s3: i2s@70080600 { | |
738 | compatible = "nvidia,tegra30-i2s"; | |
739 | reg = <0x70080600 0x100>; | |
740 | nvidia,ahub-cif-ids = <7 7>; | |
05849c93 | 741 | clocks = <&tegra_car TEGRA30_CLK_I2S3>; |
3393d422 SW |
742 | resets = <&tegra_car 101>; |
743 | reset-names = "i2s"; | |
223ef78d | 744 | status = "disabled"; |
9ee6a5c4 SW |
745 | }; |
746 | ||
747 | tegra_i2s4: i2s@70080700 { | |
748 | compatible = "nvidia,tegra30-i2s"; | |
749 | reg = <0x70080700 0x100>; | |
750 | nvidia,ahub-cif-ids = <8 8>; | |
05849c93 | 751 | clocks = <&tegra_car TEGRA30_CLK_I2S4>; |
3393d422 SW |
752 | resets = <&tegra_car 102>; |
753 | reset-names = "i2s"; | |
223ef78d | 754 | status = "disabled"; |
9ee6a5c4 SW |
755 | }; |
756 | }; | |
7868a9bc | 757 | |
c04abb3a SW |
758 | sdhci@78000000 { |
759 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
760 | reg = <0x78000000 0x200>; | |
6cecf916 | 761 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 762 | clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; |
3393d422 SW |
763 | resets = <&tegra_car 14>; |
764 | reset-names = "sdhci"; | |
223ef78d | 765 | status = "disabled"; |
7868a9bc | 766 | }; |
ecf43742 | 767 | |
c04abb3a SW |
768 | sdhci@78000200 { |
769 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
770 | reg = <0x78000200 0x200>; | |
6cecf916 | 771 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 772 | clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; |
3393d422 SW |
773 | resets = <&tegra_car 9>; |
774 | reset-names = "sdhci"; | |
223ef78d | 775 | status = "disabled"; |
ecf43742 | 776 | }; |
54174a33 | 777 | |
c04abb3a SW |
778 | sdhci@78000400 { |
779 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
780 | reg = <0x78000400 0x200>; | |
6cecf916 | 781 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 782 | clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; |
3393d422 SW |
783 | resets = <&tegra_car 69>; |
784 | reset-names = "sdhci"; | |
223ef78d | 785 | status = "disabled"; |
c04abb3a SW |
786 | }; |
787 | ||
788 | sdhci@78000600 { | |
789 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
790 | reg = <0x78000600 0x200>; | |
6cecf916 | 791 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 792 | clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; |
3393d422 SW |
793 | resets = <&tegra_car 15>; |
794 | reset-names = "sdhci"; | |
223ef78d | 795 | status = "disabled"; |
c04abb3a SW |
796 | }; |
797 | ||
cc34c9f7 TT |
798 | usb@7d000000 { |
799 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; | |
800 | reg = <0x7d000000 0x4000>; | |
801 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
802 | phy_type = "utmi"; | |
803 | clocks = <&tegra_car TEGRA30_CLK_USBD>; | |
3393d422 SW |
804 | resets = <&tegra_car 22>; |
805 | reset-names = "usb"; | |
cc34c9f7 TT |
806 | nvidia,needs-double-reset; |
807 | nvidia,phy = <&phy1>; | |
808 | status = "disabled"; | |
809 | }; | |
810 | ||
811 | phy1: usb-phy@7d000000 { | |
812 | compatible = "nvidia,tegra30-usb-phy"; | |
813 | reg = <0x7d000000 0x4000 0x7d000000 0x4000>; | |
814 | phy_type = "utmi"; | |
815 | clocks = <&tegra_car TEGRA30_CLK_USBD>, | |
816 | <&tegra_car TEGRA30_CLK_PLL_U>, | |
817 | <&tegra_car TEGRA30_CLK_USBD>; | |
818 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
819 | resets = <&tegra_car 22>, <&tegra_car 22>; |
820 | reset-names = "usb", "utmi-pads"; | |
cc34c9f7 TT |
821 | nvidia,hssync-start-delay = <9>; |
822 | nvidia,idle-wait-delay = <17>; | |
823 | nvidia,elastic-limit = <16>; | |
824 | nvidia,term-range-adj = <6>; | |
825 | nvidia,xcvr-setup = <51>; | |
826 | nvidia.xcvr-setup-use-fuses; | |
827 | nvidia,xcvr-lsfslew = <1>; | |
828 | nvidia,xcvr-lsrslew = <1>; | |
829 | nvidia,xcvr-hsslew = <32>; | |
830 | nvidia,hssquelch-level = <2>; | |
831 | nvidia,hsdiscon-level = <5>; | |
308efde2 | 832 | nvidia,has-utmi-pad-registers; |
cc34c9f7 TT |
833 | status = "disabled"; |
834 | }; | |
835 | ||
836 | usb@7d004000 { | |
837 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; | |
838 | reg = <0x7d004000 0x4000>; | |
839 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
fd6441ec | 840 | phy_type = "utmi"; |
cc34c9f7 | 841 | clocks = <&tegra_car TEGRA30_CLK_USB2>; |
3393d422 SW |
842 | resets = <&tegra_car 58>; |
843 | reset-names = "usb"; | |
cc34c9f7 TT |
844 | nvidia,phy = <&phy2>; |
845 | status = "disabled"; | |
846 | }; | |
847 | ||
848 | phy2: usb-phy@7d004000 { | |
849 | compatible = "nvidia,tegra30-usb-phy"; | |
fd6441ec EB |
850 | reg = <0x7d004000 0x4000 0x7d000000 0x4000>; |
851 | phy_type = "utmi"; | |
cc34c9f7 TT |
852 | clocks = <&tegra_car TEGRA30_CLK_USB2>, |
853 | <&tegra_car TEGRA30_CLK_PLL_U>, | |
fd6441ec EB |
854 | <&tegra_car TEGRA30_CLK_USBD>; |
855 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
856 | resets = <&tegra_car 58>, <&tegra_car 22>; |
857 | reset-names = "usb", "utmi-pads"; | |
fd6441ec EB |
858 | nvidia,hssync-start-delay = <9>; |
859 | nvidia,idle-wait-delay = <17>; | |
860 | nvidia,elastic-limit = <16>; | |
861 | nvidia,term-range-adj = <6>; | |
862 | nvidia,xcvr-setup = <51>; | |
863 | nvidia.xcvr-setup-use-fuses; | |
864 | nvidia,xcvr-lsfslew = <2>; | |
865 | nvidia,xcvr-lsrslew = <2>; | |
866 | nvidia,xcvr-hsslew = <32>; | |
867 | nvidia,hssquelch-level = <2>; | |
868 | nvidia,hsdiscon-level = <5>; | |
cc34c9f7 TT |
869 | status = "disabled"; |
870 | }; | |
871 | ||
872 | usb@7d008000 { | |
873 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; | |
874 | reg = <0x7d008000 0x4000>; | |
875 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
876 | phy_type = "utmi"; | |
877 | clocks = <&tegra_car TEGRA30_CLK_USB3>; | |
3393d422 SW |
878 | resets = <&tegra_car 59>; |
879 | reset-names = "usb"; | |
cc34c9f7 TT |
880 | nvidia,phy = <&phy3>; |
881 | status = "disabled"; | |
882 | }; | |
883 | ||
884 | phy3: usb-phy@7d008000 { | |
885 | compatible = "nvidia,tegra30-usb-phy"; | |
886 | reg = <0x7d008000 0x4000 0x7d000000 0x4000>; | |
887 | phy_type = "utmi"; | |
888 | clocks = <&tegra_car TEGRA30_CLK_USB3>, | |
889 | <&tegra_car TEGRA30_CLK_PLL_U>, | |
890 | <&tegra_car TEGRA30_CLK_USBD>; | |
891 | clock-names = "reg", "pll_u", "utmi-pads"; | |
308efde2 TT |
892 | resets = <&tegra_car 59>, <&tegra_car 22>; |
893 | reset-names = "usb", "utmi-pads"; | |
cc34c9f7 TT |
894 | nvidia,hssync-start-delay = <0>; |
895 | nvidia,idle-wait-delay = <17>; | |
896 | nvidia,elastic-limit = <16>; | |
897 | nvidia,term-range-adj = <6>; | |
898 | nvidia,xcvr-setup = <51>; | |
899 | nvidia.xcvr-setup-use-fuses; | |
900 | nvidia,xcvr-lsfslew = <2>; | |
901 | nvidia,xcvr-lsrslew = <2>; | |
902 | nvidia,xcvr-hsslew = <32>; | |
903 | nvidia,hssquelch-level = <2>; | |
904 | nvidia,hsdiscon-level = <5>; | |
905 | status = "disabled"; | |
906 | }; | |
907 | ||
7d19a34a HD |
908 | cpus { |
909 | #address-cells = <1>; | |
910 | #size-cells = <0>; | |
911 | ||
912 | cpu@0 { | |
913 | device_type = "cpu"; | |
914 | compatible = "arm,cortex-a9"; | |
915 | reg = <0>; | |
916 | }; | |
917 | ||
918 | cpu@1 { | |
919 | device_type = "cpu"; | |
920 | compatible = "arm,cortex-a9"; | |
921 | reg = <1>; | |
922 | }; | |
923 | ||
924 | cpu@2 { | |
925 | device_type = "cpu"; | |
926 | compatible = "arm,cortex-a9"; | |
927 | reg = <2>; | |
928 | }; | |
929 | ||
930 | cpu@3 { | |
931 | device_type = "cpu"; | |
932 | compatible = "arm,cortex-a9"; | |
933 | reg = <3>; | |
934 | }; | |
935 | }; | |
936 | ||
c04abb3a SW |
937 | pmu { |
938 | compatible = "arm,cortex-a9-pmu"; | |
6cecf916 SW |
939 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
940 | <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, | |
941 | <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, | |
942 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; | |
54174a33 | 943 | }; |
c3e00a0e | 944 | }; |