[deliverable/linux.git] / arch / arm / boot / dts / vexpress-v2m-rs1.dtsi

/*
 * ARM Ltd. Versatile Express
 *
 * Motherboard Express uATX
 * V2M-P1
 *
 * HBI-0190D
 *
 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
 * Technical Reference Manual)
 *
 * WARNING! The hardware described in this file is independent from the
 * original variant (vexpress-v2m.dtsi), but there is a strong
 * correspondence between the two configurations.
 *
 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
 * CHANGES TO vexpress-v2m.dtsi!
 */

	motherboard {
		model = "V2M-P1";
		arm,hbi = <0x190>;
		arm,vexpress,site = <0>;
		arm,v2m-memory-map = "rs1";
		compatible = "arm,vexpress,v2m-p1", "simple-bus";
		#address-cells = <2>; /* SMB chipselect number and offset */
		#size-cells = <1>;
		#interrupt-cells = <1>;
		ranges;

		flash@0,00000000 {
			compatible = "arm,vexpress-flash", "cfi-flash";
			reg = <0 0x00000000 0x04000000>,
			      <4 0x00000000 0x04000000>;
			bank-width = <4>;
		};

		psram@1,00000000 {
			compatible = "arm,vexpress-psram", "mtd-ram";
			reg = <1 0x00000000 0x02000000>;
			bank-width = <4>;
		};

		v2m_video_ram: vram@2,00000000 {
			compatible = "arm,vexpress-vram";
			reg = <2 0x00000000 0x00800000>;
		};

		ethernet@2,02000000 {
			compatible = "smsc,lan9118", "smsc,lan9115";
			reg = <2 0x02000000 0x10000>;
			interrupts = <15>;
			phy-mode = "mii";
			reg-io-width = <4>;
			smsc,irq-active-high;
			smsc,irq-push-pull;
			vdd33a-supply = <&v2m_fixed_3v3>;
			vddvario-supply = <&v2m_fixed_3v3>;
		};

		usb@2,03000000 {
			compatible = "nxp,usb-isp1761";
			reg = <2 0x03000000 0x20000>;
			interrupts = <16>;
			port1-otg;
		};

		iofpga@3,00000000 {
			compatible = "arm,amba-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 3 0 0x200000>;

			v2m_sysreg: sysreg@010000 {
				compatible = "arm,vexpress-sysreg";
				reg = <0x010000 0x1000>;

				v2m_led_gpios: sys_led@08 {
					compatible = "arm,vexpress-sysreg,sys_led";
					gpio-controller;
					#gpio-cells = <2>;
				};

				v2m_mmc_gpios: sys_mci@48 {
					compatible = "arm,vexpress-sysreg,sys_mci";
					gpio-controller;
					#gpio-cells = <2>;
				};

				v2m_flash_gpios: sys_flash@4c {
					compatible = "arm,vexpress-sysreg,sys_flash";
					gpio-controller;
					#gpio-cells = <2>;
				};
			};

			v2m_sysctl: sysctl@020000 {
				compatible = "arm,sp810", "arm,primecell";
				reg = <0x020000 0x1000>;
				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
				clock-names = "refclk", "timclk", "apb_pclk";
				#clock-cells = <1>;
				clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
			};

			/* PCI-E I2C bus */
			v2m_i2c_pcie: i2c@030000 {
				compatible = "arm,versatile-i2c";
				reg = <0x030000 0x1000>;

				#address-cells = <1>;
				#size-cells = <0>;

				pcie-switch@60 {
					compatible = "idt,89hpes32h8";
					reg = <0x60>;
				};
			};

			aaci@040000 {
				compatible = "arm,pl041", "arm,primecell";
				reg = <0x040000 0x1000>;
				interrupts = <11>;
				clocks = <&smbclk>;
				clock-names = "apb_pclk";
			};

			mmci@050000 {
				compatible = "arm,pl180", "arm,primecell";
				reg = <0x050000 0x1000>;
				interrupts = <9 10>;
				cd-gpios = <&v2m_mmc_gpios 0 0>;
				wp-gpios = <&v2m_mmc_gpios 1 0>;
				max-frequency = <12000000>;
				vmmc-supply = <&v2m_fixed_3v3>;
				clocks = <&v2m_clk24mhz>, <&smbclk>;
				clock-names = "mclk", "apb_pclk";
			};

			kmi@060000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x060000 0x1000>;
				interrupts = <12>;
				clocks = <&v2m_clk24mhz>, <&smbclk>;
				clock-names = "KMIREFCLK", "apb_pclk";
			};

			kmi@070000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x070000 0x1000>;
				interrupts = <13>;
				clocks = <&v2m_clk24mhz>, <&smbclk>;
				clock-names = "KMIREFCLK", "apb_pclk";
			};

			v2m_serial0: uart@090000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x090000 0x1000>;
				interrupts = <5>;
				clocks = <&v2m_oscclk2>, <&smbclk>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial1: uart@0a0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0a0000 0x1000>;
				interrupts = <6>;
				clocks = <&v2m_oscclk2>, <&smbclk>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial2: uart@0b0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0b0000 0x1000>;
				interrupts = <7>;
				clocks = <&v2m_oscclk2>, <&smbclk>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial3: uart@0c0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0c0000 0x1000>;
				interrupts = <8>;
				clocks = <&v2m_oscclk2>, <&smbclk>;
				clock-names = "uartclk", "apb_pclk";
			};

			wdt@0f0000 {
				compatible = "arm,sp805", "arm,primecell";
				reg = <0x0f0000 0x1000>;
				interrupts = <0>;
				clocks = <&v2m_refclk32khz>, <&smbclk>;
				clock-names = "wdogclk", "apb_pclk";
			};

			v2m_timer01: timer@110000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x110000 0x1000>;
				interrupts = <2>;
				clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
				clock-names = "timclken1", "timclken2", "apb_pclk";
			};

			v2m_timer23: timer@120000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x120000 0x1000>;
				interrupts = <3>;
				clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
				clock-names = "timclken1", "timclken2", "apb_pclk";
			};

			/* DVI I2C bus */
			v2m_i2c_dvi: i2c@160000 {
				compatible = "arm,versatile-i2c";
				reg = <0x160000 0x1000>;

				#address-cells = <1>;
				#size-cells = <0>;

				dvi-transmitter@39 {
					compatible = "sil,sii9022-tpi", "sil,sii9022";
					reg = <0x39>;
				};

				dvi-transmitter@60 {
					compatible = "sil,sii9022-cpi", "sil,sii9022";
					reg = <0x60>;
				};
			};

			rtc@170000 {
				compatible = "arm,pl031", "arm,primecell";
				reg = <0x170000 0x1000>;
				interrupts = <4>;
				clocks = <&smbclk>;
				clock-names = "apb_pclk";
			};

			compact-flash@1a0000 {
				compatible = "arm,vexpress-cf", "ata-generic";
				reg = <0x1a0000 0x100
				       0x1a0100 0xf00>;
				reg-shift = <2>;
			};

			clcd@1f0000 {
				compatible = "arm,pl111", "arm,primecell";
				reg = <0x1f0000 0x1000>;
				interrupt-names = "combined";
				interrupts = <14>;
				clocks = <&v2m_oscclk1>, <&smbclk>;
				clock-names = "clcdclk", "apb_pclk";
				memory-region = <&v2m_video_ram>;
				max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */

				port {
					v2m_clcd_pads: endpoint {
						remote-endpoint = <&v2m_clcd_panel>;
						arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
					};
				};

				panel {
					compatible = "panel-dpi";

					port {
						v2m_clcd_panel: endpoint {
							remote-endpoint = <&v2m_clcd_pads>;
						};
					};

					panel-timing {
						clock-frequency = <25175000>;
						hactive = <640>;
						hback-porch = <40>;
						hfront-porch = <24>;
						hsync-len = <96>;
						vactive = <480>;
						vback-porch = <32>;
						vfront-porch = <11>;
						vsync-len = <2>;
					};
				};
			};
		};

		v2m_fixed_3v3: fixedregulator@0 {
			compatible = "regulator-fixed";
			regulator-name = "3V3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		v2m_clk24mhz: clk24mhz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
			clock-output-names = "v2m:clk24mhz";
		};

		v2m_refclk1mhz: refclk1mhz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1000000>;
			clock-output-names = "v2m:refclk1mhz";
		};

		v2m_refclk32khz: refclk32khz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
			clock-output-names = "v2m:refclk32khz";
		};

		leds {
			compatible = "gpio-leds";

			user@1 {
				label = "v2m:green:user1";
				gpios = <&v2m_led_gpios 0 0>;
				linux,default-trigger = "heartbeat";
			};

			user@2 {
				label = "v2m:green:user2";
				gpios = <&v2m_led_gpios 1 0>;
				linux,default-trigger = "mmc0";
			};

			user@3 {
				label = "v2m:green:user3";
				gpios = <&v2m_led_gpios 2 0>;
				linux,default-trigger = "cpu0";
			};

			user@4 {
				label = "v2m:green:user4";
				gpios = <&v2m_led_gpios 3 0>;
				linux,default-trigger = "cpu1";
			};

			user@5 {
				label = "v2m:green:user5";
				gpios = <&v2m_led_gpios 4 0>;
				linux,default-trigger = "cpu2";
			};

			user@6 {
				label = "v2m:green:user6";
				gpios = <&v2m_led_gpios 5 0>;
				linux,default-trigger = "cpu3";
			};

			user@7 {
				label = "v2m:green:user7";
				gpios = <&v2m_led_gpios 6 0>;
				linux,default-trigger = "cpu4";
			};

			user@8 {
				label = "v2m:green:user8";
				gpios = <&v2m_led_gpios 7 0>;
				linux,default-trigger = "cpu5";
			};
		};

		mcc {
			compatible = "arm,vexpress,config-bus";
			arm,vexpress,config-bridge = <&v2m_sysreg>;

			osc@0 {
				/* MCC static memory clock */
				compatible = "arm,vexpress-osc";
				arm,vexpress-sysreg,func = <1 0>;
				freq-range = <25000000 60000000>;
				#clock-cells = <0>;
				clock-output-names = "v2m:oscclk0";
			};

			v2m_oscclk1: osc@1 {
				/* CLCD clock */
				compatible = "arm,vexpress-osc";
				arm,vexpress-sysreg,func = <1 1>;
				freq-range = <23750000 65000000>;
				#clock-cells = <0>;
				clock-output-names = "v2m:oscclk1";
			};

			v2m_oscclk2: osc@2 {
				/* IO FPGA peripheral clock */
				compatible = "arm,vexpress-osc";
				arm,vexpress-sysreg,func = <1 2>;
				freq-range = <24000000 24000000>;
				#clock-cells = <0>;
				clock-output-names = "v2m:oscclk2";
			};

			volt@0 {
				/* Logic level voltage */
				compatible = "arm,vexpress-volt";
				arm,vexpress-sysreg,func = <2 0>;
				regulator-name = "VIO";
				regulator-always-on;
				label = "VIO";
			};

			temp@0 {
				/* MCC internal operating temperature */
				compatible = "arm,vexpress-temp";
				arm,vexpress-sysreg,func = <4 0>;
				label = "MCC";
			};

			reset@0 {
				compatible = "arm,vexpress-reset";
				arm,vexpress-sysreg,func = <5 0>;
			};

			muxfpga@0 {
				compatible = "arm,vexpress-muxfpga";
				arm,vexpress-sysreg,func = <7 0>;
			};

			shutdown@0 {
				compatible = "arm,vexpress-shutdown";
				arm,vexpress-sysreg,func = <8 0>;
			};

			reboot@0 {
				compatible = "arm,vexpress-reboot";
				arm,vexpress-sysreg,func = <9 0>;
			};

			dvimode@0 {
				compatible = "arm,vexpress-dvimode";
				arm,vexpress-sysreg,func = <11 0>;
			};
		};
	};
Commit	Line	Data
6a371956 PM	1	/*
	2	* ARM Ltd. Versatile Express
	3	*
	4	* Motherboard Express uATX
	5	* V2M-P1
	6	*
	7	* HBI-0190D
	8	*
	9	* RS1 memory map ("ARM Cortex-A Series memory map" in the board's
	10	* Technical Reference Manual)
	11	*
	12	* WARNING! The hardware described in this file is independent from the
	13	* original variant (vexpress-v2m.dtsi), but there is a strong
	14	* correspondence between the two configurations.
	15	*
	16	* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
	17	* CHANGES TO vexpress-v2m.dtsi!
	18	*/
	19
6a371956	20	motherboard {
433683a6 PM	21	model = "V2M-P1";
433683a6 PM	22	arm,hbi = <0x190>;
842839a3	23	arm,vexpress,site = <0>;
6a371956	24	arm,v2m-memory-map = "rs1";
433683a6	25	compatible = "arm,vexpress,v2m-p1", "simple-bus";
6a371956 PM	26	#address-cells = <2>; /* SMB chipselect number and offset */
	27	#size-cells = <1>;
	28	#interrupt-cells = <1>;
433683a6	29	ranges;
6a371956 PM	30
	31	flash@0,00000000 {
	32	compatible = "arm,vexpress-flash", "cfi-flash";
	33	reg = <0 0x00000000 0x04000000>,
	34	<4 0x00000000 0x04000000>;
	35	bank-width = <4>;
	36	};
	37
	38	psram@1,00000000 {
	39	compatible = "arm,vexpress-psram", "mtd-ram";
	40	reg = <1 0x00000000 0x02000000>;
	41	bank-width = <4>;
	42	};
	43
478a4f81	44	v2m_video_ram: vram@2,00000000 {
6a371956 PM	45	compatible = "arm,vexpress-vram";
	46	reg = <2 0x00000000 0x00800000>;
	47	};
	48
	49	ethernet@2,02000000 {
	50	compatible = "smsc,lan9118", "smsc,lan9115";
	51	reg = <2 0x02000000 0x10000>;
	52	interrupts = <15>;
	53	phy-mode = "mii";
	54	reg-io-width = <4>;
	55	smsc,irq-active-high;
	56	smsc,irq-push-pull;
b2a54ff0 PM	57	vdd33a-supply = <&v2m_fixed_3v3>;
b2a54ff0 PM	58	vddvario-supply = <&v2m_fixed_3v3>;
6a371956 PM	59	};
	60
	61	usb@2,03000000 {
	62	compatible = "nxp,usb-isp1761";
	63	reg = <2 0x03000000 0x20000>;
	64	interrupts = <16>;
	65	port1-otg;
	66	};
	67
	68	iofpga@3,00000000 {
	69	compatible = "arm,amba-bus", "simple-bus";
	70	#address-cells = <1>;
	71	#size-cells = <1>;
	72	ranges = <0 3 0 0x200000>;
	73
842839a3	74	v2m_sysreg: sysreg@010000 {
6a371956 PM	75	compatible = "arm,vexpress-sysreg";
6a371956 PM	76	reg = <0x010000 0x1000>;
974cc7b9 PM	77
	78	v2m_led_gpios: sys_led@08 {
	79	compatible = "arm,vexpress-sysreg,sys_led";
	80	gpio-controller;
	81	#gpio-cells = <2>;
	82	};
	83
	84	v2m_mmc_gpios: sys_mci@48 {
	85	compatible = "arm,vexpress-sysreg,sys_mci";
	86	gpio-controller;
	87	#gpio-cells = <2>;
	88	};
	89
	90	v2m_flash_gpios: sys_flash@4c {
	91	compatible = "arm,vexpress-sysreg,sys_flash";
	92	gpio-controller;
	93	#gpio-cells = <2>;
	94	};
6a371956 PM	95	};
6a371956 PM	96
842839a3	97	v2m_sysctl: sysctl@020000 {
6a371956 PM	98	compatible = "arm,sp810", "arm,primecell";
6a371956 PM	99	reg = <0x020000 0x1000>;
842839a3 PM	100	clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
	101	clock-names = "refclk", "timclk", "apb_pclk";
	102	#clock-cells = <1>;
	103	clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
6a371956 PM	104	};
	105
	106	/* PCI-E I2C bus */
	107	v2m_i2c_pcie: i2c@030000 {
	108	compatible = "arm,versatile-i2c";
	109	reg = <0x030000 0x1000>;
	110
	111	#address-cells = <1>;
	112	#size-cells = <0>;
	113
	114	pcie-switch@60 {
	115	compatible = "idt,89hpes32h8";
	116	reg = <0x60>;
	117	};
	118	};
	119
	120	aaci@040000 {
	121	compatible = "arm,pl041", "arm,primecell";
	122	reg = <0x040000 0x1000>;
	123	interrupts = <11>;
842839a3 PM	124	clocks = <&smbclk>;
842839a3 PM	125	clock-names = "apb_pclk";
6a371956 PM	126	};
	127
	128	mmci@050000 {
	129	compatible = "arm,pl180", "arm,primecell";
	130	reg = <0x050000 0x1000>;
	131	interrupts = <9 10>;
974cc7b9 PM	132	cd-gpios = <&v2m_mmc_gpios 0 0>;
974cc7b9 PM	133	wp-gpios = <&v2m_mmc_gpios 1 0>;
842839a3 PM	134	max-frequency = <12000000>;
	135	vmmc-supply = <&v2m_fixed_3v3>;
	136	clocks = <&v2m_clk24mhz>, <&smbclk>;
	137	clock-names = "mclk", "apb_pclk";
6a371956 PM	138	};
	139
	140	kmi@060000 {
	141	compatible = "arm,pl050", "arm,primecell";
	142	reg = <0x060000 0x1000>;
	143	interrupts = <12>;
842839a3 PM	144	clocks = <&v2m_clk24mhz>, <&smbclk>;
842839a3 PM	145	clock-names = "KMIREFCLK", "apb_pclk";
6a371956 PM	146	};
	147
	148	kmi@070000 {
	149	compatible = "arm,pl050", "arm,primecell";
	150	reg = <0x070000 0x1000>;
	151	interrupts = <13>;
842839a3 PM	152	clocks = <&v2m_clk24mhz>, <&smbclk>;
842839a3 PM	153	clock-names = "KMIREFCLK", "apb_pclk";
6a371956 PM	154	};
	155
	156	v2m_serial0: uart@090000 {
	157	compatible = "arm,pl011", "arm,primecell";
	158	reg = <0x090000 0x1000>;
	159	interrupts = <5>;
842839a3 PM	160	clocks = <&v2m_oscclk2>, <&smbclk>;
842839a3 PM	161	clock-names = "uartclk", "apb_pclk";
6a371956 PM	162	};
	163
	164	v2m_serial1: uart@0a0000 {
	165	compatible = "arm,pl011", "arm,primecell";
	166	reg = <0x0a0000 0x1000>;
	167	interrupts = <6>;
842839a3 PM	168	clocks = <&v2m_oscclk2>, <&smbclk>;
842839a3 PM	169	clock-names = "uartclk", "apb_pclk";
6a371956 PM	170	};
	171
	172	v2m_serial2: uart@0b0000 {
	173	compatible = "arm,pl011", "arm,primecell";
	174	reg = <0x0b0000 0x1000>;
	175	interrupts = <7>;
842839a3 PM	176	clocks = <&v2m_oscclk2>, <&smbclk>;
842839a3 PM	177	clock-names = "uartclk", "apb_pclk";
6a371956 PM	178	};
	179
	180	v2m_serial3: uart@0c0000 {
	181	compatible = "arm,pl011", "arm,primecell";
	182	reg = <0x0c0000 0x1000>;
	183	interrupts = <8>;
842839a3 PM	184	clocks = <&v2m_oscclk2>, <&smbclk>;
842839a3 PM	185	clock-names = "uartclk", "apb_pclk";
6a371956 PM	186	};
	187
	188	wdt@0f0000 {
	189	compatible = "arm,sp805", "arm,primecell";
	190	reg = <0x0f0000 0x1000>;
	191	interrupts = <0>;
842839a3 PM	192	clocks = <&v2m_refclk32khz>, <&smbclk>;
842839a3 PM	193	clock-names = "wdogclk", "apb_pclk";
6a371956 PM	194	};
	195
	196	v2m_timer01: timer@110000 {
	197	compatible = "arm,sp804", "arm,primecell";
	198	reg = <0x110000 0x1000>;
	199	interrupts = <2>;
842839a3 PM	200	clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
842839a3 PM	201	clock-names = "timclken1", "timclken2", "apb_pclk";
6a371956 PM	202	};
	203
	204	v2m_timer23: timer@120000 {
	205	compatible = "arm,sp804", "arm,primecell";
	206	reg = <0x120000 0x1000>;
b7541a95	207	interrupts = <3>;
842839a3 PM	208	clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
842839a3 PM	209	clock-names = "timclken1", "timclken2", "apb_pclk";
6a371956 PM	210	};
	211
	212	/* DVI I2C bus */
	213	v2m_i2c_dvi: i2c@160000 {
	214	compatible = "arm,versatile-i2c";
	215	reg = <0x160000 0x1000>;
	216
	217	#address-cells = <1>;
	218	#size-cells = <0>;
	219
	220	dvi-transmitter@39 {
	221	compatible = "sil,sii9022-tpi", "sil,sii9022";
	222	reg = <0x39>;
	223	};
	224
	225	dvi-transmitter@60 {
	226	compatible = "sil,sii9022-cpi", "sil,sii9022";
	227	reg = <0x60>;
	228	};
	229	};
	230
	231	rtc@170000 {
	232	compatible = "arm,pl031", "arm,primecell";
	233	reg = <0x170000 0x1000>;
	234	interrupts = <4>;
842839a3 PM	235	clocks = <&smbclk>;
842839a3 PM	236	clock-names = "apb_pclk";
6a371956 PM	237	};
	238
	239	compact-flash@1a0000 {
	240	compatible = "arm,vexpress-cf", "ata-generic";
	241	reg = <0x1a0000 0x100
	242	0x1a0100 0xf00>;
	243	reg-shift = <2>;
	244	};
	245
	246	clcd@1f0000 {
	247	compatible = "arm,pl111", "arm,primecell";
	248	reg = <0x1f0000 0x1000>;
478a4f81	249	interrupt-names = "combined";
6a371956	250	interrupts = <14>;
842839a3 PM	251	clocks = <&v2m_oscclk1>, <&smbclk>;
842839a3 PM	252	clock-names = "clcdclk", "apb_pclk";
478a4f81 PM	253	memory-region = <&v2m_video_ram>;
	254	max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
	255
	256	port {
	257	v2m_clcd_pads: endpoint {
	258	remote-endpoint = <&v2m_clcd_panel>;
	259	arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
	260	};
	261	};
	262
	263	panel {
	264	compatible = "panel-dpi";
	265
	266	port {
	267	v2m_clcd_panel: endpoint {
	268	remote-endpoint = <&v2m_clcd_pads>;
	269	};
	270	};
	271
	272	panel-timing {
	273	clock-frequency = <25175000>;
	274	hactive = <640>;
	275	hback-porch = <40>;
	276	hfront-porch = <24>;
	277	hsync-len = <96>;
	278	vactive = <480>;
	279	vback-porch = <32>;
	280	vfront-porch = <11>;
	281	vsync-len = <2>;
	282	};
	283	};
6a371956 PM	284	};
6a371956 PM	285	};
b2a54ff0 PM	286
	287	v2m_fixed_3v3: fixedregulator@0 {
	288	compatible = "regulator-fixed";
	289	regulator-name = "3V3";
	290	regulator-min-microvolt = <3300000>;
	291	regulator-max-microvolt = <3300000>;
	292	regulator-always-on;
	293	};
842839a3 PM	294
	295	v2m_clk24mhz: clk24mhz {
	296	compatible = "fixed-clock";
	297	#clock-cells = <0>;
	298	clock-frequency = <24000000>;
	299	clock-output-names = "v2m:clk24mhz";
	300	};
	301
	302	v2m_refclk1mhz: refclk1mhz {
	303	compatible = "fixed-clock";
	304	#clock-cells = <0>;
	305	clock-frequency = <1000000>;
	306	clock-output-names = "v2m:refclk1mhz";
	307	};
	308
	309	v2m_refclk32khz: refclk32khz {
	310	compatible = "fixed-clock";
	311	#clock-cells = <0>;
	312	clock-frequency = <32768>;
	313	clock-output-names = "v2m:refclk32khz";
	314	};
	315
974cc7b9 PM	316	leds {
	317	compatible = "gpio-leds";
	318
	319	user@1 {
	320	label = "v2m:green:user1";
	321	gpios = <&v2m_led_gpios 0 0>;
	322	linux,default-trigger = "heartbeat";
	323	};
	324
	325	user@2 {
	326	label = "v2m:green:user2";
	327	gpios = <&v2m_led_gpios 1 0>;
	328	linux,default-trigger = "mmc0";
	329	};
	330
	331	user@3 {
	332	label = "v2m:green:user3";
	333	gpios = <&v2m_led_gpios 2 0>;
	334	linux,default-trigger = "cpu0";
	335	};
	336
	337	user@4 {
	338	label = "v2m:green:user4";
	339	gpios = <&v2m_led_gpios 3 0>;
	340	linux,default-trigger = "cpu1";
	341	};
	342
	343	user@5 {
	344	label = "v2m:green:user5";
	345	gpios = <&v2m_led_gpios 4 0>;
	346	linux,default-trigger = "cpu2";
	347	};
	348
	349	user@6 {
	350	label = "v2m:green:user6";
	351	gpios = <&v2m_led_gpios 5 0>;
	352	linux,default-trigger = "cpu3";
	353	};
	354
	355	user@7 {
	356	label = "v2m:green:user7";
	357	gpios = <&v2m_led_gpios 6 0>;
	358	linux,default-trigger = "cpu4";
	359	};
	360
	361	user@8 {
	362	label = "v2m:green:user8";
	363	gpios = <&v2m_led_gpios 7 0>;
	364	linux,default-trigger = "cpu5";
	365	};
	366	};
	367
842839a3 PM	368	mcc {
	369	compatible = "arm,vexpress,config-bus";
	370	arm,vexpress,config-bridge = <&v2m_sysreg>;
	371
	372	osc@0 {
	373	/* MCC static memory clock */
	374	compatible = "arm,vexpress-osc";
	375	arm,vexpress-sysreg,func = <1 0>;
	376	freq-range = <25000000 60000000>;
	377	#clock-cells = <0>;
	378	clock-output-names = "v2m:oscclk0";
	379	};
	380
	381	v2m_oscclk1: osc@1 {
	382	/* CLCD clock */
	383	compatible = "arm,vexpress-osc";
	384	arm,vexpress-sysreg,func = <1 1>;
478a4f81	385	freq-range = <23750000 65000000>;
842839a3 PM	386	#clock-cells = <0>;
	387	clock-output-names = "v2m:oscclk1";
	388	};
	389
	390	v2m_oscclk2: osc@2 {
	391	/* IO FPGA peripheral clock */
	392	compatible = "arm,vexpress-osc";
	393	arm,vexpress-sysreg,func = <1 2>;
	394	freq-range = <24000000 24000000>;
	395	#clock-cells = <0>;
	396	clock-output-names = "v2m:oscclk2";
	397	};
	398
	399	volt@0 {
	400	/* Logic level voltage */
	401	compatible = "arm,vexpress-volt";
	402	arm,vexpress-sysreg,func = <2 0>;
	403	regulator-name = "VIO";
	404	regulator-always-on;
	405	label = "VIO";
	406	};
	407
	408	temp@0 {
	409	/* MCC internal operating temperature */
	410	compatible = "arm,vexpress-temp";
	411	arm,vexpress-sysreg,func = <4 0>;
	412	label = "MCC";
	413	};
	414
	415	reset@0 {
	416	compatible = "arm,vexpress-reset";
	417	arm,vexpress-sysreg,func = <5 0>;
	418	};
	419
	420	muxfpga@0 {
	421	compatible = "arm,vexpress-muxfpga";
	422	arm,vexpress-sysreg,func = <7 0>;
	423	};
	424
	425	shutdown@0 {
	426	compatible = "arm,vexpress-shutdown";
	427	arm,vexpress-sysreg,func = <8 0>;
	428	};
	429
	430	reboot@0 {
	431	compatible = "arm,vexpress-reboot";
	432	arm,vexpress-sysreg,func = <9 0>;
	433	};
	434
	435	dvimode@0 {
	436	compatible = "arm,vexpress-dvimode";
	437	arm,vexpress-sysreg,func = <11 0>;
	438	};
	439	};
6a371956	440	};