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ARM: shmobile: r8a7790: tidyup SDHI register size on DTSI
[deliverable/linux.git] / arch / arm / boot / dts / vexpress-v2m.dtsi
CommitLineData
8deed178
PM		 1/*
2 * ARM Ltd. Versatile Express
3 *
4 * Motherboard Express uATX
5 * V2M-P1
6 *
7 * HBI-0190D
8 *
9 * Original memory map ("Legacy memory map" in the board's
10 * Technical Reference Manual)
11 *
12 * WARNING! The hardware described in this file is independent from the
13 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
14 * correspondence between the two configurations.
15 *
16 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
17 * CHANGES TO vexpress-v2m-rs1.dtsi!
18 */
19
8deed178 20 motherboard {
433683a6
PM		 21 model = "V2M-P1";
22 arm,hbi = <0x190>;
842839a3 23 arm,vexpress,site = <0>;
433683a6 24 compatible = "arm,vexpress,v2m-p1", "simple-bus";
8deed178
PM		 25 #address-cells = <2>; /* SMB chipselect number and offset */
26 #size-cells = <1>;
27 #interrupt-cells = <1>;
433683a6 28 ranges;
8deed178
PM		 29
30 flash@0,00000000 {
31 compatible = "arm,vexpress-flash", "cfi-flash";
32 reg = <0 0x00000000 0x04000000>,
33 <1 0x00000000 0x04000000>;
34 bank-width = <4>;
35 };
36
37 psram@2,00000000 {
38 compatible = "arm,vexpress-psram", "mtd-ram";
39 reg = <2 0x00000000 0x02000000>;
40 bank-width = <4>;
41 };
42
478a4f81 43 v2m_video_ram: vram@3,00000000 {
8deed178
PM		 44 compatible = "arm,vexpress-vram";
45 reg = <3 0x00000000 0x00800000>;
46 };
47
48 ethernet@3,02000000 {
49 compatible = "smsc,lan9118", "smsc,lan9115";
50 reg = <3 0x02000000 0x10000>;
51 interrupts = <15>;
52 phy-mode = "mii";
53 reg-io-width = <4>;
54 smsc,irq-active-high;
55 smsc,irq-push-pull;
b2a54ff0
PM		 56 vdd33a-supply = <&v2m_fixed_3v3>;
57 vddvario-supply = <&v2m_fixed_3v3>;
8deed178
PM		 58 };
59
60 usb@3,03000000 {
61 compatible = "nxp,usb-isp1761";
62 reg = <3 0x03000000 0x20000>;
63 interrupts = <16>;
64 port1-otg;
65 };
66
67 iofpga@7,00000000 {
68 compatible = "arm,amba-bus", "simple-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 ranges = <0 7 0 0x20000>;
72
842839a3 73 v2m_sysreg: sysreg@00000 {
8deed178
PM		 74 compatible = "arm,vexpress-sysreg";
75 reg = <0x00000 0x1000>;
974cc7b9
PM		 76
77 v2m_led_gpios: sys_led@08 {
78 compatible = "arm,vexpress-sysreg,sys_led";
79 gpio-controller;
80 #gpio-cells = <2>;
81 };
82
83 v2m_mmc_gpios: sys_mci@48 {
84 compatible = "arm,vexpress-sysreg,sys_mci";
85 gpio-controller;
86 #gpio-cells = <2>;
87 };
88
89 v2m_flash_gpios: sys_flash@4c {
90 compatible = "arm,vexpress-sysreg,sys_flash";
91 gpio-controller;
92 #gpio-cells = <2>;
93 };
8deed178
PM		 94 };
95
842839a3 96 v2m_sysctl: sysctl@01000 {
8deed178
PM		 97 compatible = "arm,sp810", "arm,primecell";
98 reg = <0x01000 0x1000>;
842839a3
PM		 99 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
100 clock-names = "refclk", "timclk", "apb_pclk";
101 #clock-cells = <1>;
102 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
8deed178
PM		 103 };
104
105 /* PCI-E I2C bus */
106 v2m_i2c_pcie: i2c@02000 {
107 compatible = "arm,versatile-i2c";
108 reg = <0x02000 0x1000>;
109
110 #address-cells = <1>;
111 #size-cells = <0>;
112
113 pcie-switch@60 {
114 compatible = "idt,89hpes32h8";
115 reg = <0x60>;
116 };
117 };
118
119 aaci@04000 {
120 compatible = "arm,pl041", "arm,primecell";
121 reg = <0x04000 0x1000>;
122 interrupts = <11>;
842839a3
PM		 123 clocks = <&smbclk>;
124 clock-names = "apb_pclk";
8deed178
PM		 125 };
126
127 mmci@05000 {
128 compatible = "arm,pl180", "arm,primecell";
129 reg = <0x05000 0x1000>;
130 interrupts = <9 10>;
974cc7b9
PM		 131 cd-gpios = <&v2m_mmc_gpios 0 0>;
132 wp-gpios = <&v2m_mmc_gpios 1 0>;
842839a3
PM		 133 max-frequency = <12000000>;
134 vmmc-supply = <&v2m_fixed_3v3>;
135 clocks = <&v2m_clk24mhz>, <&smbclk>;
136 clock-names = "mclk", "apb_pclk";
8deed178
PM		 137 };
138
139 kmi@06000 {
140 compatible = "arm,pl050", "arm,primecell";
141 reg = <0x06000 0x1000>;
142 interrupts = <12>;
842839a3
PM		 143 clocks = <&v2m_clk24mhz>, <&smbclk>;
144 clock-names = "KMIREFCLK", "apb_pclk";
8deed178
PM		 145 };
146
147 kmi@07000 {
148 compatible = "arm,pl050", "arm,primecell";
149 reg = <0x07000 0x1000>;
150 interrupts = <13>;
842839a3
PM		 151 clocks = <&v2m_clk24mhz>, <&smbclk>;
152 clock-names = "KMIREFCLK", "apb_pclk";
8deed178
PM		 153 };
154
155 v2m_serial0: uart@09000 {
156 compatible = "arm,pl011", "arm,primecell";
157 reg = <0x09000 0x1000>;
158 interrupts = <5>;
842839a3
PM		 159 clocks = <&v2m_oscclk2>, <&smbclk>;
160 clock-names = "uartclk", "apb_pclk";
8deed178
PM		 161 };
162
163 v2m_serial1: uart@0a000 {
164 compatible = "arm,pl011", "arm,primecell";
165 reg = <0x0a000 0x1000>;
166 interrupts = <6>;
842839a3
PM		 167 clocks = <&v2m_oscclk2>, <&smbclk>;
168 clock-names = "uartclk", "apb_pclk";
8deed178
PM		 169 };
170
171 v2m_serial2: uart@0b000 {
172 compatible = "arm,pl011", "arm,primecell";
173 reg = <0x0b000 0x1000>;
174 interrupts = <7>;
842839a3
PM		 175 clocks = <&v2m_oscclk2>, <&smbclk>;
176 clock-names = "uartclk", "apb_pclk";
8deed178
PM		 177 };
178
179 v2m_serial3: uart@0c000 {
180 compatible = "arm,pl011", "arm,primecell";
181 reg = <0x0c000 0x1000>;
182 interrupts = <8>;
842839a3
PM		 183 clocks = <&v2m_oscclk2>, <&smbclk>;
184 clock-names = "uartclk", "apb_pclk";
8deed178
PM		 185 };
186
187 wdt@0f000 {
188 compatible = "arm,sp805", "arm,primecell";
189 reg = <0x0f000 0x1000>;
190 interrupts = <0>;
842839a3
PM		 191 clocks = <&v2m_refclk32khz>, <&smbclk>;
192 clock-names = "wdogclk", "apb_pclk";
8deed178
PM		 193 };
194
195 v2m_timer01: timer@11000 {
196 compatible = "arm,sp804", "arm,primecell";
197 reg = <0x11000 0x1000>;
198 interrupts = <2>;
842839a3
PM		 199 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
200 clock-names = "timclken1", "timclken2", "apb_pclk";
8deed178
PM		 201 };
202
203 v2m_timer23: timer@12000 {
204 compatible = "arm,sp804", "arm,primecell";
205 reg = <0x12000 0x1000>;
b7541a95 206 interrupts = <3>;
842839a3
PM		 207 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
208 clock-names = "timclken1", "timclken2", "apb_pclk";
8deed178
PM		 209 };
210
211 /* DVI I2C bus */
212 v2m_i2c_dvi: i2c@16000 {
213 compatible = "arm,versatile-i2c";
214 reg = <0x16000 0x1000>;
215
216 #address-cells = <1>;
217 #size-cells = <0>;
218
219 dvi-transmitter@39 {
220 compatible = "sil,sii9022-tpi", "sil,sii9022";
221 reg = <0x39>;
222 };
223
224 dvi-transmitter@60 {
225 compatible = "sil,sii9022-cpi", "sil,sii9022";
226 reg = <0x60>;
227 };
228 };
229
230 rtc@17000 {
231 compatible = "arm,pl031", "arm,primecell";
232 reg = <0x17000 0x1000>;
233 interrupts = <4>;
842839a3
PM		 234 clocks = <&smbclk>;
235 clock-names = "apb_pclk";
8deed178
PM		 236 };
237
238 compact-flash@1a000 {
239 compatible = "arm,vexpress-cf", "ata-generic";
240 reg = <0x1a000 0x100
241 0x1a100 0xf00>;
242 reg-shift = <2>;
243 };
244
245 clcd@1f000 {
246 compatible = "arm,pl111", "arm,primecell";
247 reg = <0x1f000 0x1000>;
478a4f81 248 interrupt-names = "combined";
8deed178 249 interrupts = <14>;
842839a3
PM		 250 clocks = <&v2m_oscclk1>, <&smbclk>;
251 clock-names = "clcdclk", "apb_pclk";
478a4f81
PM		 252 memory-region = <&v2m_video_ram>;
253 max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
254
255 port {
256 v2m_clcd_pads: endpoint {
257 remote-endpoint = <&v2m_clcd_panel>;
258 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
259 };
260 };
261
262 panel {
263 compatible = "panel-dpi";
264
265 port {
266 v2m_clcd_panel: endpoint {
267 remote-endpoint = <&v2m_clcd_pads>;
268 };
269 };
270
271 panel-timing {
272 clock-frequency = <25175000>;
273 hactive = <640>;
274 hback-porch = <40>;
275 hfront-porch = <24>;
276 hsync-len = <96>;
277 vactive = <480>;
278 vback-porch = <32>;
279 vfront-porch = <11>;
280 vsync-len = <2>;
281 };
282 };
8deed178
PM		 283 };
284 };
b2a54ff0
PM		 285
286 v2m_fixed_3v3: fixedregulator@0 {
287 compatible = "regulator-fixed";
288 regulator-name = "3V3";
289 regulator-min-microvolt = <3300000>;
290 regulator-max-microvolt = <3300000>;
291 regulator-always-on;
292 };
842839a3
PM		 293
294 v2m_clk24mhz: clk24mhz {
295 compatible = "fixed-clock";
296 #clock-cells = <0>;
297 clock-frequency = <24000000>;
298 clock-output-names = "v2m:clk24mhz";
299 };
300
301 v2m_refclk1mhz: refclk1mhz {
302 compatible = "fixed-clock";
303 #clock-cells = <0>;
304 clock-frequency = <1000000>;
305 clock-output-names = "v2m:refclk1mhz";
306 };
307
308 v2m_refclk32khz: refclk32khz {
309 compatible = "fixed-clock";
310 #clock-cells = <0>;
311 clock-frequency = <32768>;
312 clock-output-names = "v2m:refclk32khz";
313 };
314
974cc7b9
PM		 315 leds {
316 compatible = "gpio-leds";
317
318 user@1 {
319 label = "v2m:green:user1";
320 gpios = <&v2m_led_gpios 0 0>;
321 linux,default-trigger = "heartbeat";
322 };
323
324 user@2 {
325 label = "v2m:green:user2";
326 gpios = <&v2m_led_gpios 1 0>;
327 linux,default-trigger = "mmc0";
328 };
329
330 user@3 {
331 label = "v2m:green:user3";
332 gpios = <&v2m_led_gpios 2 0>;
333 linux,default-trigger = "cpu0";
334 };
335
336 user@4 {
337 label = "v2m:green:user4";
338 gpios = <&v2m_led_gpios 3 0>;
339 linux,default-trigger = "cpu1";
340 };
341
342 user@5 {
343 label = "v2m:green:user5";
344 gpios = <&v2m_led_gpios 4 0>;
345 linux,default-trigger = "cpu2";
346 };
347
348 user@6 {
349 label = "v2m:green:user6";
350 gpios = <&v2m_led_gpios 5 0>;
351 linux,default-trigger = "cpu3";
352 };
353
354 user@7 {
355 label = "v2m:green:user7";
356 gpios = <&v2m_led_gpios 6 0>;
357 linux,default-trigger = "cpu4";
358 };
359
360 user@8 {
361 label = "v2m:green:user8";
362 gpios = <&v2m_led_gpios 7 0>;
363 linux,default-trigger = "cpu5";
364 };
365 };
366
842839a3
PM		 367 mcc {
368 compatible = "arm,vexpress,config-bus";
369 arm,vexpress,config-bridge = <&v2m_sysreg>;
370
371 osc@0 {
372 /* MCC static memory clock */
373 compatible = "arm,vexpress-osc";
374 arm,vexpress-sysreg,func = <1 0>;
375 freq-range = <25000000 60000000>;
376 #clock-cells = <0>;
377 clock-output-names = "v2m:oscclk0";
378 };
379
380 v2m_oscclk1: osc@1 {
381 /* CLCD clock */
382 compatible = "arm,vexpress-osc";
383 arm,vexpress-sysreg,func = <1 1>;
478a4f81 384 freq-range = <23750000 65000000>;
842839a3
PM		 385 #clock-cells = <0>;
386 clock-output-names = "v2m:oscclk1";
387 };
388
389 v2m_oscclk2: osc@2 {
390 /* IO FPGA peripheral clock */
391 compatible = "arm,vexpress-osc";
392 arm,vexpress-sysreg,func = <1 2>;
393 freq-range = <24000000 24000000>;
394 #clock-cells = <0>;
395 clock-output-names = "v2m:oscclk2";
396 };
397
398 volt@0 {
399 /* Logic level voltage */
400 compatible = "arm,vexpress-volt";
401 arm,vexpress-sysreg,func = <2 0>;
402 regulator-name = "VIO";
403 regulator-always-on;
404 label = "VIO";
405 };
406
407 temp@0 {
408 /* MCC internal operating temperature */
409 compatible = "arm,vexpress-temp";
410 arm,vexpress-sysreg,func = <4 0>;
411 label = "MCC";
412 };
413
414 reset@0 {
415 compatible = "arm,vexpress-reset";
416 arm,vexpress-sysreg,func = <5 0>;
417 };
418
419 muxfpga@0 {
420 compatible = "arm,vexpress-muxfpga";
421 arm,vexpress-sysreg,func = <7 0>;
422 };
423
424 shutdown@0 {
425 compatible = "arm,vexpress-shutdown";
426 arm,vexpress-sysreg,func = <8 0>;
427 };
428
429 reboot@0 {
430 compatible = "arm,vexpress-reboot";
431 arm,vexpress-sysreg,func = <9 0>;
432 };
433
434 dvimode@0 {
435 compatible = "arm,vexpress-dvimode";
436 arm,vexpress-sysreg,func = <11 0>;
437 };
438 };
8deed178 439 };
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