[deliverable/linux.git] / arch / arm / boot / dts / vexpress-v2m.dtsi

/*
 * ARM Ltd. Versatile Express
 *
 * Motherboard Express uATX
 * V2M-P1
 *
 * HBI-0190D
 *
 * Original memory map ("Legacy memory map" in the board's
 * Technical Reference Manual)
 *
 * WARNING! The hardware described in this file is independent from the
 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
 * correspondence between the two configurations.
 *
 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
 * CHANGES TO vexpress-v2m-rs1.dtsi!
 */

	motherboard {
		model = "V2M-P1";
		arm,hbi = <0x190>;
		arm,vexpress,site = <0>;
		compatible = "arm,vexpress,v2m-p1", "simple-bus";
		#address-cells = <2>; /* SMB chipselect number and offset */
		#size-cells = <1>;
		#interrupt-cells = <1>;
		ranges;

		flash@0,00000000 {
			compatible = "arm,vexpress-flash", "cfi-flash";
			reg = <0 0x00000000 0x04000000>,
			      <1 0x00000000 0x04000000>;
			bank-width = <4>;
		};

		psram@2,00000000 {
			compatible = "arm,vexpress-psram", "mtd-ram";
			reg = <2 0x00000000 0x02000000>;
			bank-width = <4>;
		};

		vram@3,00000000 {
			compatible = "arm,vexpress-vram";
			reg = <3 0x00000000 0x00800000>;
		};

		ethernet@3,02000000 {
			compatible = "smsc,lan9118", "smsc,lan9115";
			reg = <3 0x02000000 0x10000>;
			interrupts = <15>;
			phy-mode = "mii";
			reg-io-width = <4>;
			smsc,irq-active-high;
			smsc,irq-push-pull;
			vdd33a-supply = <&v2m_fixed_3v3>;
			vddvario-supply = <&v2m_fixed_3v3>;
		};

		usb@3,03000000 {
			compatible = "nxp,usb-isp1761";
			reg = <3 0x03000000 0x20000>;
			interrupts = <16>;
			port1-otg;
		};

		iofpga@7,00000000 {
			compatible = "arm,amba-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 7 0 0x20000>;

			v2m_sysreg: sysreg@00000 {
				compatible = "arm,vexpress-sysreg";
				reg = <0x00000 0x1000>;

				v2m_led_gpios: sys_led@08 {
					compatible = "arm,vexpress-sysreg,sys_led";
					gpio-controller;
					#gpio-cells = <2>;
				};

				v2m_mmc_gpios: sys_mci@48 {
					compatible = "arm,vexpress-sysreg,sys_mci";
					gpio-controller;
					#gpio-cells = <2>;
				};

				v2m_flash_gpios: sys_flash@4c {
					compatible = "arm,vexpress-sysreg,sys_flash";
					gpio-controller;
					#gpio-cells = <2>;
				};
			};

			v2m_sysctl: sysctl@01000 {
				compatible = "arm,sp810", "arm,primecell";
				reg = <0x01000 0x1000>;
				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
				clock-names = "refclk", "timclk", "apb_pclk";
				#clock-cells = <1>;
				clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
			};

			/* PCI-E I2C bus */
			v2m_i2c_pcie: i2c@02000 {
				compatible = "arm,versatile-i2c";
				reg = <0x02000 0x1000>;

				#address-cells = <1>;
				#size-cells = <0>;

				pcie-switch@60 {
					compatible = "idt,89hpes32h8";
					reg = <0x60>;
				};
			};

			aaci@04000 {
				compatible = "arm,pl041", "arm,primecell";
				reg = <0x04000 0x1000>;
				interrupts = <11>;
				clocks = <&smbclk>;
				clock-names = "apb_pclk";
			};

			mmci@05000 {
				compatible = "arm,pl180", "arm,primecell";
				reg = <0x05000 0x1000>;
				interrupts = <9 10>;
				cd-gpios = <&v2m_mmc_gpios 0 0>;
				wp-gpios = <&v2m_mmc_gpios 1 0>;
				max-frequency = <12000000>;
				vmmc-supply = <&v2m_fixed_3v3>;
				clocks = <&v2m_clk24mhz>, <&smbclk>;
				clock-names = "mclk", "apb_pclk";
			};

			kmi@06000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x06000 0x1000>;
				interrupts = <12>;
				clocks = <&v2m_clk24mhz>, <&smbclk>;
				clock-names = "KMIREFCLK", "apb_pclk";
			};

			kmi@07000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x07000 0x1000>;
				interrupts = <13>;
				clocks = <&v2m_clk24mhz>, <&smbclk>;
				clock-names = "KMIREFCLK", "apb_pclk";
			};

			v2m_serial0: uart@09000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x09000 0x1000>;
				interrupts = <5>;
				clocks = <&v2m_oscclk2>, <&smbclk>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial1: uart@0a000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0a000 0x1000>;
				interrupts = <6>;
				clocks = <&v2m_oscclk2>, <&smbclk>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial2: uart@0b000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0b000 0x1000>;
				interrupts = <7>;
				clocks = <&v2m_oscclk2>, <&smbclk>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial3: uart@0c000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0c000 0x1000>;
				interrupts = <8>;
				clocks = <&v2m_oscclk2>, <&smbclk>;
				clock-names = "uartclk", "apb_pclk";
			};

			wdt@0f000 {
				compatible = "arm,sp805", "arm,primecell";
				reg = <0x0f000 0x1000>;
				interrupts = <0>;
				clocks = <&v2m_refclk32khz>, <&smbclk>;
				clock-names = "wdogclk", "apb_pclk";
			};

			v2m_timer01: timer@11000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x11000 0x1000>;
				interrupts = <2>;
				clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
				clock-names = "timclken1", "timclken2", "apb_pclk";
			};

			v2m_timer23: timer@12000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x12000 0x1000>;
				interrupts = <3>;
				clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
				clock-names = "timclken1", "timclken2", "apb_pclk";
			};

			/* DVI I2C bus */
			v2m_i2c_dvi: i2c@16000 {
				compatible = "arm,versatile-i2c";
				reg = <0x16000 0x1000>;

				#address-cells = <1>;
				#size-cells = <0>;

				dvi-transmitter@39 {
					compatible = "sil,sii9022-tpi", "sil,sii9022";
					reg = <0x39>;
				};

				dvi-transmitter@60 {
					compatible = "sil,sii9022-cpi", "sil,sii9022";
					reg = <0x60>;
				};
			};

			rtc@17000 {
				compatible = "arm,pl031", "arm,primecell";
				reg = <0x17000 0x1000>;
				interrupts = <4>;
				clocks = <&smbclk>;
				clock-names = "apb_pclk";
			};

			compact-flash@1a000 {
				compatible = "arm,vexpress-cf", "ata-generic";
				reg = <0x1a000 0x100
				       0x1a100 0xf00>;
				reg-shift = <2>;
			};

			clcd@1f000 {
				compatible = "arm,pl111", "arm,primecell";
				reg = <0x1f000 0x1000>;
				interrupts = <14>;
				clocks = <&v2m_oscclk1>, <&smbclk>;
				clock-names = "clcdclk", "apb_pclk";
			};
		};

		v2m_fixed_3v3: fixedregulator@0 {
			compatible = "regulator-fixed";
			regulator-name = "3V3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		v2m_clk24mhz: clk24mhz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
			clock-output-names = "v2m:clk24mhz";
		};

		v2m_refclk1mhz: refclk1mhz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1000000>;
			clock-output-names = "v2m:refclk1mhz";
		};

		v2m_refclk32khz: refclk32khz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
			clock-output-names = "v2m:refclk32khz";
		};

		leds {
			compatible = "gpio-leds";

			user@1 {
				label = "v2m:green:user1";
				gpios = <&v2m_led_gpios 0 0>;
				linux,default-trigger = "heartbeat";
			};

			user@2 {
				label = "v2m:green:user2";
				gpios = <&v2m_led_gpios 1 0>;
				linux,default-trigger = "mmc0";
			};

			user@3 {
				label = "v2m:green:user3";
				gpios = <&v2m_led_gpios 2 0>;
				linux,default-trigger = "cpu0";
			};

			user@4 {
				label = "v2m:green:user4";
				gpios = <&v2m_led_gpios 3 0>;
				linux,default-trigger = "cpu1";
			};

			user@5 {
				label = "v2m:green:user5";
				gpios = <&v2m_led_gpios 4 0>;
				linux,default-trigger = "cpu2";
			};

			user@6 {
				label = "v2m:green:user6";
				gpios = <&v2m_led_gpios 5 0>;
				linux,default-trigger = "cpu3";
			};

			user@7 {
				label = "v2m:green:user7";
				gpios = <&v2m_led_gpios 6 0>;
				linux,default-trigger = "cpu4";
			};

			user@8 {
				label = "v2m:green:user8";
				gpios = <&v2m_led_gpios 7 0>;
				linux,default-trigger = "cpu5";
			};
		};

		mcc {
			compatible = "arm,vexpress,config-bus";
			arm,vexpress,config-bridge = <&v2m_sysreg>;

			osc@0 {
				/* MCC static memory clock */
				compatible = "arm,vexpress-osc";
				arm,vexpress-sysreg,func = <1 0>;
				freq-range = <25000000 60000000>;
				#clock-cells = <0>;
				clock-output-names = "v2m:oscclk0";
			};

			v2m_oscclk1: osc@1 {
				/* CLCD clock */
				compatible = "arm,vexpress-osc";
				arm,vexpress-sysreg,func = <1 1>;
				freq-range = <23750000 63500000>;
				#clock-cells = <0>;
				clock-output-names = "v2m:oscclk1";
			};

			v2m_oscclk2: osc@2 {
				/* IO FPGA peripheral clock */
				compatible = "arm,vexpress-osc";
				arm,vexpress-sysreg,func = <1 2>;
				freq-range = <24000000 24000000>;
				#clock-cells = <0>;
				clock-output-names = "v2m:oscclk2";
			};

			volt@0 {
				/* Logic level voltage */
				compatible = "arm,vexpress-volt";
				arm,vexpress-sysreg,func = <2 0>;
				regulator-name = "VIO";
				regulator-always-on;
				label = "VIO";
			};

			temp@0 {
				/* MCC internal operating temperature */
				compatible = "arm,vexpress-temp";
				arm,vexpress-sysreg,func = <4 0>;
				label = "MCC";
			};

			reset@0 {
				compatible = "arm,vexpress-reset";
				arm,vexpress-sysreg,func = <5 0>;
			};

			muxfpga@0 {
				compatible = "arm,vexpress-muxfpga";
				arm,vexpress-sysreg,func = <7 0>;
			};

			shutdown@0 {
				compatible = "arm,vexpress-shutdown";
				arm,vexpress-sysreg,func = <8 0>;
			};

			reboot@0 {
				compatible = "arm,vexpress-reboot";
				arm,vexpress-sysreg,func = <9 0>;
			};

			dvimode@0 {
				compatible = "arm,vexpress-dvimode";
				arm,vexpress-sysreg,func = <11 0>;
			};
		};
	};
Commit	Line	Data
8deed178 PM	1	/*
	2	* ARM Ltd. Versatile Express
	3	*
	4	* Motherboard Express uATX
	5	* V2M-P1
	6	*
	7	* HBI-0190D
	8	*
	9	* Original memory map ("Legacy memory map" in the board's
	10	* Technical Reference Manual)
	11	*
	12	* WARNING! The hardware described in this file is independent from the
	13	* RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
	14	* correspondence between the two configurations.
	15	*
	16	* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
	17	* CHANGES TO vexpress-v2m-rs1.dtsi!
	18	*/
	19
8deed178	20	motherboard {
433683a6 PM	21	model = "V2M-P1";
433683a6 PM	22	arm,hbi = <0x190>;
842839a3	23	arm,vexpress,site = <0>;
433683a6	24	compatible = "arm,vexpress,v2m-p1", "simple-bus";
8deed178 PM	25	#address-cells = <2>; /* SMB chipselect number and offset */
	26	#size-cells = <1>;
	27	#interrupt-cells = <1>;
433683a6	28	ranges;
8deed178 PM	29
	30	flash@0,00000000 {
	31	compatible = "arm,vexpress-flash", "cfi-flash";
	32	reg = <0 0x00000000 0x04000000>,
	33	<1 0x00000000 0x04000000>;
	34	bank-width = <4>;
	35	};
	36
	37	psram@2,00000000 {
	38	compatible = "arm,vexpress-psram", "mtd-ram";
	39	reg = <2 0x00000000 0x02000000>;
	40	bank-width = <4>;
	41	};
	42
	43	vram@3,00000000 {
	44	compatible = "arm,vexpress-vram";
	45	reg = <3 0x00000000 0x00800000>;
	46	};
	47
	48	ethernet@3,02000000 {
	49	compatible = "smsc,lan9118", "smsc,lan9115";
	50	reg = <3 0x02000000 0x10000>;
	51	interrupts = <15>;
	52	phy-mode = "mii";
	53	reg-io-width = <4>;
	54	smsc,irq-active-high;
	55	smsc,irq-push-pull;
b2a54ff0 PM	56	vdd33a-supply = <&v2m_fixed_3v3>;
b2a54ff0 PM	57	vddvario-supply = <&v2m_fixed_3v3>;
8deed178 PM	58	};
	59
	60	usb@3,03000000 {
	61	compatible = "nxp,usb-isp1761";
	62	reg = <3 0x03000000 0x20000>;
	63	interrupts = <16>;
	64	port1-otg;
	65	};
	66
	67	iofpga@7,00000000 {
	68	compatible = "arm,amba-bus", "simple-bus";
	69	#address-cells = <1>;
	70	#size-cells = <1>;
	71	ranges = <0 7 0 0x20000>;
	72
842839a3	73	v2m_sysreg: sysreg@00000 {
8deed178 PM	74	compatible = "arm,vexpress-sysreg";
8deed178 PM	75	reg = <0x00000 0x1000>;
974cc7b9 PM	76
	77	v2m_led_gpios: sys_led@08 {
	78	compatible = "arm,vexpress-sysreg,sys_led";
	79	gpio-controller;
	80	#gpio-cells = <2>;
	81	};
	82
	83	v2m_mmc_gpios: sys_mci@48 {
	84	compatible = "arm,vexpress-sysreg,sys_mci";
	85	gpio-controller;
	86	#gpio-cells = <2>;
	87	};
	88
	89	v2m_flash_gpios: sys_flash@4c {
	90	compatible = "arm,vexpress-sysreg,sys_flash";
	91	gpio-controller;
	92	#gpio-cells = <2>;
	93	};
8deed178 PM	94	};
8deed178 PM	95
842839a3	96	v2m_sysctl: sysctl@01000 {
8deed178 PM	97	compatible = "arm,sp810", "arm,primecell";
8deed178 PM	98	reg = <0x01000 0x1000>;
842839a3 PM	99	clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
	100	clock-names = "refclk", "timclk", "apb_pclk";
	101	#clock-cells = <1>;
	102	clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
8deed178 PM	103	};
	104
	105	/* PCI-E I2C bus */
	106	v2m_i2c_pcie: i2c@02000 {
	107	compatible = "arm,versatile-i2c";
	108	reg = <0x02000 0x1000>;
	109
	110	#address-cells = <1>;
	111	#size-cells = <0>;
	112
	113	pcie-switch@60 {
	114	compatible = "idt,89hpes32h8";
	115	reg = <0x60>;
	116	};
	117	};
	118
	119	aaci@04000 {
	120	compatible = "arm,pl041", "arm,primecell";
	121	reg = <0x04000 0x1000>;
	122	interrupts = <11>;
842839a3 PM	123	clocks = <&smbclk>;
842839a3 PM	124	clock-names = "apb_pclk";
8deed178 PM	125	};
	126
	127	mmci@05000 {
	128	compatible = "arm,pl180", "arm,primecell";
	129	reg = <0x05000 0x1000>;
	130	interrupts = <9 10>;
974cc7b9 PM	131	cd-gpios = <&v2m_mmc_gpios 0 0>;
974cc7b9 PM	132	wp-gpios = <&v2m_mmc_gpios 1 0>;
842839a3 PM	133	max-frequency = <12000000>;
	134	vmmc-supply = <&v2m_fixed_3v3>;
	135	clocks = <&v2m_clk24mhz>, <&smbclk>;
	136	clock-names = "mclk", "apb_pclk";
8deed178 PM	137	};
	138
	139	kmi@06000 {
	140	compatible = "arm,pl050", "arm,primecell";
	141	reg = <0x06000 0x1000>;
	142	interrupts = <12>;
842839a3 PM	143	clocks = <&v2m_clk24mhz>, <&smbclk>;
842839a3 PM	144	clock-names = "KMIREFCLK", "apb_pclk";
8deed178 PM	145	};
	146
	147	kmi@07000 {
	148	compatible = "arm,pl050", "arm,primecell";
	149	reg = <0x07000 0x1000>;
	150	interrupts = <13>;
842839a3 PM	151	clocks = <&v2m_clk24mhz>, <&smbclk>;
842839a3 PM	152	clock-names = "KMIREFCLK", "apb_pclk";
8deed178 PM	153	};
	154
	155	v2m_serial0: uart@09000 {
	156	compatible = "arm,pl011", "arm,primecell";
	157	reg = <0x09000 0x1000>;
	158	interrupts = <5>;
842839a3 PM	159	clocks = <&v2m_oscclk2>, <&smbclk>;
842839a3 PM	160	clock-names = "uartclk", "apb_pclk";
8deed178 PM	161	};
	162
	163	v2m_serial1: uart@0a000 {
	164	compatible = "arm,pl011", "arm,primecell";
	165	reg = <0x0a000 0x1000>;
	166	interrupts = <6>;
842839a3 PM	167	clocks = <&v2m_oscclk2>, <&smbclk>;
842839a3 PM	168	clock-names = "uartclk", "apb_pclk";
8deed178 PM	169	};
	170
	171	v2m_serial2: uart@0b000 {
	172	compatible = "arm,pl011", "arm,primecell";
	173	reg = <0x0b000 0x1000>;
	174	interrupts = <7>;
842839a3 PM	175	clocks = <&v2m_oscclk2>, <&smbclk>;
842839a3 PM	176	clock-names = "uartclk", "apb_pclk";
8deed178 PM	177	};
	178
	179	v2m_serial3: uart@0c000 {
	180	compatible = "arm,pl011", "arm,primecell";
	181	reg = <0x0c000 0x1000>;
	182	interrupts = <8>;
842839a3 PM	183	clocks = <&v2m_oscclk2>, <&smbclk>;
842839a3 PM	184	clock-names = "uartclk", "apb_pclk";
8deed178 PM	185	};
	186
	187	wdt@0f000 {
	188	compatible = "arm,sp805", "arm,primecell";
	189	reg = <0x0f000 0x1000>;
	190	interrupts = <0>;
842839a3 PM	191	clocks = <&v2m_refclk32khz>, <&smbclk>;
842839a3 PM	192	clock-names = "wdogclk", "apb_pclk";
8deed178 PM	193	};
	194
	195	v2m_timer01: timer@11000 {
	196	compatible = "arm,sp804", "arm,primecell";
	197	reg = <0x11000 0x1000>;
	198	interrupts = <2>;
842839a3 PM	199	clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
842839a3 PM	200	clock-names = "timclken1", "timclken2", "apb_pclk";
8deed178 PM	201	};
	202
	203	v2m_timer23: timer@12000 {
	204	compatible = "arm,sp804", "arm,primecell";
	205	reg = <0x12000 0x1000>;
b7541a95	206	interrupts = <3>;
842839a3 PM	207	clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
842839a3 PM	208	clock-names = "timclken1", "timclken2", "apb_pclk";
8deed178 PM	209	};
	210
	211	/* DVI I2C bus */
	212	v2m_i2c_dvi: i2c@16000 {
	213	compatible = "arm,versatile-i2c";
	214	reg = <0x16000 0x1000>;
	215
	216	#address-cells = <1>;
	217	#size-cells = <0>;
	218
	219	dvi-transmitter@39 {
	220	compatible = "sil,sii9022-tpi", "sil,sii9022";
	221	reg = <0x39>;
	222	};
	223
	224	dvi-transmitter@60 {
	225	compatible = "sil,sii9022-cpi", "sil,sii9022";
	226	reg = <0x60>;
	227	};
	228	};
	229
	230	rtc@17000 {
	231	compatible = "arm,pl031", "arm,primecell";
	232	reg = <0x17000 0x1000>;
	233	interrupts = <4>;
842839a3 PM	234	clocks = <&smbclk>;
842839a3 PM	235	clock-names = "apb_pclk";
8deed178 PM	236	};
	237
	238	compact-flash@1a000 {
	239	compatible = "arm,vexpress-cf", "ata-generic";
	240	reg = <0x1a000 0x100
	241	0x1a100 0xf00>;
	242	reg-shift = <2>;
	243	};
	244
	245	clcd@1f000 {
	246	compatible = "arm,pl111", "arm,primecell";
	247	reg = <0x1f000 0x1000>;
	248	interrupts = <14>;
842839a3 PM	249	clocks = <&v2m_oscclk1>, <&smbclk>;
842839a3 PM	250	clock-names = "clcdclk", "apb_pclk";
8deed178 PM	251	};
8deed178 PM	252	};
b2a54ff0 PM	253
	254	v2m_fixed_3v3: fixedregulator@0 {
	255	compatible = "regulator-fixed";
	256	regulator-name = "3V3";
	257	regulator-min-microvolt = <3300000>;
	258	regulator-max-microvolt = <3300000>;
	259	regulator-always-on;
	260	};
842839a3 PM	261
	262	v2m_clk24mhz: clk24mhz {
	263	compatible = "fixed-clock";
	264	#clock-cells = <0>;
	265	clock-frequency = <24000000>;
	266	clock-output-names = "v2m:clk24mhz";
	267	};
	268
	269	v2m_refclk1mhz: refclk1mhz {
	270	compatible = "fixed-clock";
	271	#clock-cells = <0>;
	272	clock-frequency = <1000000>;
	273	clock-output-names = "v2m:refclk1mhz";
	274	};
	275
	276	v2m_refclk32khz: refclk32khz {
	277	compatible = "fixed-clock";
	278	#clock-cells = <0>;
	279	clock-frequency = <32768>;
	280	clock-output-names = "v2m:refclk32khz";
	281	};
	282
974cc7b9 PM	283	leds {
	284	compatible = "gpio-leds";
	285
	286	user@1 {
	287	label = "v2m:green:user1";
	288	gpios = <&v2m_led_gpios 0 0>;
	289	linux,default-trigger = "heartbeat";
	290	};
	291
	292	user@2 {
	293	label = "v2m:green:user2";
	294	gpios = <&v2m_led_gpios 1 0>;
	295	linux,default-trigger = "mmc0";
	296	};
	297
	298	user@3 {
	299	label = "v2m:green:user3";
	300	gpios = <&v2m_led_gpios 2 0>;
	301	linux,default-trigger = "cpu0";
	302	};
	303
	304	user@4 {
	305	label = "v2m:green:user4";
	306	gpios = <&v2m_led_gpios 3 0>;
	307	linux,default-trigger = "cpu1";
	308	};
	309
	310	user@5 {
	311	label = "v2m:green:user5";
	312	gpios = <&v2m_led_gpios 4 0>;
	313	linux,default-trigger = "cpu2";
	314	};
	315
	316	user@6 {
	317	label = "v2m:green:user6";
	318	gpios = <&v2m_led_gpios 5 0>;
	319	linux,default-trigger = "cpu3";
	320	};
	321
	322	user@7 {
	323	label = "v2m:green:user7";
	324	gpios = <&v2m_led_gpios 6 0>;
	325	linux,default-trigger = "cpu4";
	326	};
	327
	328	user@8 {
	329	label = "v2m:green:user8";
	330	gpios = <&v2m_led_gpios 7 0>;
	331	linux,default-trigger = "cpu5";
	332	};
	333	};
	334
842839a3 PM	335	mcc {
	336	compatible = "arm,vexpress,config-bus";
	337	arm,vexpress,config-bridge = <&v2m_sysreg>;
	338
	339	osc@0 {
	340	/* MCC static memory clock */
	341	compatible = "arm,vexpress-osc";
	342	arm,vexpress-sysreg,func = <1 0>;
	343	freq-range = <25000000 60000000>;
	344	#clock-cells = <0>;
	345	clock-output-names = "v2m:oscclk0";
	346	};
	347
	348	v2m_oscclk1: osc@1 {
	349	/* CLCD clock */
	350	compatible = "arm,vexpress-osc";
	351	arm,vexpress-sysreg,func = <1 1>;
	352	freq-range = <23750000 63500000>;
	353	#clock-cells = <0>;
	354	clock-output-names = "v2m:oscclk1";
	355	};
	356
	357	v2m_oscclk2: osc@2 {
	358	/* IO FPGA peripheral clock */
	359	compatible = "arm,vexpress-osc";
	360	arm,vexpress-sysreg,func = <1 2>;
	361	freq-range = <24000000 24000000>;
	362	#clock-cells = <0>;
	363	clock-output-names = "v2m:oscclk2";
	364	};
	365
	366	volt@0 {
	367	/* Logic level voltage */
	368	compatible = "arm,vexpress-volt";
	369	arm,vexpress-sysreg,func = <2 0>;
	370	regulator-name = "VIO";
	371	regulator-always-on;
	372	label = "VIO";
	373	};
	374
	375	temp@0 {
	376	/* MCC internal operating temperature */
	377	compatible = "arm,vexpress-temp";
	378	arm,vexpress-sysreg,func = <4 0>;
	379	label = "MCC";
	380	};
	381
	382	reset@0 {
	383	compatible = "arm,vexpress-reset";
	384	arm,vexpress-sysreg,func = <5 0>;
	385	};
	386
	387	muxfpga@0 {
	388	compatible = "arm,vexpress-muxfpga";
	389	arm,vexpress-sysreg,func = <7 0>;
	390	};
	391
	392	shutdown@0 {
	393	compatible = "arm,vexpress-shutdown";
	394	arm,vexpress-sysreg,func = <8 0>;
	395	};
	396
	397	reboot@0 {
	398	compatible = "arm,vexpress-reboot";
399	arm,vexpress-sysreg,func = <9 0>;
400	};
401
402	dvimode@0 {
403	compatible = "arm,vexpress-dvimode";
404	arm,vexpress-sysreg,func = <11 0>;
405	};
406	};
8deed178	407	};