Commit | Line | Data |
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375faa93 PM |
1 | /* |
2 | * ARM Ltd. Versatile Express | |
3 | * | |
4 | * CoreTile Express A15x2 A7x3 | |
5 | * Cortex-A15_A7 MPCore (V2P-CA15_A7) | |
6 | * | |
7 | * HBI-0249A | |
8 | */ | |
9 | ||
10 | /dts-v1/; | |
11 | ||
12 | / { | |
13 | model = "V2P-CA15_CA7"; | |
14 | arm,hbi = <0x249>; | |
842839a3 | 15 | arm,vexpress,site = <0xf>; |
375faa93 PM |
16 | compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; |
17 | interrupt-parent = <&gic>; | |
18 | #address-cells = <2>; | |
19 | #size-cells = <2>; | |
20 | ||
21 | chosen { }; | |
22 | ||
23 | aliases { | |
24 | serial0 = &v2m_serial0; | |
25 | serial1 = &v2m_serial1; | |
26 | serial2 = &v2m_serial2; | |
27 | serial3 = &v2m_serial3; | |
28 | i2c0 = &v2m_i2c_dvi; | |
29 | i2c1 = &v2m_i2c_pcie; | |
30 | }; | |
31 | ||
32 | cpus { | |
33 | #address-cells = <1>; | |
34 | #size-cells = <0>; | |
35 | ||
36 | cpu0: cpu@0 { | |
37 | device_type = "cpu"; | |
38 | compatible = "arm,cortex-a15"; | |
39 | reg = <0>; | |
a2bdc32a | 40 | cci-control-port = <&cci_control1>; |
375faa93 PM |
41 | }; |
42 | ||
43 | cpu1: cpu@1 { | |
44 | device_type = "cpu"; | |
45 | compatible = "arm,cortex-a15"; | |
46 | reg = <1>; | |
a2bdc32a | 47 | cci-control-port = <&cci_control1>; |
375faa93 PM |
48 | }; |
49 | ||
375faa93 PM |
50 | cpu2: cpu@2 { |
51 | device_type = "cpu"; | |
52 | compatible = "arm,cortex-a7"; | |
53 | reg = <0x100>; | |
a2bdc32a | 54 | cci-control-port = <&cci_control2>; |
375faa93 PM |
55 | }; |
56 | ||
57 | cpu3: cpu@3 { | |
58 | device_type = "cpu"; | |
59 | compatible = "arm,cortex-a7"; | |
60 | reg = <0x101>; | |
a2bdc32a | 61 | cci-control-port = <&cci_control2>; |
375faa93 PM |
62 | }; |
63 | ||
64 | cpu4: cpu@4 { | |
65 | device_type = "cpu"; | |
66 | compatible = "arm,cortex-a7"; | |
67 | reg = <0x102>; | |
a2bdc32a | 68 | cci-control-port = <&cci_control2>; |
375faa93 | 69 | }; |
375faa93 PM |
70 | }; |
71 | ||
72 | memory@80000000 { | |
73 | device_type = "memory"; | |
74 | reg = <0 0x80000000 0 0x40000000>; | |
75 | }; | |
76 | ||
77 | wdt@2a490000 { | |
78 | compatible = "arm,sp805", "arm,primecell"; | |
79 | reg = <0 0x2a490000 0 0x1000>; | |
aab7da70 | 80 | interrupts = <0 98 4>; |
842839a3 PM |
81 | clocks = <&oscclk6a>, <&oscclk6a>; |
82 | clock-names = "wdogclk", "apb_pclk"; | |
375faa93 PM |
83 | }; |
84 | ||
85 | hdlcd@2b000000 { | |
86 | compatible = "arm,hdlcd"; | |
87 | reg = <0 0x2b000000 0 0x1000>; | |
88 | interrupts = <0 85 4>; | |
842839a3 PM |
89 | clocks = <&oscclk5>; |
90 | clock-names = "pxlclk"; | |
375faa93 PM |
91 | }; |
92 | ||
93 | memory-controller@2b0a0000 { | |
94 | compatible = "arm,pl341", "arm,primecell"; | |
95 | reg = <0 0x2b0a0000 0 0x1000>; | |
842839a3 PM |
96 | clocks = <&oscclk6a>; |
97 | clock-names = "apb_pclk"; | |
375faa93 PM |
98 | }; |
99 | ||
100 | gic: interrupt-controller@2c001000 { | |
101 | compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; | |
102 | #interrupt-cells = <3>; | |
103 | #address-cells = <0>; | |
104 | interrupt-controller; | |
105 | reg = <0 0x2c001000 0 0x1000>, | |
106 | <0 0x2c002000 0 0x1000>, | |
107 | <0 0x2c004000 0 0x2000>, | |
108 | <0 0x2c006000 0 0x2000>; | |
109 | interrupts = <1 9 0xf04>; | |
110 | }; | |
111 | ||
a2bdc32a JMT |
112 | cci@2c090000 { |
113 | compatible = "arm,cci-400"; | |
114 | #address-cells = <1>; | |
115 | #size-cells = <1>; | |
116 | reg = <0 0x2c090000 0 0x1000>; | |
117 | ranges = <0x0 0x0 0x2c090000 0x10000>; | |
118 | ||
119 | cci_control1: slave-if@4000 { | |
120 | compatible = "arm,cci-400-ctrl-if"; | |
121 | interface-type = "ace"; | |
122 | reg = <0x4000 0x1000>; | |
123 | }; | |
124 | ||
125 | cci_control2: slave-if@5000 { | |
126 | compatible = "arm,cci-400-ctrl-if"; | |
127 | interface-type = "ace"; | |
128 | reg = <0x5000 0x1000>; | |
129 | }; | |
130 | }; | |
131 | ||
375faa93 PM |
132 | memory-controller@7ffd0000 { |
133 | compatible = "arm,pl354", "arm,primecell"; | |
134 | reg = <0 0x7ffd0000 0 0x1000>; | |
135 | interrupts = <0 86 4>, | |
136 | <0 87 4>; | |
842839a3 PM |
137 | clocks = <&oscclk6a>; |
138 | clock-names = "apb_pclk"; | |
375faa93 PM |
139 | }; |
140 | ||
141 | dma@7ff00000 { | |
142 | compatible = "arm,pl330", "arm,primecell"; | |
143 | reg = <0 0x7ff00000 0 0x1000>; | |
144 | interrupts = <0 92 4>, | |
145 | <0 88 4>, | |
146 | <0 89 4>, | |
147 | <0 90 4>, | |
148 | <0 91 4>; | |
842839a3 PM |
149 | clocks = <&oscclk6a>; |
150 | clock-names = "apb_pclk"; | |
375faa93 PM |
151 | }; |
152 | ||
ceca0e1c PM |
153 | scc@7fff0000 { |
154 | compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; | |
155 | reg = <0 0x7fff0000 0 0x1000>; | |
156 | interrupts = <0 95 4>; | |
157 | }; | |
158 | ||
375faa93 PM |
159 | timer { |
160 | compatible = "arm,armv7-timer"; | |
161 | interrupts = <1 13 0xf08>, | |
162 | <1 14 0xf08>, | |
163 | <1 11 0xf08>, | |
164 | <1 10 0xf08>; | |
165 | }; | |
166 | ||
167 | pmu { | |
7e16063b | 168 | compatible = "arm,cortex-a15-pmu"; |
375faa93 PM |
169 | interrupts = <0 68 4>, |
170 | <0 69 4>; | |
171 | }; | |
172 | ||
842839a3 PM |
173 | oscclk6a: oscclk6a { |
174 | /* Reference 24MHz clock */ | |
175 | compatible = "fixed-clock"; | |
176 | #clock-cells = <0>; | |
177 | clock-frequency = <24000000>; | |
178 | clock-output-names = "oscclk6a"; | |
179 | }; | |
180 | ||
181 | dcc { | |
182 | compatible = "arm,vexpress,config-bus"; | |
183 | arm,vexpress,config-bridge = <&v2m_sysreg>; | |
184 | ||
185 | osc@0 { | |
186 | /* A15 PLL 0 reference clock */ | |
187 | compatible = "arm,vexpress-osc"; | |
188 | arm,vexpress-sysreg,func = <1 0>; | |
189 | freq-range = <17000000 50000000>; | |
190 | #clock-cells = <0>; | |
191 | clock-output-names = "oscclk0"; | |
192 | }; | |
193 | ||
194 | osc@1 { | |
195 | /* A15 PLL 1 reference clock */ | |
196 | compatible = "arm,vexpress-osc"; | |
197 | arm,vexpress-sysreg,func = <1 1>; | |
198 | freq-range = <17000000 50000000>; | |
199 | #clock-cells = <0>; | |
200 | clock-output-names = "oscclk1"; | |
201 | }; | |
202 | ||
203 | osc@2 { | |
204 | /* A7 PLL 0 reference clock */ | |
205 | compatible = "arm,vexpress-osc"; | |
206 | arm,vexpress-sysreg,func = <1 2>; | |
207 | freq-range = <17000000 50000000>; | |
208 | #clock-cells = <0>; | |
209 | clock-output-names = "oscclk2"; | |
210 | }; | |
211 | ||
212 | osc@3 { | |
213 | /* A7 PLL 1 reference clock */ | |
214 | compatible = "arm,vexpress-osc"; | |
215 | arm,vexpress-sysreg,func = <1 3>; | |
216 | freq-range = <17000000 50000000>; | |
217 | #clock-cells = <0>; | |
218 | clock-output-names = "oscclk3"; | |
219 | }; | |
220 | ||
221 | osc@4 { | |
222 | /* External AXI master clock */ | |
223 | compatible = "arm,vexpress-osc"; | |
224 | arm,vexpress-sysreg,func = <1 4>; | |
225 | freq-range = <20000000 40000000>; | |
226 | #clock-cells = <0>; | |
227 | clock-output-names = "oscclk4"; | |
228 | }; | |
229 | ||
230 | oscclk5: osc@5 { | |
231 | /* HDLCD PLL reference clock */ | |
232 | compatible = "arm,vexpress-osc"; | |
233 | arm,vexpress-sysreg,func = <1 5>; | |
234 | freq-range = <23750000 165000000>; | |
235 | #clock-cells = <0>; | |
236 | clock-output-names = "oscclk5"; | |
237 | }; | |
238 | ||
239 | smbclk: osc@6 { | |
240 | /* Static memory controller clock */ | |
241 | compatible = "arm,vexpress-osc"; | |
242 | arm,vexpress-sysreg,func = <1 6>; | |
243 | freq-range = <20000000 40000000>; | |
244 | #clock-cells = <0>; | |
245 | clock-output-names = "oscclk6"; | |
246 | }; | |
247 | ||
248 | osc@7 { | |
249 | /* SYS PLL reference clock */ | |
250 | compatible = "arm,vexpress-osc"; | |
251 | arm,vexpress-sysreg,func = <1 7>; | |
252 | freq-range = <17000000 50000000>; | |
253 | #clock-cells = <0>; | |
254 | clock-output-names = "oscclk7"; | |
255 | }; | |
256 | ||
257 | osc@8 { | |
258 | /* DDR2 PLL reference clock */ | |
259 | compatible = "arm,vexpress-osc"; | |
260 | arm,vexpress-sysreg,func = <1 8>; | |
261 | freq-range = <20000000 50000000>; | |
262 | #clock-cells = <0>; | |
263 | clock-output-names = "oscclk8"; | |
264 | }; | |
265 | ||
266 | volt@0 { | |
267 | /* A15 CPU core voltage */ | |
268 | compatible = "arm,vexpress-volt"; | |
269 | arm,vexpress-sysreg,func = <2 0>; | |
270 | regulator-name = "A15 Vcore"; | |
271 | regulator-min-microvolt = <800000>; | |
272 | regulator-max-microvolt = <1050000>; | |
273 | regulator-always-on; | |
274 | label = "A15 Vcore"; | |
275 | }; | |
276 | ||
277 | volt@1 { | |
278 | /* A7 CPU core voltage */ | |
279 | compatible = "arm,vexpress-volt"; | |
280 | arm,vexpress-sysreg,func = <2 1>; | |
281 | regulator-name = "A7 Vcore"; | |
282 | regulator-min-microvolt = <800000>; | |
283 | regulator-max-microvolt = <1050000>; | |
284 | regulator-always-on; | |
285 | label = "A7 Vcore"; | |
286 | }; | |
287 | ||
288 | amp@0 { | |
289 | /* Total current for the two A15 cores */ | |
290 | compatible = "arm,vexpress-amp"; | |
291 | arm,vexpress-sysreg,func = <3 0>; | |
292 | label = "A15 Icore"; | |
293 | }; | |
294 | ||
295 | amp@1 { | |
296 | /* Total current for the three A7 cores */ | |
297 | compatible = "arm,vexpress-amp"; | |
298 | arm,vexpress-sysreg,func = <3 1>; | |
299 | label = "A7 Icore"; | |
300 | }; | |
301 | ||
302 | temp@0 { | |
303 | /* DCC internal temperature */ | |
304 | compatible = "arm,vexpress-temp"; | |
305 | arm,vexpress-sysreg,func = <4 0>; | |
306 | label = "DCC"; | |
307 | }; | |
308 | ||
309 | power@0 { | |
310 | /* Total power for the two A15 cores */ | |
311 | compatible = "arm,vexpress-power"; | |
312 | arm,vexpress-sysreg,func = <12 0>; | |
313 | label = "A15 Pcore"; | |
314 | }; | |
3b9334ac | 315 | |
842839a3 PM |
316 | power@1 { |
317 | /* Total power for the three A7 cores */ | |
318 | compatible = "arm,vexpress-power"; | |
319 | arm,vexpress-sysreg,func = <12 1>; | |
320 | label = "A7 Pcore"; | |
321 | }; | |
322 | ||
323 | energy@0 { | |
324 | /* Total energy for the two A15 cores */ | |
325 | compatible = "arm,vexpress-energy"; | |
3b9334ac | 326 | arm,vexpress-sysreg,func = <13 0>, <13 1>; |
842839a3 PM |
327 | label = "A15 Jcore"; |
328 | }; | |
329 | ||
330 | energy@2 { | |
331 | /* Total energy for the three A7 cores */ | |
332 | compatible = "arm,vexpress-energy"; | |
3b9334ac | 333 | arm,vexpress-sysreg,func = <13 2>, <13 3>; |
842839a3 PM |
334 | label = "A7 Jcore"; |
335 | }; | |
336 | }; | |
337 | ||
433683a6 PM |
338 | smb { |
339 | compatible = "simple-bus"; | |
340 | ||
341 | #address-cells = <2>; | |
342 | #size-cells = <1>; | |
375faa93 PM |
343 | ranges = <0 0 0 0x08000000 0x04000000>, |
344 | <1 0 0 0x14000000 0x04000000>, | |
345 | <2 0 0 0x18000000 0x04000000>, | |
346 | <3 0 0 0x1c000000 0x04000000>, | |
347 | <4 0 0 0x0c000000 0x04000000>, | |
348 | <5 0 0 0x10000000 0x04000000>; | |
349 | ||
433683a6 | 350 | #interrupt-cells = <1>; |
375faa93 PM |
351 | interrupt-map-mask = <0 0 63>; |
352 | interrupt-map = <0 0 0 &gic 0 0 4>, | |
353 | <0 0 1 &gic 0 1 4>, | |
354 | <0 0 2 &gic 0 2 4>, | |
355 | <0 0 3 &gic 0 3 4>, | |
356 | <0 0 4 &gic 0 4 4>, | |
357 | <0 0 5 &gic 0 5 4>, | |
358 | <0 0 6 &gic 0 6 4>, | |
359 | <0 0 7 &gic 0 7 4>, | |
360 | <0 0 8 &gic 0 8 4>, | |
361 | <0 0 9 &gic 0 9 4>, | |
362 | <0 0 10 &gic 0 10 4>, | |
363 | <0 0 11 &gic 0 11 4>, | |
364 | <0 0 12 &gic 0 12 4>, | |
365 | <0 0 13 &gic 0 13 4>, | |
366 | <0 0 14 &gic 0 14 4>, | |
367 | <0 0 15 &gic 0 15 4>, | |
368 | <0 0 16 &gic 0 16 4>, | |
369 | <0 0 17 &gic 0 17 4>, | |
370 | <0 0 18 &gic 0 18 4>, | |
371 | <0 0 19 &gic 0 19 4>, | |
372 | <0 0 20 &gic 0 20 4>, | |
373 | <0 0 21 &gic 0 21 4>, | |
374 | <0 0 22 &gic 0 22 4>, | |
375 | <0 0 23 &gic 0 23 4>, | |
376 | <0 0 24 &gic 0 24 4>, | |
377 | <0 0 25 &gic 0 25 4>, | |
378 | <0 0 26 &gic 0 26 4>, | |
379 | <0 0 27 &gic 0 27 4>, | |
380 | <0 0 28 &gic 0 28 4>, | |
381 | <0 0 29 &gic 0 29 4>, | |
382 | <0 0 30 &gic 0 30 4>, | |
383 | <0 0 31 &gic 0 31 4>, | |
384 | <0 0 32 &gic 0 32 4>, | |
385 | <0 0 33 &gic 0 33 4>, | |
386 | <0 0 34 &gic 0 34 4>, | |
387 | <0 0 35 &gic 0 35 4>, | |
388 | <0 0 36 &gic 0 36 4>, | |
389 | <0 0 37 &gic 0 37 4>, | |
390 | <0 0 38 &gic 0 38 4>, | |
391 | <0 0 39 &gic 0 39 4>, | |
392 | <0 0 40 &gic 0 40 4>, | |
393 | <0 0 41 &gic 0 41 4>, | |
394 | <0 0 42 &gic 0 42 4>; | |
433683a6 PM |
395 | |
396 | /include/ "vexpress-v2m-rs1.dtsi" | |
375faa93 PM |
397 | }; |
398 | }; |