Commit | Line | Data |
---|---|---|
cca070a9 PM |
1 | /* |
2 | * ARM Ltd. Versatile Express | |
3 | * | |
4 | * CoreTile Express A9x4 | |
5 | * Cortex-A9 MPCore (V2P-CA9) | |
6 | * | |
7 | * HBI-0191B | |
8 | */ | |
9 | ||
10 | /dts-v1/; | |
11 | ||
12 | / { | |
13 | model = "V2P-CA9"; | |
14 | arm,hbi = <0x191>; | |
842839a3 | 15 | arm,vexpress,site = <0xf>; |
cca070a9 PM |
16 | compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; |
17 | interrupt-parent = <&gic>; | |
18 | #address-cells = <1>; | |
19 | #size-cells = <1>; | |
20 | ||
21 | chosen { }; | |
22 | ||
23 | aliases { | |
24 | serial0 = &v2m_serial0; | |
25 | serial1 = &v2m_serial1; | |
26 | serial2 = &v2m_serial2; | |
27 | serial3 = &v2m_serial3; | |
28 | i2c0 = &v2m_i2c_dvi; | |
29 | i2c1 = &v2m_i2c_pcie; | |
30 | }; | |
31 | ||
32 | cpus { | |
33 | #address-cells = <1>; | |
34 | #size-cells = <0>; | |
35 | ||
613880a1 | 36 | A9_0: cpu@0 { |
cca070a9 PM |
37 | device_type = "cpu"; |
38 | compatible = "arm,cortex-a9"; | |
39 | reg = <0>; | |
40 | next-level-cache = <&L2>; | |
41 | }; | |
42 | ||
613880a1 | 43 | A9_1: cpu@1 { |
cca070a9 PM |
44 | device_type = "cpu"; |
45 | compatible = "arm,cortex-a9"; | |
46 | reg = <1>; | |
47 | next-level-cache = <&L2>; | |
48 | }; | |
49 | ||
613880a1 | 50 | A9_2: cpu@2 { |
cca070a9 PM |
51 | device_type = "cpu"; |
52 | compatible = "arm,cortex-a9"; | |
53 | reg = <2>; | |
54 | next-level-cache = <&L2>; | |
55 | }; | |
56 | ||
613880a1 | 57 | A9_3: cpu@3 { |
cca070a9 PM |
58 | device_type = "cpu"; |
59 | compatible = "arm,cortex-a9"; | |
60 | reg = <3>; | |
61 | next-level-cache = <&L2>; | |
62 | }; | |
63 | }; | |
64 | ||
65 | memory@60000000 { | |
66 | device_type = "memory"; | |
67 | reg = <0x60000000 0x40000000>; | |
68 | }; | |
69 | ||
70 | clcd@10020000 { | |
71 | compatible = "arm,pl111", "arm,primecell"; | |
72 | reg = <0x10020000 0x1000>; | |
478a4f81 | 73 | interrupt-names = "combined"; |
cca070a9 | 74 | interrupts = <0 44 4>; |
842839a3 PM |
75 | clocks = <&oscclk1>, <&oscclk2>; |
76 | clock-names = "clcdclk", "apb_pclk"; | |
478a4f81 PM |
77 | max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ |
78 | ||
79 | port { | |
80 | clcd_pads: endpoint { | |
81 | remote-endpoint = <&clcd_panel>; | |
82 | arm,pl11x,tft-r0g0b0-pads = <0 8 16>; | |
83 | }; | |
84 | }; | |
85 | ||
86 | panel { | |
87 | compatible = "panel-dpi"; | |
88 | ||
89 | port { | |
90 | clcd_panel: endpoint { | |
91 | remote-endpoint = <&clcd_pads>; | |
92 | }; | |
93 | }; | |
94 | ||
95 | panel-timing { | |
96 | clock-frequency = <63500127>; | |
97 | hactive = <1024>; | |
98 | hback-porch = <152>; | |
99 | hfront-porch = <48>; | |
100 | hsync-len = <104>; | |
101 | vactive = <768>; | |
102 | vback-porch = <23>; | |
103 | vfront-porch = <3>; | |
104 | vsync-len = <4>; | |
105 | }; | |
106 | }; | |
cca070a9 PM |
107 | }; |
108 | ||
109 | memory-controller@100e0000 { | |
110 | compatible = "arm,pl341", "arm,primecell"; | |
111 | reg = <0x100e0000 0x1000>; | |
842839a3 PM |
112 | clocks = <&oscclk2>; |
113 | clock-names = "apb_pclk"; | |
cca070a9 PM |
114 | }; |
115 | ||
116 | memory-controller@100e1000 { | |
117 | compatible = "arm,pl354", "arm,primecell"; | |
118 | reg = <0x100e1000 0x1000>; | |
119 | interrupts = <0 45 4>, | |
120 | <0 46 4>; | |
842839a3 PM |
121 | clocks = <&oscclk2>; |
122 | clock-names = "apb_pclk"; | |
cca070a9 PM |
123 | }; |
124 | ||
125 | timer@100e4000 { | |
126 | compatible = "arm,sp804", "arm,primecell"; | |
127 | reg = <0x100e4000 0x1000>; | |
128 | interrupts = <0 48 4>, | |
129 | <0 49 4>; | |
842839a3 PM |
130 | clocks = <&oscclk2>, <&oscclk2>; |
131 | clock-names = "timclk", "apb_pclk"; | |
34c2e5fe | 132 | status = "disabled"; |
cca070a9 PM |
133 | }; |
134 | ||
135 | watchdog@100e5000 { | |
136 | compatible = "arm,sp805", "arm,primecell"; | |
137 | reg = <0x100e5000 0x1000>; | |
138 | interrupts = <0 51 4>; | |
842839a3 PM |
139 | clocks = <&oscclk2>, <&oscclk2>; |
140 | clock-names = "wdogclk", "apb_pclk"; | |
cca070a9 PM |
141 | }; |
142 | ||
143 | scu@1e000000 { | |
144 | compatible = "arm,cortex-a9-scu"; | |
145 | reg = <0x1e000000 0x58>; | |
146 | }; | |
147 | ||
148 | timer@1e000600 { | |
149 | compatible = "arm,cortex-a9-twd-timer"; | |
150 | reg = <0x1e000600 0x20>; | |
e29b65db PM |
151 | interrupts = <1 13 0xf04>; |
152 | }; | |
153 | ||
154 | watchdog@1e000620 { | |
155 | compatible = "arm,cortex-a9-twd-wdt"; | |
156 | reg = <0x1e000620 0x20>; | |
157 | interrupts = <1 14 0xf04>; | |
cca070a9 PM |
158 | }; |
159 | ||
160 | gic: interrupt-controller@1e001000 { | |
161 | compatible = "arm,cortex-a9-gic"; | |
162 | #interrupt-cells = <3>; | |
163 | #address-cells = <0>; | |
164 | interrupt-controller; | |
165 | reg = <0x1e001000 0x1000>, | |
166 | <0x1e000100 0x100>; | |
167 | }; | |
168 | ||
169 | L2: cache-controller@1e00a000 { | |
170 | compatible = "arm,pl310-cache"; | |
171 | reg = <0x1e00a000 0x1000>; | |
172 | interrupts = <0 43 4>; | |
2004f98a | 173 | cache-unified; |
cca070a9 PM |
174 | cache-level = <2>; |
175 | arm,data-latency = <1 1 1>; | |
176 | arm,tag-latency = <1 1 1>; | |
177 | }; | |
178 | ||
179 | pmu { | |
180 | compatible = "arm,cortex-a9-pmu"; | |
181 | interrupts = <0 60 4>, | |
182 | <0 61 4>, | |
183 | <0 62 4>, | |
184 | <0 63 4>; | |
613880a1 RS |
185 | interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; |
186 | ||
cca070a9 PM |
187 | }; |
188 | ||
842839a3 PM |
189 | dcc { |
190 | compatible = "arm,vexpress,config-bus"; | |
191 | arm,vexpress,config-bridge = <&v2m_sysreg>; | |
192 | ||
193 | osc@0 { | |
194 | /* ACLK clock to the AXI master port on the test chip */ | |
195 | compatible = "arm,vexpress-osc"; | |
196 | arm,vexpress-sysreg,func = <1 0>; | |
197 | freq-range = <30000000 50000000>; | |
198 | #clock-cells = <0>; | |
199 | clock-output-names = "extsaxiclk"; | |
200 | }; | |
201 | ||
202 | oscclk1: osc@1 { | |
203 | /* Reference clock for the CLCD */ | |
204 | compatible = "arm,vexpress-osc"; | |
205 | arm,vexpress-sysreg,func = <1 1>; | |
206 | freq-range = <10000000 80000000>; | |
207 | #clock-cells = <0>; | |
208 | clock-output-names = "clcdclk"; | |
209 | }; | |
210 | ||
211 | smbclk: oscclk2: osc@2 { | |
212 | /* Reference clock for the test chip internal PLLs */ | |
213 | compatible = "arm,vexpress-osc"; | |
214 | arm,vexpress-sysreg,func = <1 2>; | |
215 | freq-range = <33000000 100000000>; | |
216 | #clock-cells = <0>; | |
217 | clock-output-names = "tcrefclk"; | |
218 | }; | |
219 | ||
220 | volt@0 { | |
221 | /* Test Chip internal logic voltage */ | |
222 | compatible = "arm,vexpress-volt"; | |
223 | arm,vexpress-sysreg,func = <2 0>; | |
224 | regulator-name = "VD10"; | |
225 | regulator-always-on; | |
226 | label = "VD10"; | |
227 | }; | |
228 | ||
229 | volt@1 { | |
230 | /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ | |
231 | compatible = "arm,vexpress-volt"; | |
232 | arm,vexpress-sysreg,func = <2 1>; | |
233 | regulator-name = "VD10_S2"; | |
234 | regulator-always-on; | |
235 | label = "VD10_S2"; | |
236 | }; | |
237 | ||
238 | volt@2 { | |
239 | /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ | |
240 | compatible = "arm,vexpress-volt"; | |
241 | arm,vexpress-sysreg,func = <2 2>; | |
242 | regulator-name = "VD10_S3"; | |
243 | regulator-always-on; | |
244 | label = "VD10_S3"; | |
245 | }; | |
246 | ||
247 | volt@3 { | |
248 | /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ | |
249 | compatible = "arm,vexpress-volt"; | |
250 | arm,vexpress-sysreg,func = <2 3>; | |
251 | regulator-name = "VCC1V8"; | |
252 | regulator-always-on; | |
253 | label = "VCC1V8"; | |
254 | }; | |
255 | ||
256 | volt@4 { | |
257 | /* DDR2 SDRAM VTT termination voltage */ | |
258 | compatible = "arm,vexpress-volt"; | |
259 | arm,vexpress-sysreg,func = <2 4>; | |
260 | regulator-name = "DDR2VTT"; | |
261 | regulator-always-on; | |
262 | label = "DDR2VTT"; | |
263 | }; | |
264 | ||
265 | volt@5 { | |
266 | /* Local board supply for miscellaneous logic external to the Test Chip */ | |
267 | arm,vexpress-sysreg,func = <2 5>; | |
268 | compatible = "arm,vexpress-volt"; | |
269 | regulator-name = "VCC3V3"; | |
270 | regulator-always-on; | |
271 | label = "VCC3V3"; | |
272 | }; | |
273 | ||
274 | amp@0 { | |
275 | /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ | |
276 | compatible = "arm,vexpress-amp"; | |
277 | arm,vexpress-sysreg,func = <3 0>; | |
278 | label = "VD10_S2"; | |
279 | }; | |
280 | ||
281 | amp@1 { | |
282 | /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ | |
283 | compatible = "arm,vexpress-amp"; | |
284 | arm,vexpress-sysreg,func = <3 1>; | |
285 | label = "VD10_S3"; | |
286 | }; | |
287 | ||
288 | power@0 { | |
289 | /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ | |
290 | compatible = "arm,vexpress-power"; | |
291 | arm,vexpress-sysreg,func = <12 0>; | |
292 | label = "PVD10_S2"; | |
293 | }; | |
294 | ||
295 | power@1 { | |
296 | /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ | |
297 | compatible = "arm,vexpress-power"; | |
298 | arm,vexpress-sysreg,func = <12 1>; | |
299 | label = "PVD10_S3"; | |
300 | }; | |
301 | }; | |
302 | ||
433683a6 PM |
303 | smb { |
304 | compatible = "simple-bus"; | |
305 | ||
306 | #address-cells = <2>; | |
307 | #size-cells = <1>; | |
cca070a9 PM |
308 | ranges = <0 0 0x40000000 0x04000000>, |
309 | <1 0 0x44000000 0x04000000>, | |
310 | <2 0 0x48000000 0x04000000>, | |
311 | <3 0 0x4c000000 0x04000000>, | |
312 | <7 0 0x10000000 0x00020000>; | |
313 | ||
433683a6 | 314 | #interrupt-cells = <1>; |
cca070a9 PM |
315 | interrupt-map-mask = <0 0 63>; |
316 | interrupt-map = <0 0 0 &gic 0 0 4>, | |
317 | <0 0 1 &gic 0 1 4>, | |
318 | <0 0 2 &gic 0 2 4>, | |
319 | <0 0 3 &gic 0 3 4>, | |
320 | <0 0 4 &gic 0 4 4>, | |
321 | <0 0 5 &gic 0 5 4>, | |
322 | <0 0 6 &gic 0 6 4>, | |
323 | <0 0 7 &gic 0 7 4>, | |
324 | <0 0 8 &gic 0 8 4>, | |
325 | <0 0 9 &gic 0 9 4>, | |
326 | <0 0 10 &gic 0 10 4>, | |
327 | <0 0 11 &gic 0 11 4>, | |
328 | <0 0 12 &gic 0 12 4>, | |
329 | <0 0 13 &gic 0 13 4>, | |
330 | <0 0 14 &gic 0 14 4>, | |
331 | <0 0 15 &gic 0 15 4>, | |
332 | <0 0 16 &gic 0 16 4>, | |
333 | <0 0 17 &gic 0 17 4>, | |
334 | <0 0 18 &gic 0 18 4>, | |
335 | <0 0 19 &gic 0 19 4>, | |
336 | <0 0 20 &gic 0 20 4>, | |
337 | <0 0 21 &gic 0 21 4>, | |
338 | <0 0 22 &gic 0 22 4>, | |
339 | <0 0 23 &gic 0 23 4>, | |
340 | <0 0 24 &gic 0 24 4>, | |
341 | <0 0 25 &gic 0 25 4>, | |
342 | <0 0 26 &gic 0 26 4>, | |
343 | <0 0 27 &gic 0 27 4>, | |
344 | <0 0 28 &gic 0 28 4>, | |
345 | <0 0 29 &gic 0 29 4>, | |
346 | <0 0 30 &gic 0 30 4>, | |
347 | <0 0 31 &gic 0 31 4>, | |
348 | <0 0 32 &gic 0 32 4>, | |
349 | <0 0 33 &gic 0 33 4>, | |
350 | <0 0 34 &gic 0 34 4>, | |
351 | <0 0 35 &gic 0 35 4>, | |
352 | <0 0 36 &gic 0 36 4>, | |
353 | <0 0 37 &gic 0 37 4>, | |
354 | <0 0 38 &gic 0 38 4>, | |
355 | <0 0 39 &gic 0 39 4>, | |
356 | <0 0 40 &gic 0 40 4>, | |
357 | <0 0 41 &gic 0 41 4>, | |
358 | <0 0 42 &gic 0 42 4>; | |
433683a6 PM |
359 | |
360 | /include/ "vexpress-v2m.dtsi" | |
cca070a9 PM |
361 | }; |
362 | }; |