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efb45b30 SA |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include "skeleton.dtsi" | |
11 | #include "vfxxx.dtsi" | |
12 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
13 | ||
14 | / { | |
15 | cpus { | |
16 | #address-cells = <1>; | |
17 | #size-cells = <0>; | |
18 | ||
19 | a5_cpu: cpu@0 { | |
20 | compatible = "arm,cortex-a5"; | |
21 | device_type = "cpu"; | |
22 | reg = <0x0>; | |
23 | }; | |
24 | }; | |
25 | ||
26 | soc { | |
efb45b30 SA |
27 | aips-bus@40000000 { |
28 | ||
29 | intc: interrupt-controller@40002000 { | |
30 | compatible = "arm,cortex-a9-gic"; | |
31 | #interrupt-cells = <3>; | |
32 | interrupt-controller; | |
c09d0f7c | 33 | interrupt-parent = <&intc>; |
efb45b30 SA |
34 | reg = <0x40003000 0x1000>, |
35 | <0x40002100 0x100>; | |
36 | }; | |
37 | ||
38 | global_timer: timer@40002200 { | |
39 | compatible = "arm,cortex-a9-global-timer"; | |
40 | reg = <0x40002200 0x20>; | |
41 | interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
c09d0f7c | 42 | interrupt-parent = <&intc>; |
efb45b30 SA |
43 | clocks = <&clks VF610_CLK_PLATFORM_BUS>; |
44 | }; | |
45 | }; | |
46 | }; | |
47 | }; | |
48 | ||
c09d0f7c SA |
49 | &mscm_ir { |
50 | interrupt-parent = <&intc>; | |
efb45b30 | 51 | }; |
c134e09f SA |
52 | |
53 | &wdoga5 { | |
c134e09f SA |
54 | status = "okay"; |
55 | }; |