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Merge branch 'core-objtool-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / arm / boot / dts / vf610-twr.dts
CommitLineData
e77b74ee
JL		 1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10/dts-v1/;
11#include "vf610.dtsi"
12
13/ {
14 model = "VF610 Tower Board";
15 compatible = "fsl,vf610-twr", "fsl,vf610";
16
17 chosen {
18 bootargs = "console=ttyLP1,115200";
19 };
20
21 memory {
22 reg = <0x80000000 0x8000000>;
23 };
24
3f3ebfb8
SA		 25 audio_ext: mclk_osc {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <24576000>;
29 };
e77b74ee 30
3f3ebfb8
SA		 31 enet_ext: eth_osc {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <50000000>;
e77b74ee
JL		 35 };
36
c5d571e7
XL		 37 regulators {
38 compatible = "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 reg_3p3v: regulator@0 {
43 compatible = "regulator-fixed";
44 reg = <0>;
45 regulator-name = "3P3V";
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
48 regulator-always-on;
49 };
64436ff6
FD		 50
51 reg_vcc_3v3_mcu: regulator@1 {
52 compatible = "regulator-fixed";
53 reg = <1>;
54 regulator-name = "vcc_3v3_mcu";
55 regulator-min-microvolt = <3300000>;
56 regulator-max-microvolt = <3300000>;
57 };
c5d571e7 58 };
8128c4f3
XL		 59
60 sound {
61 compatible = "simple-audio-card";
62 simple-audio-card,format = "i2s";
63 simple-audio-card,widgets =
64 "Microphone", "Microphone Jack",
65 "Headphone", "Headphone Jack",
66 "Speaker", "Speaker Ext",
67 "Line", "Line In Jack";
68 simple-audio-card,routing =
69 "MIC_IN", "Microphone Jack",
70 "Microphone Jack", "Mic Bias",
71 "LINE_IN", "Line In Jack",
72 "Headphone Jack", "HP_OUT",
73 "Speaker Ext", "LINE_OUT";
74
75 simple-audio-card,cpu {
76 sound-dai = <&sai2>;
8128c4f3
XL		 77 frame-master;
78 bitclock-master;
79 };
80
81 simple-audio-card,codec {
82 sound-dai = <&codec>;
83 frame-master;
84 bitclock-master;
85 };
86 };
e77b74ee
JL		 87};
88
64436ff6
FD		 89&adc0 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_adc0_ad5>;
92 vref-supply = <&reg_vcc_3v3_mcu>;
93 status = "okay";
94};
95
3f3ebfb8
SA		 96&clks {
97 clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
98 clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
99};
100
dc03a50f
CF		 101&dspi0 {
102 bus-num = <0>;
103 pinctrl-names = "default";
07ed1eed 104 pinctrl-0 = <&pinctrl_dspi0>;
dc03a50f
CF		 105 status = "okay";
106
107 sflash: at26df081a@0 {
108 #address-cells = <1>;
109 #size-cells = <1>;
110 compatible = "atmel,at26df081a";
111 spi-max-frequency = <16000000>;
112 spi-cpol;
113 spi-cpha;
114 reg = <0>;
115 };
116};
117
efb45b30
SA		 118&edma0 {
119 status = "okay";
120};
121
0517fe6a
CS		 122&esdhc1 {
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_esdhc1>;
125 bus-width = <4>;
76713954 126 cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
0517fe6a
CS		 127 status = "okay";
128};
129
e77b74ee
JL		 130&fec0 {
131 phy-mode = "rmii";
3d125f9c 132 phy-handle = <&ethphy0>;
e77b74ee 133 pinctrl-names = "default";
07ed1eed 134 pinctrl-0 = <&pinctrl_fec0>;
e77b74ee 135 status = "okay";
3d125f9c
SA		 136
137 mdio {
138 #address-cells = <1>;
139 #size-cells = <0>;
140
141 ethphy0: ethernet-phy@0 {
142 reg = <0>;
143 };
144
145 ethphy1: ethernet-phy@1 {
146 reg = <1>;
147 };
148 };
e77b74ee
JL		 149};
150
151&fec1 {
152 phy-mode = "rmii";
3d125f9c 153 phy-handle = <&ethphy1>;
e77b74ee 154 pinctrl-names = "default";
07ed1eed 155 pinctrl-0 = <&pinctrl_fec1>;
e77b74ee
JL		 156 status = "okay";
157};
158
d45393cd
JL		 159&i2c0 {
160 clock-frequency = <100000>;
161 pinctrl-names = "default";
07ed1eed 162 pinctrl-0 = <&pinctrl_i2c0>;
d45393cd 163 status = "okay";
c5d571e7
XL		 164
165 codec: sgtl5000@0a {
8128c4f3 166 #sound-dai-cells = <0>;
c5d571e7
XL		 167 compatible = "fsl,sgtl5000";
168 reg = <0x0a>;
169 VDDA-supply = <&reg_3p3v>;
170 VDDIO-supply = <&reg_3p3v>;
171 clocks = <&clks VF610_CLK_SAI2>;
172 };
d45393cd
JL		 173};
174
07ed1eed
SG		 175&iomuxc {
176 vf610-twr {
64436ff6
FD		 177 pinctrl_adc0_ad5: adc0ad5grp {
178 fsl,pins = <
179 VF610_PAD_PTC30__ADC0_SE5 0xa1
180 >;
181 };
182
07ed1eed
SG		 183 pinctrl_dspi0: dspi0grp {
184 fsl,pins = <
185 VF610_PAD_PTB19__DSPI0_CS0 0x1182
186 VF610_PAD_PTB20__DSPI0_SIN 0x1181
187 VF610_PAD_PTB21__DSPI0_SOUT 0x1182
188 VF610_PAD_PTB22__DSPI0_SCK 0x1182
189 >;
190 };
191
0517fe6a 192 pinctrl_esdhc1: esdhc1grp {
0aa4dcb5 193 fsl,pins = <
0517fe6a
CS		 194 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
195 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
196 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
197 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
198 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
199 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
200 VF610_PAD_PTA7__GPIO_134 0x219d
201 >;
202 };
203
07ed1eed
SG		 204 pinctrl_fec0: fec0grp {
205 fsl,pins = <
206 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
207 VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3
208 VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
209 VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
210 VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
211 VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
212 VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
213 VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
214 VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
215 VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
216 >;
217 };
218
219 pinctrl_fec1: fec1grp {
220 fsl,pins = <
221 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
222 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
223 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
aa5fec2d 224 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
07ed1eed
SG		 225 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
226 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
227 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
228 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
229 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
230 >;
231 };
232
233 pinctrl_i2c0: i2c0grp {
234 fsl,pins = <
235 VF610_PAD_PTB14__I2C0_SCL 0x30d3
236 VF610_PAD_PTB15__I2C0_SDA 0x30d3
237 >;
238 };
239
baeeb541
SA		 240 pinctrl_nfc: nfcgrp {
241 fsl,pins = <
242 VF610_PAD_PTD31__NF_IO15 0x28df
243 VF610_PAD_PTD30__NF_IO14 0x28df
244 VF610_PAD_PTD29__NF_IO13 0x28df
245 VF610_PAD_PTD28__NF_IO12 0x28df
246 VF610_PAD_PTD27__NF_IO11 0x28df
247 VF610_PAD_PTD26__NF_IO10 0x28df
248 VF610_PAD_PTD25__NF_IO9 0x28df
249 VF610_PAD_PTD24__NF_IO8 0x28df
250 VF610_PAD_PTD23__NF_IO7 0x28df
251 VF610_PAD_PTD22__NF_IO6 0x28df
252 VF610_PAD_PTD21__NF_IO5 0x28df
253 VF610_PAD_PTD20__NF_IO4 0x28df
254 VF610_PAD_PTD19__NF_IO3 0x28df
255 VF610_PAD_PTD18__NF_IO2 0x28df
256 VF610_PAD_PTD17__NF_IO1 0x28df
257 VF610_PAD_PTD16__NF_IO0 0x28df
258 VF610_PAD_PTB24__NF_WE_B 0x28c2
259 VF610_PAD_PTB25__NF_CE0_B 0x28c2
260 VF610_PAD_PTB27__NF_RE_B 0x28c2
261 VF610_PAD_PTC26__NF_RB_B 0x283d
262 VF610_PAD_PTC27__NF_ALE 0x28c2
263 VF610_PAD_PTC28__NF_CLE 0x28c2
264 >;
265 };
266
f54c2fea
XL		 267 pinctrl_pwm0: pwm0grp {
268 fsl,pins = <
269 VF610_PAD_PTB0__FTM0_CH0 0x1582
270 VF610_PAD_PTB1__FTM0_CH1 0x1582
271 VF610_PAD_PTB2__FTM0_CH2 0x1582
272 VF610_PAD_PTB3__FTM0_CH3 0x1582
f54c2fea
XL		 273 >;
274 };
275
95b13b66
XL		 276 pinctrl_sai2: sai2grp {
277 fsl,pins = <
278 VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed
279 VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee
280 VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed
281 VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed
282 VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed
283 VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed
284 VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
285 >;
286 };
287
07ed1eed
SG		 288 pinctrl_uart1: uart1grp {
289 fsl,pins = <
290 VF610_PAD_PTB4__UART1_TX 0x21a2
291 VF610_PAD_PTB5__UART1_RX 0x21a1
292 >;
293 };
d8c99930
BP		 294
295 pinctrl_uart2: uart2grp {
296 fsl,pins = <
297 VF610_PAD_PTB6__UART2_TX 0x21a2
298 VF610_PAD_PTB7__UART2_RX 0x21a1
299 >;
300 };
07ed1eed
SG		 301 };
302};
303
baeeb541
SA		 304&nfc {
305 assigned-clocks = <&clks VF610_CLK_NFC>;
306 assigned-clock-rates = <33000000>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_nfc>;
309 status = "okay";
310
311 nand@0 {
312 compatible = "fsl,vf610-nfc-nandcs";
313 reg = <0>;
314 #address-cells = <1>;
315 #size-cells = <1>;
316 nand-bus-width = <16>;
317 nand-ecc-mode = "hw";
318 nand-ecc-strength = <24>;
319 nand-ecc-step-size = <2048>;
320 nand-on-flash-bbt;
321 };
322};
323
266a71b3
XL		 324&pwm0 {
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_pwm0>;
327 status = "okay";
328};
329
95b13b66 330&sai2 {
8128c4f3 331 #sound-dai-cells = <0>;
95b13b66
XL		 332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_sai2>;
334 status = "okay";
335};
336
e77b74ee
JL		 337&uart1 {
338 pinctrl-names = "default";
07ed1eed 339 pinctrl-0 = <&pinctrl_uart1>;
e77b74ee
JL		 340 status = "okay";
341};
d8c99930
BP		 342
343&uart2 {
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_uart2>;
346 status = "okay";
347};
49b2ae0c
SA		 348
349&usbdev0 {
350 disable-over-current;
351 status = "okay";
352};
353
354&usbh1 {
355 disable-over-current;
356 status = "okay";
357};
efb45b30 358
ac039cd9
SA		 359&usbmisc0 {
360 status = "okay";
361};
362
363&usbmisc1 {
364 status = "okay";
365};
366
efb45b30
SA		 367&usbphy0 {
368 status = "okay";
369};
370
371&usbphy1 {
372 status = "okay";
373};
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