Commit | Line | Data |
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cb935e71 TP |
1 | /* |
2 | * vt8500.dtsi - Device tree file for VIA VT8500 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | |
5 | * | |
6 | * Licensed under GPLv2 or later | |
7 | */ | |
8 | ||
9 | /include/ "skeleton.dtsi" | |
10 | ||
11 | / { | |
12 | compatible = "via,vt8500"; | |
13 | ||
14 | soc { | |
15 | #address-cells = <1>; | |
16 | #size-cells = <1>; | |
17 | compatible = "simple-bus"; | |
18 | ranges; | |
19 | interrupt-parent = <&intc>; | |
20 | ||
21 | intc: interrupt-controller@d8140000 { | |
22 | compatible = "via,vt8500-intc"; | |
23 | interrupt-controller; | |
24 | reg = <0xd8140000 0x10000>; | |
25 | #interrupt-cells = <1>; | |
26 | }; | |
27 | ||
649a59cf TP |
28 | pinctrl: pinctrl@d8110000 { |
29 | compatible = "via,vt8500-pinctrl"; | |
cb935e71 | 30 | reg = <0xd8110000 0x10000>; |
649a59cf TP |
31 | interrupt-controller; |
32 | #interrupt-cells = <2>; | |
33 | gpio-controller; | |
34 | #gpio-cells = <2>; | |
cb935e71 TP |
35 | }; |
36 | ||
37 | pmc@d8130000 { | |
38 | compatible = "via,vt8500-pmc"; | |
39 | reg = <0xd8130000 0x1000>; | |
40 | ||
41 | clocks { | |
42 | #address-cells = <1>; | |
43 | #size-cells = <0>; | |
44 | ||
45 | ref24: ref24M { | |
46 | #clock-cells = <0>; | |
47 | compatible = "fixed-clock"; | |
48 | clock-frequency = <24000000>; | |
49 | }; | |
12faa35a TP |
50 | |
51 | clkuart0: uart0 { | |
52 | #clock-cells = <0>; | |
53 | compatible = "via,vt8500-device-clock"; | |
54 | clocks = <&ref24>; | |
55 | enable-reg = <0x250>; | |
56 | enable-bit = <1>; | |
57 | }; | |
58 | ||
59 | clkuart1: uart1 { | |
60 | #clock-cells = <0>; | |
61 | compatible = "via,vt8500-device-clock"; | |
62 | clocks = <&ref24>; | |
63 | enable-reg = <0x250>; | |
64 | enable-bit = <2>; | |
65 | }; | |
66 | ||
67 | clkuart2: uart2 { | |
68 | #clock-cells = <0>; | |
69 | compatible = "via,vt8500-device-clock"; | |
70 | clocks = <&ref24>; | |
71 | enable-reg = <0x250>; | |
72 | enable-bit = <3>; | |
73 | }; | |
74 | ||
75 | clkuart3: uart3 { | |
76 | #clock-cells = <0>; | |
77 | compatible = "via,vt8500-device-clock"; | |
78 | clocks = <&ref24>; | |
79 | enable-reg = <0x250>; | |
80 | enable-bit = <4>; | |
81 | }; | |
cb935e71 TP |
82 | }; |
83 | }; | |
84 | ||
85 | timer@d8130100 { | |
86 | compatible = "via,vt8500-timer"; | |
87 | reg = <0xd8130100 0x28>; | |
88 | interrupts = <36>; | |
89 | }; | |
90 | ||
91 | ehci@d8007900 { | |
92 | compatible = "via,vt8500-ehci"; | |
93 | reg = <0xd8007900 0x200>; | |
94 | interrupts = <43>; | |
95 | }; | |
96 | ||
97 | uhci@d8007b00 { | |
98 | compatible = "platform-uhci"; | |
99 | reg = <0xd8007b00 0x200>; | |
100 | interrupts = <43>; | |
101 | }; | |
102 | ||
7ab0a484 | 103 | fb: fb@d8050800 { |
cb935e71 TP |
104 | compatible = "via,vt8500-fb"; |
105 | reg = <0xd800e400 0x400>; | |
106 | interrupts = <12>; | |
cb935e71 TP |
107 | }; |
108 | ||
109 | ge_rops@d8050400 { | |
110 | compatible = "wm,prizm-ge-rops"; | |
111 | reg = <0xd8050400 0x100>; | |
112 | }; | |
113 | ||
114 | uart@d8200000 { | |
115 | compatible = "via,vt8500-uart"; | |
116 | reg = <0xd8200000 0x1040>; | |
117 | interrupts = <32>; | |
12faa35a | 118 | clocks = <&clkuart0>; |
cb935e71 TP |
119 | }; |
120 | ||
121 | uart@d82b0000 { | |
122 | compatible = "via,vt8500-uart"; | |
123 | reg = <0xd82b0000 0x1040>; | |
124 | interrupts = <33>; | |
12faa35a | 125 | clocks = <&clkuart1>; |
cb935e71 TP |
126 | }; |
127 | ||
128 | uart@d8210000 { | |
129 | compatible = "via,vt8500-uart"; | |
130 | reg = <0xd8210000 0x1040>; | |
131 | interrupts = <47>; | |
12faa35a | 132 | clocks = <&clkuart2>; |
cb935e71 TP |
133 | }; |
134 | ||
135 | uart@d82c0000 { | |
136 | compatible = "via,vt8500-uart"; | |
137 | reg = <0xd82c0000 0x1040>; | |
138 | interrupts = <50>; | |
12faa35a | 139 | clocks = <&clkuart3>; |
cb935e71 TP |
140 | }; |
141 | ||
142 | rtc@d8100000 { | |
143 | compatible = "via,vt8500-rtc"; | |
144 | reg = <0xd8100000 0x10000>; | |
145 | interrupts = <48>; | |
146 | }; | |
147 | }; | |
148 | }; |