projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| cb935e71 TP |
1 | /* |
| 2 | * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | |
| 5 | * | |
| 6 | * Licensed under GPLv2 or later | |
| 7 | */ | |
| 8 | ||
| 9 | /include/ "skeleton.dtsi" | |
| 10 | ||
| 11 | / { | |
| 12 | compatible = "wm,wm8505"; | |
| 13 | ||
| 14 | cpus { | |
| 7ec13d42 TP |
15 | #address-cells = <0>; |
| 16 | #size-cells = <0>; | |
| 17 | ||
| 18 | cpu { | |
| 19 | device_type = "cpu"; | |
| 20 | compatible = "arm,arm926ej-s"; | |
| cb935e71 TP |
21 | }; |
| 22 | }; | |
| 23 | ||
| 55954f85 TP |
24 | aliases { |
| 25 | serial0 = &uart0; | |
| 26 | serial1 = &uart1; | |
| 27 | serial2 = &uart2; | |
| 28 | serial3 = &uart3; | |
| 29 | serial4 = &uart4; | |
| 30 | serial5 = &uart5; | |
| 31 | }; | |
| 32 | ||
| cb935e71 TP |
33 | soc { |
| 34 | #address-cells = <1>; | |
| 35 | #size-cells = <1>; | |
| 36 | compatible = "simple-bus"; | |
| 37 | ranges; | |
| 38 | interrupt-parent = <&intc0>; | |
| 39 | ||
| 40 | intc0: interrupt-controller@d8140000 { | |
| 41 | compatible = "via,vt8500-intc"; | |
| 42 | interrupt-controller; | |
| 43 | reg = <0xd8140000 0x10000>; | |
| 44 | #interrupt-cells = <1>; | |
| 45 | }; | |
| 46 | ||
| 47 | /* Secondary IC cascaded to intc0 */ | |
| 48 | intc1: interrupt-controller@d8150000 { | |
| 49 | compatible = "via,vt8500-intc"; | |
| 50 | interrupt-controller; | |
| 51 | #interrupt-cells = <1>; | |
| 52 | reg = <0xD8150000 0x10000>; | |
| 53 | interrupts = <56 57 58 59 60 61 62 63>; | |
| 54 | }; | |
| 55 | ||
| 649a59cf TP |
56 | pinctrl: pinctrl@d8110000 { |
| 57 | compatible = "wm,wm8505-pinctrl"; | |
| cb935e71 | 58 | reg = <0xd8110000 0x10000>; |
| 649a59cf TP |
59 | interrupt-controller; |
| 60 | #interrupt-cells = <2>; | |
| 61 | gpio-controller; | |
| 62 | #gpio-cells = <2>; | |
| cb935e71 TP |
63 | }; |
| 64 | ||
| 65 | pmc@d8130000 { | |
| 66 | compatible = "via,vt8500-pmc"; | |
| 67 | reg = <0xd8130000 0x1000>; | |
| 68 | clocks { | |
| 69 | #address-cells = <1>; | |
| 70 | #size-cells = <0>; | |
| 71 | ||
| 72 | ref24: ref24M { | |
| 73 | #clock-cells = <0>; | |
| 74 | compatible = "fixed-clock"; | |
| 75 | clock-frequency = <24000000>; | |
| 76 | }; | |
| 12faa35a | 77 | |
| 3e87515a TP |
78 | ref25: ref25M { |
| 79 | #clock-cells = <0>; | |
| 80 | compatible = "fixed-clock"; | |
| 81 | clock-frequency = <25000000>; | |
| 82 | }; | |
| 83 | ||
| 84 | pllb: pllb { | |
| 85 | #clock-cells = <0>; | |
| 86 | compatible = "via,vt8500-pll-clock"; | |
| 87 | clocks = <&ref25>; | |
| 88 | reg = <0x204>; | |
| 89 | }; | |
| 90 | ||
| 12faa35a TP |
91 | clkuart0: uart0 { |
| 92 | #clock-cells = <0>; | |
| 93 | compatible = "via,vt8500-device-clock"; | |
| 94 | clocks = <&ref24>; | |
| 95 | enable-reg = <0x250>; | |
| 96 | enable-bit = <1>; | |
| 97 | }; | |
| 98 | ||
| 99 | clkuart1: uart1 { | |
| 100 | #clock-cells = <0>; | |
| 101 | compatible = "via,vt8500-device-clock"; | |
| 102 | clocks = <&ref24>; | |
| 103 | enable-reg = <0x250>; | |
| 104 | enable-bit = <2>; | |
| 105 | }; | |
| 106 | ||
| 107 | clkuart2: uart2 { | |
| 108 | #clock-cells = <0>; | |
| 109 | compatible = "via,vt8500-device-clock"; | |
| 110 | clocks = <&ref24>; | |
| 111 | enable-reg = <0x250>; | |
| 112 | enable-bit = <3>; | |
| 113 | }; | |
| 114 | ||
| 115 | clkuart3: uart3 { | |
| 116 | #clock-cells = <0>; | |
| 117 | compatible = "via,vt8500-device-clock"; | |
| 118 | clocks = <&ref24>; | |
| 119 | enable-reg = <0x250>; | |
| 120 | enable-bit = <4>; | |
| 121 | }; | |
| 122 | ||
| 123 | clkuart4: uart4 { | |
| 124 | #clock-cells = <0>; | |
| 125 | compatible = "via,vt8500-device-clock"; | |
| 126 | clocks = <&ref24>; | |
| 127 | enable-reg = <0x250>; | |
| 128 | enable-bit = <22>; | |
| 129 | }; | |
| 130 | ||
| 131 | clkuart5: uart5 { | |
| 132 | #clock-cells = <0>; | |
| 133 | compatible = "via,vt8500-device-clock"; | |
| 134 | clocks = <&ref24>; | |
| 135 | enable-reg = <0x250>; | |
| 136 | enable-bit = <23>; | |
| 137 | }; | |
| 3e87515a TP |
138 | |
| 139 | clksdhc: sdhc { | |
| 140 | #clock-cells = <0>; | |
| 141 | compatible = "via,vt8500-device-clock"; | |
| 142 | clocks = <&pllb>; | |
| 143 | divisor-reg = <0x328>; | |
| 144 | divisor-mask = <0x3f>; | |
| 145 | enable-reg = <0x254>; | |
| 146 | enable-bit = <18>; | |
| 147 | }; | |
| cb935e71 TP |
148 | }; |
| 149 | }; | |
| 150 | ||
| 151 | timer@d8130100 { | |
| 152 | compatible = "via,vt8500-timer"; | |
| 153 | reg = <0xd8130100 0x28>; | |
| 154 | interrupts = <36>; | |
| 155 | }; | |
| 156 | ||
| 157 | ehci@d8007100 { | |
| 158 | compatible = "via,vt8500-ehci"; | |
| 159 | reg = <0xd8007100 0x200>; | |
| 5448a279 | 160 | interrupts = <1>; |
| cb935e71 TP |
161 | }; |
| 162 | ||
| 163 | uhci@d8007300 { | |
| 164 | compatible = "platform-uhci"; | |
| 165 | reg = <0xd8007300 0x200>; | |
| 5448a279 | 166 | interrupts = <0>; |
| cb935e71 TP |
167 | }; |
| 168 | ||
| 7ab0a484 | 169 | fb: fb@d8050800 { |
| cb935e71 TP |
170 | compatible = "wm,wm8505-fb"; |
| 171 | reg = <0xd8050800 0x200>; | |
| cb935e71 TP |
172 | }; |
| 173 | ||
| 174 | ge_rops@d8050400 { | |
| 175 | compatible = "wm,prizm-ge-rops"; | |
| 176 | reg = <0xd8050400 0x100>; | |
| 177 | }; | |
| 178 | ||
| 55954f85 | 179 | uart0: serial@d8200000 { |
| cb935e71 TP |
180 | compatible = "via,vt8500-uart"; |
| 181 | reg = <0xd8200000 0x1040>; | |
| 182 | interrupts = <32>; | |
| 12faa35a | 183 | clocks = <&clkuart0>; |
| 55954f85 | 184 | status = "disabled"; |
| cb935e71 TP |
185 | }; |
| 186 | ||
| 55954f85 | 187 | uart1: serial@d82b0000 { |
| cb935e71 TP |
188 | compatible = "via,vt8500-uart"; |
| 189 | reg = <0xd82b0000 0x1040>; | |
| 190 | interrupts = <33>; | |
| 12faa35a | 191 | clocks = <&clkuart1>; |
| 55954f85 | 192 | status = "disabled"; |
| cb935e71 TP |
193 | }; |
| 194 | ||
| 55954f85 | 195 | uart2: serial@d8210000 { |
| cb935e71 TP |
196 | compatible = "via,vt8500-uart"; |
| 197 | reg = <0xd8210000 0x1040>; | |
| 198 | interrupts = <47>; | |
| 12faa35a | 199 | clocks = <&clkuart2>; |
| 55954f85 | 200 | status = "disabled"; |
| cb935e71 TP |
201 | }; |
| 202 | ||
| 55954f85 | 203 | uart3: serial@d82c0000 { |
| cb935e71 TP |
204 | compatible = "via,vt8500-uart"; |
| 205 | reg = <0xd82c0000 0x1040>; | |
| 206 | interrupts = <50>; | |
| 12faa35a | 207 | clocks = <&clkuart3>; |
| 55954f85 | 208 | status = "disabled"; |
| cb935e71 TP |
209 | }; |
| 210 | ||
| 55954f85 | 211 | uart4: serial@d8370000 { |
| cb935e71 TP |
212 | compatible = "via,vt8500-uart"; |
| 213 | reg = <0xd8370000 0x1040>; | |
| 214 | interrupts = <31>; | |
| 12faa35a | 215 | clocks = <&clkuart4>; |
| 55954f85 | 216 | status = "disabled"; |
| cb935e71 TP |
217 | }; |
| 218 | ||
| 55954f85 | 219 | uart5: serial@d8380000 { |
| cb935e71 TP |
220 | compatible = "via,vt8500-uart"; |
| 221 | reg = <0xd8380000 0x1040>; | |
| 222 | interrupts = <30>; | |
| 12faa35a | 223 | clocks = <&clkuart5>; |
| 55954f85 | 224 | status = "disabled"; |
| cb935e71 TP |
225 | }; |
| 226 | ||
| 227 | rtc@d8100000 { | |
| 228 | compatible = "via,vt8500-rtc"; | |
| 229 | reg = <0xd8100000 0x10000>; | |
| 230 | interrupts = <48>; | |
| 231 | }; | |
| 3e87515a TP |
232 | |
| 233 | sdhc@d800a000 { | |
| 234 | compatible = "wm,wm8505-sdhc"; | |
| 235 | reg = <0xd800a000 0x1000>; | |
| 236 | interrupts = <20 21>; | |
| 237 | clocks = <&clksdhc>; | |
| 238 | bus-width = <4>; | |
| 239 | }; | |
| cb935e71 TP |
240 | }; |
| 241 | }; |