Commit | Line | Data |
---|---|---|
cb935e71 TP |
1 | /* |
2 | * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | |
5 | * | |
6 | * Licensed under GPLv2 or later | |
7 | */ | |
8 | ||
9 | /include/ "skeleton.dtsi" | |
10 | ||
11 | / { | |
12 | compatible = "wm,wm8650"; | |
13 | ||
7ec13d42 TP |
14 | cpus { |
15 | #address-cells = <0>; | |
16 | #size-cells = <0>; | |
17 | ||
18 | cpu { | |
19 | device_type = "cpu"; | |
20 | compatible = "arm,arm926ej-s"; | |
21 | }; | |
22 | }; | |
23 | ||
55954f85 TP |
24 | aliases { |
25 | serial0 = &uart0; | |
26 | serial1 = &uart1; | |
27 | }; | |
28 | ||
cb935e71 TP |
29 | soc { |
30 | #address-cells = <1>; | |
31 | #size-cells = <1>; | |
32 | compatible = "simple-bus"; | |
33 | ranges; | |
34 | interrupt-parent = <&intc0>; | |
35 | ||
36 | intc0: interrupt-controller@d8140000 { | |
37 | compatible = "via,vt8500-intc"; | |
38 | interrupt-controller; | |
39 | reg = <0xd8140000 0x10000>; | |
40 | #interrupt-cells = <1>; | |
41 | }; | |
42 | ||
43 | /* Secondary IC cascaded to intc0 */ | |
44 | intc1: interrupt-controller@d8150000 { | |
45 | compatible = "via,vt8500-intc"; | |
46 | interrupt-controller; | |
47 | #interrupt-cells = <1>; | |
48 | reg = <0xD8150000 0x10000>; | |
49 | interrupts = <56 57 58 59 60 61 62 63>; | |
50 | }; | |
51 | ||
649a59cf TP |
52 | pinctrl: pinctrl@d8110000 { |
53 | compatible = "wm,wm8650-pinctrl"; | |
cb935e71 | 54 | reg = <0xd8110000 0x10000>; |
649a59cf TP |
55 | interrupt-controller; |
56 | #interrupt-cells = <2>; | |
57 | gpio-controller; | |
58 | #gpio-cells = <2>; | |
cb935e71 TP |
59 | }; |
60 | ||
61 | pmc@d8130000 { | |
62 | compatible = "via,vt8500-pmc"; | |
63 | reg = <0xd8130000 0x1000>; | |
64 | ||
65 | clocks { | |
66 | #address-cells = <1>; | |
67 | #size-cells = <0>; | |
68 | ||
69 | ref25: ref25M { | |
70 | #clock-cells = <0>; | |
71 | compatible = "fixed-clock"; | |
72 | clock-frequency = <25000000>; | |
73 | }; | |
74 | ||
75 | ref24: ref24M { | |
76 | #clock-cells = <0>; | |
77 | compatible = "fixed-clock"; | |
78 | clock-frequency = <24000000>; | |
79 | }; | |
80 | ||
81 | plla: plla { | |
82 | #clock-cells = <0>; | |
83 | compatible = "wm,wm8650-pll-clock"; | |
84 | clocks = <&ref25>; | |
85 | reg = <0x200>; | |
86 | }; | |
87 | ||
88 | pllb: pllb { | |
89 | #clock-cells = <0>; | |
90 | compatible = "wm,wm8650-pll-clock"; | |
91 | clocks = <&ref25>; | |
92 | reg = <0x204>; | |
93 | }; | |
94 | ||
12faa35a TP |
95 | clkuart0: uart0 { |
96 | #clock-cells = <0>; | |
97 | compatible = "via,vt8500-device-clock"; | |
98 | clocks = <&ref24>; | |
99 | enable-reg = <0x250>; | |
100 | enable-bit = <1>; | |
101 | }; | |
102 | ||
103 | clkuart1: uart1 { | |
104 | #clock-cells = <0>; | |
105 | compatible = "via,vt8500-device-clock"; | |
106 | clocks = <&ref24>; | |
107 | enable-reg = <0x250>; | |
108 | enable-bit = <2>; | |
109 | }; | |
110 | ||
cb935e71 TP |
111 | arm: arm { |
112 | #clock-cells = <0>; | |
113 | compatible = "via,vt8500-device-clock"; | |
114 | clocks = <&plla>; | |
115 | divisor-reg = <0x300>; | |
116 | }; | |
117 | ||
118 | sdhc: sdhc { | |
119 | #clock-cells = <0>; | |
120 | compatible = "via,vt8500-device-clock"; | |
121 | clocks = <&pllb>; | |
122 | divisor-reg = <0x328>; | |
123 | divisor-mask = <0x3f>; | |
124 | enable-reg = <0x254>; | |
125 | enable-bit = <18>; | |
126 | }; | |
127 | }; | |
128 | }; | |
129 | ||
130 | timer@d8130100 { | |
131 | compatible = "via,vt8500-timer"; | |
132 | reg = <0xd8130100 0x28>; | |
133 | interrupts = <36>; | |
134 | }; | |
135 | ||
136 | ehci@d8007900 { | |
137 | compatible = "via,vt8500-ehci"; | |
138 | reg = <0xd8007900 0x200>; | |
139 | interrupts = <43>; | |
140 | }; | |
141 | ||
142 | uhci@d8007b00 { | |
143 | compatible = "platform-uhci"; | |
144 | reg = <0xd8007b00 0x200>; | |
145 | interrupts = <43>; | |
146 | }; | |
147 | ||
7ab0a484 | 148 | fb: fb@d8050800 { |
cb935e71 TP |
149 | compatible = "wm,wm8505-fb"; |
150 | reg = <0xd8050800 0x200>; | |
cb935e71 TP |
151 | }; |
152 | ||
153 | ge_rops@d8050400 { | |
154 | compatible = "wm,prizm-ge-rops"; | |
155 | reg = <0xd8050400 0x100>; | |
156 | }; | |
157 | ||
55954f85 | 158 | uart0: serial@d8200000 { |
cb935e71 TP |
159 | compatible = "via,vt8500-uart"; |
160 | reg = <0xd8200000 0x1040>; | |
161 | interrupts = <32>; | |
12faa35a | 162 | clocks = <&clkuart0>; |
55954f85 | 163 | status = "disabled"; |
cb935e71 TP |
164 | }; |
165 | ||
55954f85 | 166 | uart1: serial@d82b0000 { |
cb935e71 TP |
167 | compatible = "via,vt8500-uart"; |
168 | reg = <0xd82b0000 0x1040>; | |
169 | interrupts = <33>; | |
12faa35a | 170 | clocks = <&clkuart1>; |
55954f85 | 171 | status = "disabled"; |
cb935e71 TP |
172 | }; |
173 | ||
174 | rtc@d8100000 { | |
175 | compatible = "via,vt8500-rtc"; | |
176 | reg = <0xd8100000 0x10000>; | |
177 | interrupts = <48>; | |
178 | }; | |
179 | }; | |
180 | }; |