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b85a3ef4 JL |
1 | /* |
2 | * Copyright (C) 2011 Xilinx | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
e06f1a9e | 13 | /include/ "skeleton.dtsi" |
b85a3ef4 | 14 | |
b85a3ef4 | 15 | / { |
e06f1a9e | 16 | compatible = "xlnx,zynq-7000"; |
b85a3ef4 | 17 | |
268a8200 MS |
18 | pmu { |
19 | compatible = "arm,cortex-a9-pmu"; | |
20 | interrupts = <0 5 4>, <0 6 4>; | |
21 | interrupt-parent = <&intc>; | |
22 | reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; | |
23 | }; | |
24 | ||
b85a3ef4 JL |
25 | amba { |
26 | compatible = "simple-bus"; | |
27 | #address-cells = <1>; | |
28 | #size-cells = <1>; | |
e06f1a9e | 29 | interrupt-parent = <&intc>; |
b85a3ef4 JL |
30 | ranges; |
31 | ||
32 | intc: interrupt-controller@f8f01000 { | |
f447ed2d JC |
33 | compatible = "arm,cortex-a9-gic"; |
34 | #interrupt-cells = <3>; | |
35 | #address-cells = <1>; | |
b85a3ef4 | 36 | interrupt-controller; |
f447ed2d JC |
37 | reg = <0xF8F01000 0x1000>, |
38 | <0xF8F00100 0x100>; | |
b85a3ef4 JL |
39 | }; |
40 | ||
0fcfdbca JC |
41 | L2: cache-controller { |
42 | compatible = "arm,pl310-cache"; | |
43 | reg = <0xF8F02000 0x1000>; | |
44 | arm,data-latency = <2 3 2>; | |
45 | arm,tag-latency = <2 3 2>; | |
46 | cache-unified; | |
47 | cache-level = <2>; | |
48 | }; | |
49 | ||
b85a3ef4 JL |
50 | uart0: uart@e0000000 { |
51 | compatible = "xlnx,xuartps"; | |
52 | reg = <0xE0000000 0x1000>; | |
f447ed2d | 53 | interrupts = <0 27 4>; |
2326669c | 54 | clocks = <&uart_clk 0>; |
b85a3ef4 | 55 | }; |
78d6785d JC |
56 | |
57 | uart1: uart@e0001000 { | |
58 | compatible = "xlnx,xuartps"; | |
59 | reg = <0xE0001000 0x1000>; | |
60 | interrupts = <0 50 4>; | |
2326669c | 61 | clocks = <&uart_clk 1>; |
78d6785d | 62 | }; |
0f586fbf JC |
63 | |
64 | slcr: slcr@f8000000 { | |
65 | compatible = "xlnx,zynq-slcr"; | |
66 | reg = <0xF8000000 0x1000>; | |
67 | ||
68 | clocks { | |
69 | #address-cells = <1>; | |
70 | #size-cells = <0>; | |
71 | ||
72 | ps_clk: ps_clk { | |
73 | #clock-cells = <0>; | |
74 | compatible = "fixed-clock"; | |
75 | /* clock-frequency set in board-specific file */ | |
76 | clock-output-names = "ps_clk"; | |
77 | }; | |
78 | armpll: armpll { | |
79 | #clock-cells = <0>; | |
80 | compatible = "xlnx,zynq-pll"; | |
81 | clocks = <&ps_clk>; | |
82 | reg = <0x100 0x110>; | |
83 | clock-output-names = "armpll"; | |
84 | }; | |
85 | ddrpll: ddrpll { | |
86 | #clock-cells = <0>; | |
87 | compatible = "xlnx,zynq-pll"; | |
88 | clocks = <&ps_clk>; | |
89 | reg = <0x104 0x114>; | |
90 | clock-output-names = "ddrpll"; | |
91 | }; | |
92 | iopll: iopll { | |
93 | #clock-cells = <0>; | |
94 | compatible = "xlnx,zynq-pll"; | |
95 | clocks = <&ps_clk>; | |
96 | reg = <0x108 0x118>; | |
97 | clock-output-names = "iopll"; | |
98 | }; | |
99 | uart_clk: uart_clk { | |
100 | #clock-cells = <1>; | |
101 | compatible = "xlnx,zynq-periph-clock"; | |
102 | clocks = <&iopll &armpll &ddrpll>; | |
103 | reg = <0x154>; | |
104 | clock-output-names = "uart0_ref_clk", | |
105 | "uart1_ref_clk"; | |
106 | }; | |
107 | cpu_clk: cpu_clk { | |
108 | #clock-cells = <1>; | |
109 | compatible = "xlnx,zynq-cpu-clock"; | |
110 | clocks = <&iopll &armpll &ddrpll>; | |
111 | reg = <0x120 0x1C4>; | |
112 | clock-output-names = "cpu_6x4x", | |
113 | "cpu_3x2x", | |
114 | "cpu_2x", | |
115 | "cpu_1x"; | |
116 | }; | |
117 | }; | |
118 | }; | |
91dc985c JC |
119 | |
120 | ttc0: ttc0@f8001000 { | |
e932900a MS |
121 | interrupt-parent = <&intc>; |
122 | interrupts = < 0 10 4 0 11 4 0 12 4 >; | |
123 | compatible = "cdns,ttc"; | |
91dc985c JC |
124 | reg = <0xF8001000 0x1000>; |
125 | clocks = <&cpu_clk 3>; | |
126 | clock-names = "cpu_1x"; | |
127 | clock-ranges; | |
91dc985c JC |
128 | }; |
129 | ||
130 | ttc1: ttc1@f8002000 { | |
e932900a MS |
131 | interrupt-parent = <&intc>; |
132 | interrupts = < 0 37 4 0 38 4 0 39 4 >; | |
133 | compatible = "cdns,ttc"; | |
91dc985c JC |
134 | reg = <0xF8002000 0x1000>; |
135 | clocks = <&cpu_clk 3>; | |
136 | clock-names = "cpu_1x"; | |
137 | clock-ranges; | |
91dc985c | 138 | }; |
2f34e0a5 MS |
139 | scutimer: scutimer@f8f00600 { |
140 | interrupt-parent = <&intc>; | |
141 | interrupts = < 1 13 0x301 >; | |
142 | compatible = "arm,cortex-a9-twd-timer"; | |
143 | reg = < 0xf8f00600 0x20 >; | |
144 | clocks = <&cpu_clk 1>; | |
145 | } ; | |
b85a3ef4 JL |
146 | }; |
147 | }; |