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b85a3ef4 JL |
1 | /* |
2 | * Copyright (C) 2011 Xilinx | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
e06f1a9e | 13 | /include/ "skeleton.dtsi" |
b85a3ef4 | 14 | |
b85a3ef4 | 15 | / { |
e06f1a9e | 16 | compatible = "xlnx,zynq-7000"; |
b85a3ef4 JL |
17 | |
18 | amba { | |
19 | compatible = "simple-bus"; | |
20 | #address-cells = <1>; | |
21 | #size-cells = <1>; | |
e06f1a9e | 22 | interrupt-parent = <&intc>; |
b85a3ef4 JL |
23 | ranges; |
24 | ||
25 | intc: interrupt-controller@f8f01000 { | |
f447ed2d JC |
26 | compatible = "arm,cortex-a9-gic"; |
27 | #interrupt-cells = <3>; | |
28 | #address-cells = <1>; | |
b85a3ef4 | 29 | interrupt-controller; |
f447ed2d JC |
30 | reg = <0xF8F01000 0x1000>, |
31 | <0xF8F00100 0x100>; | |
b85a3ef4 JL |
32 | }; |
33 | ||
0fcfdbca JC |
34 | L2: cache-controller { |
35 | compatible = "arm,pl310-cache"; | |
36 | reg = <0xF8F02000 0x1000>; | |
37 | arm,data-latency = <2 3 2>; | |
38 | arm,tag-latency = <2 3 2>; | |
39 | cache-unified; | |
40 | cache-level = <2>; | |
41 | }; | |
42 | ||
b85a3ef4 JL |
43 | uart0: uart@e0000000 { |
44 | compatible = "xlnx,xuartps"; | |
45 | reg = <0xE0000000 0x1000>; | |
f447ed2d | 46 | interrupts = <0 27 4>; |
b85a3ef4 JL |
47 | clock = <50000000>; |
48 | }; | |
78d6785d JC |
49 | |
50 | uart1: uart@e0001000 { | |
51 | compatible = "xlnx,xuartps"; | |
52 | reg = <0xE0001000 0x1000>; | |
53 | interrupts = <0 50 4>; | |
54 | clock = <50000000>; | |
55 | }; | |
b85a3ef4 JL |
56 | }; |
57 | }; |