Commit | Line | Data |
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a4768d22 KH |
1 | /* |
2 | * EDMA3 support for DaVinci | |
3 | * | |
4 | * Copyright (C) 2006-2009 Texas Instruments. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
e7eff702 | 20 | #include <linux/err.h> |
a4768d22 | 21 | #include <linux/kernel.h> |
a4768d22 KH |
22 | #include <linux/init.h> |
23 | #include <linux/module.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/platform_device.h> | |
a4768d22 | 26 | #include <linux/io.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
6cba4355 MP |
28 | #include <linux/edma.h> |
29 | #include <linux/err.h> | |
30 | #include <linux/of_address.h> | |
31 | #include <linux/of_device.h> | |
32 | #include <linux/of_dma.h> | |
33 | #include <linux/of_irq.h> | |
34 | #include <linux/pm_runtime.h> | |
a4768d22 | 35 | |
3ad7a42d | 36 | #include <linux/platform_data/edma.h> |
a4768d22 KH |
37 | |
38 | /* Offsets matching "struct edmacc_param" */ | |
39 | #define PARM_OPT 0x00 | |
40 | #define PARM_SRC 0x04 | |
41 | #define PARM_A_B_CNT 0x08 | |
42 | #define PARM_DST 0x0c | |
43 | #define PARM_SRC_DST_BIDX 0x10 | |
44 | #define PARM_LINK_BCNTRLD 0x14 | |
45 | #define PARM_SRC_DST_CIDX 0x18 | |
46 | #define PARM_CCNT 0x1c | |
47 | ||
48 | #define PARM_SIZE 0x20 | |
49 | ||
50 | /* Offsets for EDMA CC global channel registers and their shadows */ | |
51 | #define SH_ER 0x00 /* 64 bits */ | |
52 | #define SH_ECR 0x08 /* 64 bits */ | |
53 | #define SH_ESR 0x10 /* 64 bits */ | |
54 | #define SH_CER 0x18 /* 64 bits */ | |
55 | #define SH_EER 0x20 /* 64 bits */ | |
56 | #define SH_EECR 0x28 /* 64 bits */ | |
57 | #define SH_EESR 0x30 /* 64 bits */ | |
58 | #define SH_SER 0x38 /* 64 bits */ | |
59 | #define SH_SECR 0x40 /* 64 bits */ | |
60 | #define SH_IER 0x50 /* 64 bits */ | |
61 | #define SH_IECR 0x58 /* 64 bits */ | |
62 | #define SH_IESR 0x60 /* 64 bits */ | |
63 | #define SH_IPR 0x68 /* 64 bits */ | |
64 | #define SH_ICR 0x70 /* 64 bits */ | |
65 | #define SH_IEVAL 0x78 | |
66 | #define SH_QER 0x80 | |
67 | #define SH_QEER 0x84 | |
68 | #define SH_QEECR 0x88 | |
69 | #define SH_QEESR 0x8c | |
70 | #define SH_QSER 0x90 | |
71 | #define SH_QSECR 0x94 | |
72 | #define SH_SIZE 0x200 | |
73 | ||
74 | /* Offsets for EDMA CC global registers */ | |
75 | #define EDMA_REV 0x0000 | |
76 | #define EDMA_CCCFG 0x0004 | |
77 | #define EDMA_QCHMAP 0x0200 /* 8 registers */ | |
78 | #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ | |
79 | #define EDMA_QDMAQNUM 0x0260 | |
80 | #define EDMA_QUETCMAP 0x0280 | |
81 | #define EDMA_QUEPRI 0x0284 | |
82 | #define EDMA_EMR 0x0300 /* 64 bits */ | |
83 | #define EDMA_EMCR 0x0308 /* 64 bits */ | |
84 | #define EDMA_QEMR 0x0310 | |
85 | #define EDMA_QEMCR 0x0314 | |
86 | #define EDMA_CCERR 0x0318 | |
87 | #define EDMA_CCERRCLR 0x031c | |
88 | #define EDMA_EEVAL 0x0320 | |
89 | #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ | |
90 | #define EDMA_QRAE 0x0380 /* 4 registers */ | |
91 | #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ | |
92 | #define EDMA_QSTAT 0x0600 /* 2 registers */ | |
93 | #define EDMA_QWMTHRA 0x0620 | |
94 | #define EDMA_QWMTHRB 0x0624 | |
95 | #define EDMA_CCSTAT 0x0640 | |
96 | ||
97 | #define EDMA_M 0x1000 /* global channel registers */ | |
98 | #define EDMA_ECR 0x1008 | |
99 | #define EDMA_ECRH 0x100C | |
100 | #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ | |
101 | #define EDMA_PARM 0x4000 /* 128 param entries */ | |
102 | ||
a4768d22 KH |
103 | #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) |
104 | ||
60902a2c SR |
105 | #define EDMA_DCHMAP 0x0100 /* 64 registers */ |
106 | #define CHMAP_EXIST BIT(24) | |
107 | ||
a4768d22 KH |
108 | #define EDMA_MAX_DMACH 64 |
109 | #define EDMA_MAX_PARAMENTRY 512 | |
a4768d22 KH |
110 | |
111 | /*****************************************************************************/ | |
112 | ||
60902a2c | 113 | static void __iomem *edmacc_regs_base[EDMA_MAX_CC]; |
a4768d22 | 114 | |
60902a2c | 115 | static inline unsigned int edma_read(unsigned ctlr, int offset) |
a4768d22 | 116 | { |
60902a2c | 117 | return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset); |
a4768d22 KH |
118 | } |
119 | ||
60902a2c | 120 | static inline void edma_write(unsigned ctlr, int offset, int val) |
a4768d22 | 121 | { |
60902a2c | 122 | __raw_writel(val, edmacc_regs_base[ctlr] + offset); |
a4768d22 | 123 | } |
60902a2c SR |
124 | static inline void edma_modify(unsigned ctlr, int offset, unsigned and, |
125 | unsigned or) | |
a4768d22 | 126 | { |
60902a2c | 127 | unsigned val = edma_read(ctlr, offset); |
a4768d22 KH |
128 | val &= and; |
129 | val |= or; | |
60902a2c | 130 | edma_write(ctlr, offset, val); |
a4768d22 | 131 | } |
60902a2c | 132 | static inline void edma_and(unsigned ctlr, int offset, unsigned and) |
a4768d22 | 133 | { |
60902a2c | 134 | unsigned val = edma_read(ctlr, offset); |
a4768d22 | 135 | val &= and; |
60902a2c | 136 | edma_write(ctlr, offset, val); |
a4768d22 | 137 | } |
60902a2c | 138 | static inline void edma_or(unsigned ctlr, int offset, unsigned or) |
a4768d22 | 139 | { |
60902a2c | 140 | unsigned val = edma_read(ctlr, offset); |
a4768d22 | 141 | val |= or; |
60902a2c | 142 | edma_write(ctlr, offset, val); |
a4768d22 | 143 | } |
60902a2c | 144 | static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i) |
a4768d22 | 145 | { |
60902a2c | 146 | return edma_read(ctlr, offset + (i << 2)); |
a4768d22 | 147 | } |
60902a2c SR |
148 | static inline void edma_write_array(unsigned ctlr, int offset, int i, |
149 | unsigned val) | |
a4768d22 | 150 | { |
60902a2c | 151 | edma_write(ctlr, offset + (i << 2), val); |
a4768d22 | 152 | } |
60902a2c | 153 | static inline void edma_modify_array(unsigned ctlr, int offset, int i, |
a4768d22 KH |
154 | unsigned and, unsigned or) |
155 | { | |
60902a2c | 156 | edma_modify(ctlr, offset + (i << 2), and, or); |
a4768d22 | 157 | } |
60902a2c | 158 | static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or) |
a4768d22 | 159 | { |
60902a2c | 160 | edma_or(ctlr, offset + (i << 2), or); |
a4768d22 | 161 | } |
60902a2c SR |
162 | static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j, |
163 | unsigned or) | |
a4768d22 | 164 | { |
60902a2c | 165 | edma_or(ctlr, offset + ((i*2 + j) << 2), or); |
a4768d22 | 166 | } |
60902a2c SR |
167 | static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j, |
168 | unsigned val) | |
a4768d22 | 169 | { |
60902a2c | 170 | edma_write(ctlr, offset + ((i*2 + j) << 2), val); |
a4768d22 | 171 | } |
60902a2c | 172 | static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset) |
a4768d22 | 173 | { |
60902a2c | 174 | return edma_read(ctlr, EDMA_SHADOW0 + offset); |
a4768d22 | 175 | } |
60902a2c SR |
176 | static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset, |
177 | int i) | |
a4768d22 | 178 | { |
60902a2c | 179 | return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); |
a4768d22 | 180 | } |
60902a2c | 181 | static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val) |
a4768d22 | 182 | { |
60902a2c | 183 | edma_write(ctlr, EDMA_SHADOW0 + offset, val); |
a4768d22 | 184 | } |
60902a2c SR |
185 | static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, |
186 | unsigned val) | |
a4768d22 | 187 | { |
60902a2c | 188 | edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); |
a4768d22 | 189 | } |
60902a2c SR |
190 | static inline unsigned int edma_parm_read(unsigned ctlr, int offset, |
191 | int param_no) | |
a4768d22 | 192 | { |
60902a2c | 193 | return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); |
a4768d22 | 194 | } |
60902a2c SR |
195 | static inline void edma_parm_write(unsigned ctlr, int offset, int param_no, |
196 | unsigned val) | |
a4768d22 | 197 | { |
60902a2c | 198 | edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); |
a4768d22 | 199 | } |
60902a2c | 200 | static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no, |
a4768d22 KH |
201 | unsigned and, unsigned or) |
202 | { | |
60902a2c | 203 | edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); |
a4768d22 | 204 | } |
60902a2c SR |
205 | static inline void edma_parm_and(unsigned ctlr, int offset, int param_no, |
206 | unsigned and) | |
a4768d22 | 207 | { |
60902a2c | 208 | edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); |
a4768d22 | 209 | } |
60902a2c SR |
210 | static inline void edma_parm_or(unsigned ctlr, int offset, int param_no, |
211 | unsigned or) | |
a4768d22 | 212 | { |
60902a2c | 213 | edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); |
a4768d22 KH |
214 | } |
215 | ||
90bd4e6d RS |
216 | static inline void set_bits(int offset, int len, unsigned long *p) |
217 | { | |
218 | for (; len > 0; len--) | |
219 | set_bit(offset + (len - 1), p); | |
220 | } | |
221 | ||
222 | static inline void clear_bits(int offset, int len, unsigned long *p) | |
223 | { | |
224 | for (; len > 0; len--) | |
225 | clear_bit(offset + (len - 1), p); | |
226 | } | |
227 | ||
a4768d22 KH |
228 | /*****************************************************************************/ |
229 | ||
230 | /* actual number of DMA channels and slots on this silicon */ | |
60902a2c SR |
231 | struct edma { |
232 | /* how many dma resources of each type */ | |
233 | unsigned num_channels; | |
234 | unsigned num_region; | |
235 | unsigned num_slots; | |
236 | unsigned num_tc; | |
237 | unsigned num_cc; | |
a0f0202e | 238 | enum dma_event_q default_queue; |
60902a2c SR |
239 | |
240 | /* list of channels with no even trigger; terminated by "-1" */ | |
241 | const s8 *noevent; | |
242 | ||
243 | /* The edma_inuse bit for each PaRAM slot is clear unless the | |
244 | * channel is in use ... by ARM or DSP, for QDMA, or whatever. | |
245 | */ | |
246 | DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); | |
a4768d22 | 247 | |
f900d552 SR |
248 | /* The edma_unused bit for each channel is clear unless |
249 | * it is not being used on this platform. It uses a bit | |
250 | * of SOC-specific initialization code. | |
60902a2c | 251 | */ |
f900d552 | 252 | DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH); |
a4768d22 | 253 | |
60902a2c SR |
254 | unsigned irq_res_start; |
255 | unsigned irq_res_end; | |
a4768d22 | 256 | |
60902a2c SR |
257 | struct dma_interrupt_data { |
258 | void (*callback)(unsigned channel, unsigned short ch_status, | |
259 | void *data); | |
260 | void *data; | |
261 | } intr_data[EDMA_MAX_DMACH]; | |
262 | }; | |
263 | ||
3f68b98a | 264 | static struct edma *edma_cc[EDMA_MAX_CC]; |
2d517508 | 265 | static int arch_num_cc; |
a4768d22 KH |
266 | |
267 | /* dummy param set used to (re)initialize parameter RAM slots */ | |
268 | static const struct edmacc_param dummy_paramset = { | |
269 | .link_bcntrld = 0xffff, | |
270 | .ccnt = 1, | |
271 | }; | |
272 | ||
a4768d22 KH |
273 | /*****************************************************************************/ |
274 | ||
60902a2c SR |
275 | static void map_dmach_queue(unsigned ctlr, unsigned ch_no, |
276 | enum dma_event_q queue_no) | |
a4768d22 KH |
277 | { |
278 | int bit = (ch_no & 0x7) * 4; | |
279 | ||
280 | /* default to low priority queue */ | |
281 | if (queue_no == EVENTQ_DEFAULT) | |
3f68b98a | 282 | queue_no = edma_cc[ctlr]->default_queue; |
a4768d22 KH |
283 | |
284 | queue_no &= 7; | |
60902a2c | 285 | edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), |
a4768d22 KH |
286 | ~(0x7 << bit), queue_no << bit); |
287 | } | |
288 | ||
60902a2c | 289 | static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no) |
a4768d22 KH |
290 | { |
291 | int bit = queue_no * 4; | |
60902a2c | 292 | edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); |
a4768d22 KH |
293 | } |
294 | ||
60902a2c SR |
295 | static void __init assign_priority_to_queue(unsigned ctlr, int queue_no, |
296 | int priority) | |
a4768d22 KH |
297 | { |
298 | int bit = queue_no * 4; | |
60902a2c SR |
299 | edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), |
300 | ((priority & 0x7) << bit)); | |
301 | } | |
302 | ||
303 | /** | |
304 | * map_dmach_param - Maps channel number to param entry number | |
305 | * | |
306 | * This maps the dma channel number to param entry numberter. In | |
307 | * other words using the DMA channel mapping registers a param entry | |
308 | * can be mapped to any channel | |
309 | * | |
310 | * Callers are responsible for ensuring the channel mapping logic is | |
311 | * included in that particular EDMA variant (Eg : dm646x) | |
312 | * | |
313 | */ | |
314 | static void __init map_dmach_param(unsigned ctlr) | |
315 | { | |
316 | int i; | |
317 | for (i = 0; i < EDMA_MAX_DMACH; i++) | |
318 | edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); | |
a4768d22 KH |
319 | } |
320 | ||
321 | static inline void | |
322 | setup_dma_interrupt(unsigned lch, | |
323 | void (*callback)(unsigned channel, u16 ch_status, void *data), | |
324 | void *data) | |
325 | { | |
60902a2c SR |
326 | unsigned ctlr; |
327 | ||
328 | ctlr = EDMA_CTLR(lch); | |
329 | lch = EDMA_CHAN_SLOT(lch); | |
330 | ||
243bc654 | 331 | if (!callback) |
60902a2c | 332 | edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, |
d78a9494 | 333 | BIT(lch & 0x1f)); |
a4768d22 | 334 | |
3f68b98a SN |
335 | edma_cc[ctlr]->intr_data[lch].callback = callback; |
336 | edma_cc[ctlr]->intr_data[lch].data = data; | |
a4768d22 KH |
337 | |
338 | if (callback) { | |
60902a2c | 339 | edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, |
d78a9494 | 340 | BIT(lch & 0x1f)); |
60902a2c | 341 | edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, |
d78a9494 | 342 | BIT(lch & 0x1f)); |
a4768d22 KH |
343 | } |
344 | } | |
345 | ||
60902a2c SR |
346 | static int irq2ctlr(int irq) |
347 | { | |
3f68b98a | 348 | if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end) |
60902a2c | 349 | return 0; |
3f68b98a SN |
350 | else if (irq >= edma_cc[1]->irq_res_start && |
351 | irq <= edma_cc[1]->irq_res_end) | |
60902a2c SR |
352 | return 1; |
353 | ||
354 | return -1; | |
355 | } | |
356 | ||
a4768d22 KH |
357 | /****************************************************************************** |
358 | * | |
359 | * DMA interrupt handler | |
360 | * | |
361 | *****************************************************************************/ | |
362 | static irqreturn_t dma_irq_handler(int irq, void *data) | |
363 | { | |
93fe23d8 | 364 | int ctlr; |
bcd59b0f SAS |
365 | u32 sh_ier; |
366 | u32 sh_ipr; | |
367 | u32 bank; | |
a4768d22 | 368 | |
60902a2c | 369 | ctlr = irq2ctlr(irq); |
93fe23d8 KV |
370 | if (ctlr < 0) |
371 | return IRQ_NONE; | |
60902a2c | 372 | |
a4768d22 KH |
373 | dev_dbg(data, "dma_irq_handler\n"); |
374 | ||
bcd59b0f SAS |
375 | sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0); |
376 | if (!sh_ipr) { | |
377 | sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1); | |
378 | if (!sh_ipr) | |
379 | return IRQ_NONE; | |
380 | sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1); | |
381 | bank = 1; | |
382 | } else { | |
383 | sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0); | |
384 | bank = 0; | |
385 | } | |
386 | ||
387 | do { | |
388 | u32 slot; | |
389 | u32 channel; | |
a4768d22 | 390 | |
bcd59b0f SAS |
391 | dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr); |
392 | ||
393 | slot = __ffs(sh_ipr); | |
394 | sh_ipr &= ~(BIT(slot)); | |
395 | ||
396 | if (sh_ier & BIT(slot)) { | |
397 | channel = (bank << 5) | slot; | |
398 | /* Clear the corresponding IPR bits */ | |
399 | edma_shadow0_write_array(ctlr, SH_ICR, bank, | |
400 | BIT(slot)); | |
401 | if (edma_cc[ctlr]->intr_data[channel].callback) | |
402 | edma_cc[ctlr]->intr_data[channel].callback( | |
403 | channel, DMA_COMPLETE, | |
404 | edma_cc[ctlr]->intr_data[channel].data); | |
a4768d22 | 405 | } |
bcd59b0f SAS |
406 | } while (sh_ipr); |
407 | ||
60902a2c | 408 | edma_shadow0_write(ctlr, SH_IEVAL, 1); |
a4768d22 KH |
409 | return IRQ_HANDLED; |
410 | } | |
411 | ||
412 | /****************************************************************************** | |
413 | * | |
414 | * DMA error interrupt handler | |
415 | * | |
416 | *****************************************************************************/ | |
417 | static irqreturn_t dma_ccerr_handler(int irq, void *data) | |
418 | { | |
419 | int i; | |
93fe23d8 | 420 | int ctlr; |
a4768d22 KH |
421 | unsigned int cnt = 0; |
422 | ||
60902a2c | 423 | ctlr = irq2ctlr(irq); |
93fe23d8 KV |
424 | if (ctlr < 0) |
425 | return IRQ_NONE; | |
60902a2c | 426 | |
a4768d22 KH |
427 | dev_dbg(data, "dma_ccerr_handler\n"); |
428 | ||
60902a2c SR |
429 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && |
430 | (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && | |
431 | (edma_read(ctlr, EDMA_QEMR) == 0) && | |
432 | (edma_read(ctlr, EDMA_CCERR) == 0)) | |
a4768d22 KH |
433 | return IRQ_NONE; |
434 | ||
435 | while (1) { | |
436 | int j = -1; | |
60902a2c | 437 | if (edma_read_array(ctlr, EDMA_EMR, 0)) |
a4768d22 | 438 | j = 0; |
60902a2c | 439 | else if (edma_read_array(ctlr, EDMA_EMR, 1)) |
a4768d22 KH |
440 | j = 1; |
441 | if (j >= 0) { | |
442 | dev_dbg(data, "EMR%d %08x\n", j, | |
60902a2c | 443 | edma_read_array(ctlr, EDMA_EMR, j)); |
a4768d22 KH |
444 | for (i = 0; i < 32; i++) { |
445 | int k = (j << 5) + i; | |
60902a2c | 446 | if (edma_read_array(ctlr, EDMA_EMR, j) & |
d78a9494 | 447 | BIT(i)) { |
a4768d22 | 448 | /* Clear the corresponding EMR bits */ |
60902a2c | 449 | edma_write_array(ctlr, EDMA_EMCR, j, |
d78a9494 | 450 | BIT(i)); |
a4768d22 | 451 | /* Clear any SER */ |
60902a2c | 452 | edma_shadow0_write_array(ctlr, SH_SECR, |
d78a9494 | 453 | j, BIT(i)); |
3f68b98a | 454 | if (edma_cc[ctlr]->intr_data[k]. |
60902a2c | 455 | callback) { |
3f68b98a | 456 | edma_cc[ctlr]->intr_data[k]. |
60902a2c SR |
457 | callback(k, |
458 | DMA_CC_ERROR, | |
3f68b98a | 459 | edma_cc[ctlr]->intr_data |
60902a2c | 460 | [k].data); |
a4768d22 KH |
461 | } |
462 | } | |
463 | } | |
60902a2c | 464 | } else if (edma_read(ctlr, EDMA_QEMR)) { |
a4768d22 | 465 | dev_dbg(data, "QEMR %02x\n", |
60902a2c | 466 | edma_read(ctlr, EDMA_QEMR)); |
a4768d22 | 467 | for (i = 0; i < 8; i++) { |
d78a9494 | 468 | if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { |
a4768d22 | 469 | /* Clear the corresponding IPR bits */ |
d78a9494 | 470 | edma_write(ctlr, EDMA_QEMCR, BIT(i)); |
60902a2c | 471 | edma_shadow0_write(ctlr, SH_QSECR, |
d78a9494 | 472 | BIT(i)); |
a4768d22 KH |
473 | |
474 | /* NOTE: not reported!! */ | |
475 | } | |
476 | } | |
60902a2c | 477 | } else if (edma_read(ctlr, EDMA_CCERR)) { |
a4768d22 | 478 | dev_dbg(data, "CCERR %08x\n", |
60902a2c | 479 | edma_read(ctlr, EDMA_CCERR)); |
a4768d22 KH |
480 | /* FIXME: CCERR.BIT(16) ignored! much better |
481 | * to just write CCERRCLR with CCERR value... | |
482 | */ | |
483 | for (i = 0; i < 8; i++) { | |
d78a9494 | 484 | if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) { |
a4768d22 | 485 | /* Clear the corresponding IPR bits */ |
d78a9494 | 486 | edma_write(ctlr, EDMA_CCERRCLR, BIT(i)); |
a4768d22 KH |
487 | |
488 | /* NOTE: not reported!! */ | |
489 | } | |
490 | } | |
491 | } | |
a6374f53 SN |
492 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && |
493 | (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && | |
494 | (edma_read(ctlr, EDMA_QEMR) == 0) && | |
495 | (edma_read(ctlr, EDMA_CCERR) == 0)) | |
a4768d22 | 496 | break; |
a4768d22 KH |
497 | cnt++; |
498 | if (cnt > 10) | |
499 | break; | |
500 | } | |
60902a2c | 501 | edma_write(ctlr, EDMA_EEVAL, 1); |
a4768d22 KH |
502 | return IRQ_HANDLED; |
503 | } | |
504 | ||
134ce221 SP |
505 | static int reserve_contiguous_slots(int ctlr, unsigned int id, |
506 | unsigned int num_slots, | |
507 | unsigned int start_slot) | |
213765d7 SP |
508 | { |
509 | int i, j; | |
134ce221 SP |
510 | unsigned int count = num_slots; |
511 | int stop_slot = start_slot; | |
cc93fc3f | 512 | DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); |
213765d7 | 513 | |
3f68b98a | 514 | for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) { |
213765d7 | 515 | j = EDMA_CHAN_SLOT(i); |
3f68b98a | 516 | if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) { |
cc93fc3f | 517 | /* Record our current beginning slot */ |
134ce221 SP |
518 | if (count == num_slots) |
519 | stop_slot = i; | |
cc93fc3f | 520 | |
213765d7 | 521 | count--; |
cc93fc3f SP |
522 | set_bit(j, tmp_inuse); |
523 | ||
213765d7 SP |
524 | if (count == 0) |
525 | break; | |
cc93fc3f SP |
526 | } else { |
527 | clear_bit(j, tmp_inuse); | |
528 | ||
529 | if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { | |
134ce221 | 530 | stop_slot = i; |
cc93fc3f | 531 | break; |
243bc654 | 532 | } else { |
134ce221 | 533 | count = num_slots; |
243bc654 | 534 | } |
cc93fc3f | 535 | } |
213765d7 SP |
536 | } |
537 | ||
538 | /* | |
539 | * We have to clear any bits that we set | |
134ce221 SP |
540 | * if we run out parameter RAM slots, i.e we do find a set |
541 | * of contiguous parameter RAM slots but do not find the exact number | |
542 | * requested as we may reach the total number of parameter RAM slots | |
213765d7 | 543 | */ |
3f68b98a | 544 | if (i == edma_cc[ctlr]->num_slots) |
134ce221 | 545 | stop_slot = i; |
cc93fc3f | 546 | |
98e3b339 AM |
547 | j = start_slot; |
548 | for_each_set_bit_from(j, tmp_inuse, stop_slot) | |
549 | clear_bit(j, edma_cc[ctlr]->edma_inuse); | |
213765d7 | 550 | |
cc93fc3f | 551 | if (count) |
213765d7 | 552 | return -EBUSY; |
213765d7 | 553 | |
134ce221 | 554 | for (j = i - num_slots + 1; j <= i; ++j) |
213765d7 SP |
555 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j), |
556 | &dummy_paramset, PARM_SIZE); | |
557 | ||
134ce221 | 558 | return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1); |
213765d7 SP |
559 | } |
560 | ||
f900d552 SR |
561 | static int prepare_unused_channel_list(struct device *dev, void *data) |
562 | { | |
563 | struct platform_device *pdev = to_platform_device(dev); | |
564 | int i, ctlr; | |
565 | ||
566 | for (i = 0; i < pdev->num_resources; i++) { | |
567 | if ((pdev->resource[i].flags & IORESOURCE_DMA) && | |
568 | (int)pdev->resource[i].start >= 0) { | |
569 | ctlr = EDMA_CTLR(pdev->resource[i].start); | |
570 | clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), | |
3f68b98a | 571 | edma_cc[ctlr]->edma_unused); |
f900d552 SR |
572 | } |
573 | } | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
a4768d22 KH |
578 | /*-----------------------------------------------------------------------*/ |
579 | ||
f900d552 SR |
580 | static bool unused_chan_list_done; |
581 | ||
a4768d22 KH |
582 | /* Resource alloc/free: dma channels, parameter RAM slots */ |
583 | ||
584 | /** | |
585 | * edma_alloc_channel - allocate DMA channel and paired parameter RAM | |
586 | * @channel: specific channel to allocate; negative for "any unmapped channel" | |
587 | * @callback: optional; to be issued on DMA completion or errors | |
588 | * @data: passed to callback | |
589 | * @eventq_no: an EVENTQ_* constant, used to choose which Transfer | |
590 | * Controller (TC) executes requests using this channel. Use | |
591 | * EVENTQ_DEFAULT unless you really need a high priority queue. | |
592 | * | |
593 | * This allocates a DMA channel and its associated parameter RAM slot. | |
594 | * The parameter RAM is initialized to hold a dummy transfer. | |
595 | * | |
596 | * Normal use is to pass a specific channel number as @channel, to make | |
597 | * use of hardware events mapped to that channel. When the channel will | |
598 | * be used only for software triggering or event chaining, channels not | |
599 | * mapped to hardware events (or mapped to unused events) are preferable. | |
600 | * | |
601 | * DMA transfers start from a channel using edma_start(), or by | |
602 | * chaining. When the transfer described in that channel's parameter RAM | |
603 | * slot completes, that slot's data may be reloaded through a link. | |
604 | * | |
605 | * DMA errors are only reported to the @callback associated with the | |
606 | * channel driving that transfer, but transfer completion callbacks can | |
607 | * be sent to another channel under control of the TCC field in | |
608 | * the option word of the transfer's parameter RAM set. Drivers must not | |
609 | * use DMA transfer completion callbacks for channels they did not allocate. | |
610 | * (The same applies to TCC codes used in transfer chaining.) | |
611 | * | |
612 | * Returns the number of the channel, else negative errno. | |
613 | */ | |
614 | int edma_alloc_channel(int channel, | |
615 | void (*callback)(unsigned channel, u16 ch_status, void *data), | |
616 | void *data, | |
617 | enum dma_event_q eventq_no) | |
618 | { | |
447f18f1 | 619 | unsigned i, done = 0, ctlr = 0; |
f900d552 SR |
620 | int ret = 0; |
621 | ||
622 | if (!unused_chan_list_done) { | |
623 | /* | |
624 | * Scan all the platform devices to find out the EDMA channels | |
625 | * used and clear them in the unused list, making the rest | |
626 | * available for ARM usage. | |
627 | */ | |
628 | ret = bus_for_each_dev(&platform_bus_type, NULL, NULL, | |
629 | prepare_unused_channel_list); | |
630 | if (ret < 0) | |
631 | return ret; | |
632 | ||
633 | unused_chan_list_done = true; | |
634 | } | |
60902a2c SR |
635 | |
636 | if (channel >= 0) { | |
637 | ctlr = EDMA_CTLR(channel); | |
638 | channel = EDMA_CHAN_SLOT(channel); | |
639 | } | |
640 | ||
a4768d22 | 641 | if (channel < 0) { |
2d517508 | 642 | for (i = 0; i < arch_num_cc; i++) { |
60902a2c SR |
643 | channel = 0; |
644 | for (;;) { | |
3f68b98a SN |
645 | channel = find_next_bit(edma_cc[i]->edma_unused, |
646 | edma_cc[i]->num_channels, | |
60902a2c | 647 | channel); |
3f68b98a | 648 | if (channel == edma_cc[i]->num_channels) |
447f18f1 | 649 | break; |
60902a2c | 650 | if (!test_and_set_bit(channel, |
3f68b98a | 651 | edma_cc[i]->edma_inuse)) { |
60902a2c SR |
652 | done = 1; |
653 | ctlr = i; | |
654 | break; | |
655 | } | |
656 | channel++; | |
657 | } | |
658 | if (done) | |
a4768d22 | 659 | break; |
a4768d22 | 660 | } |
447f18f1 SR |
661 | if (!done) |
662 | return -ENOMEM; | |
3f68b98a | 663 | } else if (channel >= edma_cc[ctlr]->num_channels) { |
a4768d22 | 664 | return -EINVAL; |
3f68b98a | 665 | } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) { |
a4768d22 KH |
666 | return -EBUSY; |
667 | } | |
668 | ||
669 | /* ensure access through shadow region 0 */ | |
d78a9494 | 670 | edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); |
a4768d22 KH |
671 | |
672 | /* ensure no events are pending */ | |
60902a2c SR |
673 | edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); |
674 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), | |
a4768d22 KH |
675 | &dummy_paramset, PARM_SIZE); |
676 | ||
677 | if (callback) | |
60902a2c SR |
678 | setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), |
679 | callback, data); | |
a4768d22 | 680 | |
60902a2c | 681 | map_dmach_queue(ctlr, channel, eventq_no); |
a4768d22 | 682 | |
0e6cb8d2 | 683 | return EDMA_CTLR_CHAN(ctlr, channel); |
a4768d22 KH |
684 | } |
685 | EXPORT_SYMBOL(edma_alloc_channel); | |
686 | ||
687 | ||
688 | /** | |
689 | * edma_free_channel - deallocate DMA channel | |
690 | * @channel: dma channel returned from edma_alloc_channel() | |
691 | * | |
692 | * This deallocates the DMA channel and associated parameter RAM slot | |
693 | * allocated by edma_alloc_channel(). | |
694 | * | |
695 | * Callers are responsible for ensuring the channel is inactive, and | |
696 | * will not be reactivated by linking, chaining, or software calls to | |
697 | * edma_start(). | |
698 | */ | |
699 | void edma_free_channel(unsigned channel) | |
700 | { | |
60902a2c SR |
701 | unsigned ctlr; |
702 | ||
703 | ctlr = EDMA_CTLR(channel); | |
704 | channel = EDMA_CHAN_SLOT(channel); | |
705 | ||
3f68b98a | 706 | if (channel >= edma_cc[ctlr]->num_channels) |
a4768d22 KH |
707 | return; |
708 | ||
709 | setup_dma_interrupt(channel, NULL, NULL); | |
710 | /* REVISIT should probably take out of shadow region 0 */ | |
711 | ||
60902a2c | 712 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), |
a4768d22 | 713 | &dummy_paramset, PARM_SIZE); |
3f68b98a | 714 | clear_bit(channel, edma_cc[ctlr]->edma_inuse); |
a4768d22 KH |
715 | } |
716 | EXPORT_SYMBOL(edma_free_channel); | |
717 | ||
718 | /** | |
719 | * edma_alloc_slot - allocate DMA parameter RAM | |
720 | * @slot: specific slot to allocate; negative for "any unused slot" | |
721 | * | |
722 | * This allocates a parameter RAM slot, initializing it to hold a | |
723 | * dummy transfer. Slots allocated using this routine have not been | |
724 | * mapped to a hardware DMA channel, and will normally be used by | |
725 | * linking to them from a slot associated with a DMA channel. | |
726 | * | |
727 | * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific | |
728 | * slots may be allocated on behalf of DSP firmware. | |
729 | * | |
730 | * Returns the number of the slot, else negative errno. | |
731 | */ | |
60902a2c | 732 | int edma_alloc_slot(unsigned ctlr, int slot) |
a4768d22 | 733 | { |
06955277 MP |
734 | if (!edma_cc[ctlr]) |
735 | return -EINVAL; | |
736 | ||
60902a2c SR |
737 | if (slot >= 0) |
738 | slot = EDMA_CHAN_SLOT(slot); | |
739 | ||
a4768d22 | 740 | if (slot < 0) { |
3f68b98a | 741 | slot = edma_cc[ctlr]->num_channels; |
a4768d22 | 742 | for (;;) { |
3f68b98a SN |
743 | slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse, |
744 | edma_cc[ctlr]->num_slots, slot); | |
745 | if (slot == edma_cc[ctlr]->num_slots) | |
a4768d22 | 746 | return -ENOMEM; |
3f68b98a | 747 | if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) |
a4768d22 KH |
748 | break; |
749 | } | |
3f68b98a SN |
750 | } else if (slot < edma_cc[ctlr]->num_channels || |
751 | slot >= edma_cc[ctlr]->num_slots) { | |
a4768d22 | 752 | return -EINVAL; |
3f68b98a | 753 | } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) { |
a4768d22 KH |
754 | return -EBUSY; |
755 | } | |
756 | ||
60902a2c | 757 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
a4768d22 KH |
758 | &dummy_paramset, PARM_SIZE); |
759 | ||
60902a2c | 760 | return EDMA_CTLR_CHAN(ctlr, slot); |
a4768d22 KH |
761 | } |
762 | EXPORT_SYMBOL(edma_alloc_slot); | |
763 | ||
764 | /** | |
765 | * edma_free_slot - deallocate DMA parameter RAM | |
766 | * @slot: parameter RAM slot returned from edma_alloc_slot() | |
767 | * | |
768 | * This deallocates the parameter RAM slot allocated by edma_alloc_slot(). | |
769 | * Callers are responsible for ensuring the slot is inactive, and will | |
770 | * not be activated. | |
771 | */ | |
772 | void edma_free_slot(unsigned slot) | |
773 | { | |
60902a2c SR |
774 | unsigned ctlr; |
775 | ||
776 | ctlr = EDMA_CTLR(slot); | |
777 | slot = EDMA_CHAN_SLOT(slot); | |
778 | ||
3f68b98a SN |
779 | if (slot < edma_cc[ctlr]->num_channels || |
780 | slot >= edma_cc[ctlr]->num_slots) | |
a4768d22 KH |
781 | return; |
782 | ||
60902a2c | 783 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
a4768d22 | 784 | &dummy_paramset, PARM_SIZE); |
3f68b98a | 785 | clear_bit(slot, edma_cc[ctlr]->edma_inuse); |
a4768d22 KH |
786 | } |
787 | EXPORT_SYMBOL(edma_free_slot); | |
788 | ||
213765d7 SP |
789 | |
790 | /** | |
791 | * edma_alloc_cont_slots- alloc contiguous parameter RAM slots | |
792 | * The API will return the starting point of a set of | |
134ce221 | 793 | * contiguous parameter RAM slots that have been requested |
213765d7 SP |
794 | * |
795 | * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT | |
796 | * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT | |
134ce221 SP |
797 | * @count: number of contiguous Paramter RAM slots |
798 | * @slot - the start value of Parameter RAM slot that should be passed if id | |
213765d7 SP |
799 | * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT |
800 | * | |
801 | * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of | |
134ce221 SP |
802 | * contiguous Parameter RAM slots from parameter RAM 64 in the case of |
803 | * DaVinci SOCs and 32 in the case of DA8xx SOCs. | |
213765d7 SP |
804 | * |
805 | * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a | |
134ce221 | 806 | * set of contiguous parameter RAM slots from the "slot" that is passed as an |
213765d7 SP |
807 | * argument to the API. |
808 | * | |
809 | * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries | |
134ce221 | 810 | * starts looking for a set of contiguous parameter RAMs from the "slot" |
213765d7 | 811 | * that is passed as an argument to the API. On failure the API will try to |
134ce221 SP |
812 | * find a set of contiguous Parameter RAM slots from the remaining Parameter |
813 | * RAM slots | |
213765d7 SP |
814 | */ |
815 | int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) | |
816 | { | |
817 | /* | |
818 | * The start slot requested should be greater than | |
819 | * the number of channels and lesser than the total number | |
820 | * of slots | |
821 | */ | |
6b0cf4e9 | 822 | if ((id != EDMA_CONT_PARAMS_ANY) && |
3f68b98a SN |
823 | (slot < edma_cc[ctlr]->num_channels || |
824 | slot >= edma_cc[ctlr]->num_slots)) | |
213765d7 SP |
825 | return -EINVAL; |
826 | ||
827 | /* | |
134ce221 | 828 | * The number of parameter RAM slots requested cannot be less than 1 |
213765d7 SP |
829 | * and cannot be more than the number of slots minus the number of |
830 | * channels | |
831 | */ | |
832 | if (count < 1 || count > | |
3f68b98a | 833 | (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels)) |
213765d7 SP |
834 | return -EINVAL; |
835 | ||
836 | switch (id) { | |
837 | case EDMA_CONT_PARAMS_ANY: | |
134ce221 | 838 | return reserve_contiguous_slots(ctlr, id, count, |
3f68b98a | 839 | edma_cc[ctlr]->num_channels); |
213765d7 SP |
840 | case EDMA_CONT_PARAMS_FIXED_EXACT: |
841 | case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: | |
134ce221 | 842 | return reserve_contiguous_slots(ctlr, id, count, slot); |
213765d7 SP |
843 | default: |
844 | return -EINVAL; | |
845 | } | |
846 | ||
847 | } | |
848 | EXPORT_SYMBOL(edma_alloc_cont_slots); | |
849 | ||
850 | /** | |
134ce221 SP |
851 | * edma_free_cont_slots - deallocate DMA parameter RAM slots |
852 | * @slot: first parameter RAM of a set of parameter RAM slots to be freed | |
853 | * @count: the number of contiguous parameter RAM slots to be freed | |
213765d7 SP |
854 | * |
855 | * This deallocates the parameter RAM slots allocated by | |
856 | * edma_alloc_cont_slots. | |
857 | * Callers/applications need to keep track of sets of contiguous | |
134ce221 | 858 | * parameter RAM slots that have been allocated using the edma_alloc_cont_slots |
213765d7 SP |
859 | * API. |
860 | * Callers are responsible for ensuring the slots are inactive, and will | |
861 | * not be activated. | |
862 | */ | |
863 | int edma_free_cont_slots(unsigned slot, int count) | |
864 | { | |
51c99e04 | 865 | unsigned ctlr, slot_to_free; |
213765d7 SP |
866 | int i; |
867 | ||
868 | ctlr = EDMA_CTLR(slot); | |
869 | slot = EDMA_CHAN_SLOT(slot); | |
870 | ||
3f68b98a SN |
871 | if (slot < edma_cc[ctlr]->num_channels || |
872 | slot >= edma_cc[ctlr]->num_slots || | |
213765d7 SP |
873 | count < 1) |
874 | return -EINVAL; | |
875 | ||
876 | for (i = slot; i < slot + count; ++i) { | |
877 | ctlr = EDMA_CTLR(i); | |
51c99e04 | 878 | slot_to_free = EDMA_CHAN_SLOT(i); |
213765d7 | 879 | |
51c99e04 | 880 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free), |
213765d7 | 881 | &dummy_paramset, PARM_SIZE); |
3f68b98a | 882 | clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse); |
213765d7 SP |
883 | } |
884 | ||
885 | return 0; | |
886 | } | |
887 | EXPORT_SYMBOL(edma_free_cont_slots); | |
888 | ||
a4768d22 KH |
889 | /*-----------------------------------------------------------------------*/ |
890 | ||
891 | /* Parameter RAM operations (i) -- read/write partial slots */ | |
892 | ||
893 | /** | |
894 | * edma_set_src - set initial DMA source address in parameter RAM slot | |
895 | * @slot: parameter RAM slot being configured | |
896 | * @src_port: physical address of source (memory, controller FIFO, etc) | |
897 | * @addressMode: INCR, except in very rare cases | |
898 | * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the | |
899 | * width to use when addressing the fifo (e.g. W8BIT, W32BIT) | |
900 | * | |
901 | * Note that the source address is modified during the DMA transfer | |
902 | * according to edma_set_src_index(). | |
903 | */ | |
904 | void edma_set_src(unsigned slot, dma_addr_t src_port, | |
905 | enum address_mode mode, enum fifo_width width) | |
906 | { | |
60902a2c SR |
907 | unsigned ctlr; |
908 | ||
909 | ctlr = EDMA_CTLR(slot); | |
910 | slot = EDMA_CHAN_SLOT(slot); | |
911 | ||
3f68b98a | 912 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 913 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); |
a4768d22 KH |
914 | |
915 | if (mode) { | |
916 | /* set SAM and program FWID */ | |
917 | i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8)); | |
918 | } else { | |
919 | /* clear SAM */ | |
920 | i &= ~SAM; | |
921 | } | |
60902a2c | 922 | edma_parm_write(ctlr, PARM_OPT, slot, i); |
a4768d22 KH |
923 | |
924 | /* set the source port address | |
925 | in source register of param structure */ | |
60902a2c | 926 | edma_parm_write(ctlr, PARM_SRC, slot, src_port); |
a4768d22 KH |
927 | } |
928 | } | |
929 | EXPORT_SYMBOL(edma_set_src); | |
930 | ||
931 | /** | |
932 | * edma_set_dest - set initial DMA destination address in parameter RAM slot | |
933 | * @slot: parameter RAM slot being configured | |
934 | * @dest_port: physical address of destination (memory, controller FIFO, etc) | |
935 | * @addressMode: INCR, except in very rare cases | |
936 | * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the | |
937 | * width to use when addressing the fifo (e.g. W8BIT, W32BIT) | |
938 | * | |
939 | * Note that the destination address is modified during the DMA transfer | |
940 | * according to edma_set_dest_index(). | |
941 | */ | |
942 | void edma_set_dest(unsigned slot, dma_addr_t dest_port, | |
943 | enum address_mode mode, enum fifo_width width) | |
944 | { | |
60902a2c SR |
945 | unsigned ctlr; |
946 | ||
947 | ctlr = EDMA_CTLR(slot); | |
948 | slot = EDMA_CHAN_SLOT(slot); | |
949 | ||
3f68b98a | 950 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 951 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); |
a4768d22 KH |
952 | |
953 | if (mode) { | |
954 | /* set DAM and program FWID */ | |
955 | i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8)); | |
956 | } else { | |
957 | /* clear DAM */ | |
958 | i &= ~DAM; | |
959 | } | |
60902a2c | 960 | edma_parm_write(ctlr, PARM_OPT, slot, i); |
a4768d22 KH |
961 | /* set the destination port address |
962 | in dest register of param structure */ | |
60902a2c | 963 | edma_parm_write(ctlr, PARM_DST, slot, dest_port); |
a4768d22 KH |
964 | } |
965 | } | |
966 | EXPORT_SYMBOL(edma_set_dest); | |
967 | ||
968 | /** | |
969 | * edma_get_position - returns the current transfer points | |
970 | * @slot: parameter RAM slot being examined | |
971 | * @src: pointer to source port position | |
972 | * @dst: pointer to destination port position | |
973 | * | |
974 | * Returns current source and destination addresses for a particular | |
975 | * parameter RAM slot. Its channel should not be active when this is called. | |
976 | */ | |
977 | void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst) | |
978 | { | |
979 | struct edmacc_param temp; | |
60902a2c SR |
980 | unsigned ctlr; |
981 | ||
982 | ctlr = EDMA_CTLR(slot); | |
983 | slot = EDMA_CHAN_SLOT(slot); | |
a4768d22 | 984 | |
60902a2c | 985 | edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp); |
a4768d22 KH |
986 | if (src != NULL) |
987 | *src = temp.src; | |
988 | if (dst != NULL) | |
989 | *dst = temp.dst; | |
990 | } | |
991 | EXPORT_SYMBOL(edma_get_position); | |
992 | ||
993 | /** | |
994 | * edma_set_src_index - configure DMA source address indexing | |
995 | * @slot: parameter RAM slot being configured | |
996 | * @src_bidx: byte offset between source arrays in a frame | |
997 | * @src_cidx: byte offset between source frames in a block | |
998 | * | |
999 | * Offsets are specified to support either contiguous or discontiguous | |
1000 | * memory transfers, or repeated access to a hardware register, as needed. | |
1001 | * When accessing hardware registers, both offsets are normally zero. | |
1002 | */ | |
1003 | void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx) | |
1004 | { | |
60902a2c SR |
1005 | unsigned ctlr; |
1006 | ||
1007 | ctlr = EDMA_CTLR(slot); | |
1008 | slot = EDMA_CHAN_SLOT(slot); | |
1009 | ||
3f68b98a | 1010 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 1011 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, |
a4768d22 | 1012 | 0xffff0000, src_bidx); |
60902a2c | 1013 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
a4768d22 KH |
1014 | 0xffff0000, src_cidx); |
1015 | } | |
1016 | } | |
1017 | EXPORT_SYMBOL(edma_set_src_index); | |
1018 | ||
1019 | /** | |
1020 | * edma_set_dest_index - configure DMA destination address indexing | |
1021 | * @slot: parameter RAM slot being configured | |
1022 | * @dest_bidx: byte offset between destination arrays in a frame | |
1023 | * @dest_cidx: byte offset between destination frames in a block | |
1024 | * | |
1025 | * Offsets are specified to support either contiguous or discontiguous | |
1026 | * memory transfers, or repeated access to a hardware register, as needed. | |
1027 | * When accessing hardware registers, both offsets are normally zero. | |
1028 | */ | |
1029 | void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx) | |
1030 | { | |
60902a2c SR |
1031 | unsigned ctlr; |
1032 | ||
1033 | ctlr = EDMA_CTLR(slot); | |
1034 | slot = EDMA_CHAN_SLOT(slot); | |
1035 | ||
3f68b98a | 1036 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 1037 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, |
a4768d22 | 1038 | 0x0000ffff, dest_bidx << 16); |
60902a2c | 1039 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
a4768d22 KH |
1040 | 0x0000ffff, dest_cidx << 16); |
1041 | } | |
1042 | } | |
1043 | EXPORT_SYMBOL(edma_set_dest_index); | |
1044 | ||
1045 | /** | |
1046 | * edma_set_transfer_params - configure DMA transfer parameters | |
1047 | * @slot: parameter RAM slot being configured | |
1048 | * @acnt: how many bytes per array (at least one) | |
1049 | * @bcnt: how many arrays per frame (at least one) | |
1050 | * @ccnt: how many frames per block (at least one) | |
1051 | * @bcnt_rld: used only for A-Synchronized transfers; this specifies | |
1052 | * the value to reload into bcnt when it decrements to zero | |
1053 | * @sync_mode: ASYNC or ABSYNC | |
1054 | * | |
1055 | * See the EDMA3 documentation to understand how to configure and link | |
1056 | * transfers using the fields in PaRAM slots. If you are not doing it | |
1057 | * all at once with edma_write_slot(), you will use this routine | |
1058 | * plus two calls each for source and destination, setting the initial | |
1059 | * address and saying how to index that address. | |
1060 | * | |
1061 | * An example of an A-Synchronized transfer is a serial link using a | |
1062 | * single word shift register. In that case, @acnt would be equal to | |
1063 | * that word size; the serial controller issues a DMA synchronization | |
1064 | * event to transfer each word, and memory access by the DMA transfer | |
1065 | * controller will be word-at-a-time. | |
1066 | * | |
1067 | * An example of an AB-Synchronized transfer is a device using a FIFO. | |
1068 | * In that case, @acnt equals the FIFO width and @bcnt equals its depth. | |
1069 | * The controller with the FIFO issues DMA synchronization events when | |
1070 | * the FIFO threshold is reached, and the DMA transfer controller will | |
1071 | * transfer one frame to (or from) the FIFO. It will probably use | |
1072 | * efficient burst modes to access memory. | |
1073 | */ | |
1074 | void edma_set_transfer_params(unsigned slot, | |
1075 | u16 acnt, u16 bcnt, u16 ccnt, | |
1076 | u16 bcnt_rld, enum sync_dimension sync_mode) | |
1077 | { | |
60902a2c SR |
1078 | unsigned ctlr; |
1079 | ||
1080 | ctlr = EDMA_CTLR(slot); | |
1081 | slot = EDMA_CHAN_SLOT(slot); | |
1082 | ||
3f68b98a | 1083 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 1084 | edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, |
a4768d22 KH |
1085 | 0x0000ffff, bcnt_rld << 16); |
1086 | if (sync_mode == ASYNC) | |
60902a2c | 1087 | edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); |
a4768d22 | 1088 | else |
60902a2c | 1089 | edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); |
a4768d22 | 1090 | /* Set the acount, bcount, ccount registers */ |
60902a2c SR |
1091 | edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); |
1092 | edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); | |
a4768d22 KH |
1093 | } |
1094 | } | |
1095 | EXPORT_SYMBOL(edma_set_transfer_params); | |
1096 | ||
1097 | /** | |
1098 | * edma_link - link one parameter RAM slot to another | |
1099 | * @from: parameter RAM slot originating the link | |
1100 | * @to: parameter RAM slot which is the link target | |
1101 | * | |
1102 | * The originating slot should not be part of any active DMA transfer. | |
1103 | */ | |
1104 | void edma_link(unsigned from, unsigned to) | |
1105 | { | |
60902a2c SR |
1106 | unsigned ctlr_from, ctlr_to; |
1107 | ||
1108 | ctlr_from = EDMA_CTLR(from); | |
1109 | from = EDMA_CHAN_SLOT(from); | |
1110 | ctlr_to = EDMA_CTLR(to); | |
1111 | to = EDMA_CHAN_SLOT(to); | |
1112 | ||
3f68b98a | 1113 | if (from >= edma_cc[ctlr_from]->num_slots) |
a4768d22 | 1114 | return; |
3f68b98a | 1115 | if (to >= edma_cc[ctlr_to]->num_slots) |
a4768d22 | 1116 | return; |
60902a2c SR |
1117 | edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, |
1118 | PARM_OFFSET(to)); | |
a4768d22 KH |
1119 | } |
1120 | EXPORT_SYMBOL(edma_link); | |
1121 | ||
1122 | /** | |
1123 | * edma_unlink - cut link from one parameter RAM slot | |
1124 | * @from: parameter RAM slot originating the link | |
1125 | * | |
1126 | * The originating slot should not be part of any active DMA transfer. | |
1127 | * Its link is set to 0xffff. | |
1128 | */ | |
1129 | void edma_unlink(unsigned from) | |
1130 | { | |
60902a2c SR |
1131 | unsigned ctlr; |
1132 | ||
1133 | ctlr = EDMA_CTLR(from); | |
1134 | from = EDMA_CHAN_SLOT(from); | |
1135 | ||
3f68b98a | 1136 | if (from >= edma_cc[ctlr]->num_slots) |
a4768d22 | 1137 | return; |
60902a2c | 1138 | edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); |
a4768d22 KH |
1139 | } |
1140 | EXPORT_SYMBOL(edma_unlink); | |
1141 | ||
1142 | /*-----------------------------------------------------------------------*/ | |
1143 | ||
1144 | /* Parameter RAM operations (ii) -- read/write whole parameter sets */ | |
1145 | ||
1146 | /** | |
1147 | * edma_write_slot - write parameter RAM data for slot | |
1148 | * @slot: number of parameter RAM slot being modified | |
1149 | * @param: data to be written into parameter RAM slot | |
1150 | * | |
1151 | * Use this to assign all parameters of a transfer at once. This | |
1152 | * allows more efficient setup of transfers than issuing multiple | |
1153 | * calls to set up those parameters in small pieces, and provides | |
1154 | * complete control over all transfer options. | |
1155 | */ | |
1156 | void edma_write_slot(unsigned slot, const struct edmacc_param *param) | |
1157 | { | |
60902a2c SR |
1158 | unsigned ctlr; |
1159 | ||
1160 | ctlr = EDMA_CTLR(slot); | |
1161 | slot = EDMA_CHAN_SLOT(slot); | |
1162 | ||
3f68b98a | 1163 | if (slot >= edma_cc[ctlr]->num_slots) |
a4768d22 | 1164 | return; |
60902a2c SR |
1165 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, |
1166 | PARM_SIZE); | |
a4768d22 KH |
1167 | } |
1168 | EXPORT_SYMBOL(edma_write_slot); | |
1169 | ||
1170 | /** | |
1171 | * edma_read_slot - read parameter RAM data from slot | |
1172 | * @slot: number of parameter RAM slot being copied | |
1173 | * @param: where to store copy of parameter RAM data | |
1174 | * | |
1175 | * Use this to read data from a parameter RAM slot, perhaps to | |
1176 | * save them as a template for later reuse. | |
1177 | */ | |
1178 | void edma_read_slot(unsigned slot, struct edmacc_param *param) | |
1179 | { | |
60902a2c SR |
1180 | unsigned ctlr; |
1181 | ||
1182 | ctlr = EDMA_CTLR(slot); | |
1183 | slot = EDMA_CHAN_SLOT(slot); | |
1184 | ||
3f68b98a | 1185 | if (slot >= edma_cc[ctlr]->num_slots) |
a4768d22 | 1186 | return; |
60902a2c SR |
1187 | memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
1188 | PARM_SIZE); | |
a4768d22 KH |
1189 | } |
1190 | EXPORT_SYMBOL(edma_read_slot); | |
1191 | ||
1192 | /*-----------------------------------------------------------------------*/ | |
1193 | ||
1194 | /* Various EDMA channel control operations */ | |
1195 | ||
1196 | /** | |
1197 | * edma_pause - pause dma on a channel | |
1198 | * @channel: on which edma_start() has been called | |
1199 | * | |
1200 | * This temporarily disables EDMA hardware events on the specified channel, | |
1201 | * preventing them from triggering new transfers on its behalf | |
1202 | */ | |
1203 | void edma_pause(unsigned channel) | |
1204 | { | |
60902a2c SR |
1205 | unsigned ctlr; |
1206 | ||
1207 | ctlr = EDMA_CTLR(channel); | |
1208 | channel = EDMA_CHAN_SLOT(channel); | |
1209 | ||
3f68b98a | 1210 | if (channel < edma_cc[ctlr]->num_channels) { |
d78a9494 | 1211 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 | 1212 | |
60902a2c | 1213 | edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); |
a4768d22 KH |
1214 | } |
1215 | } | |
1216 | EXPORT_SYMBOL(edma_pause); | |
1217 | ||
1218 | /** | |
1219 | * edma_resume - resumes dma on a paused channel | |
1220 | * @channel: on which edma_pause() has been called | |
1221 | * | |
1222 | * This re-enables EDMA hardware events on the specified channel. | |
1223 | */ | |
1224 | void edma_resume(unsigned channel) | |
1225 | { | |
60902a2c SR |
1226 | unsigned ctlr; |
1227 | ||
1228 | ctlr = EDMA_CTLR(channel); | |
1229 | channel = EDMA_CHAN_SLOT(channel); | |
1230 | ||
3f68b98a | 1231 | if (channel < edma_cc[ctlr]->num_channels) { |
d78a9494 | 1232 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 | 1233 | |
60902a2c | 1234 | edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); |
a4768d22 KH |
1235 | } |
1236 | } | |
1237 | EXPORT_SYMBOL(edma_resume); | |
1238 | ||
1239 | /** | |
1240 | * edma_start - start dma on a channel | |
1241 | * @channel: channel being activated | |
1242 | * | |
1243 | * Channels with event associations will be triggered by their hardware | |
1244 | * events, and channels without such associations will be triggered by | |
1245 | * software. (At this writing there is no interface for using software | |
1246 | * triggers except with channels that don't support hardware triggers.) | |
1247 | * | |
1248 | * Returns zero on success, else negative errno. | |
1249 | */ | |
1250 | int edma_start(unsigned channel) | |
1251 | { | |
60902a2c SR |
1252 | unsigned ctlr; |
1253 | ||
1254 | ctlr = EDMA_CTLR(channel); | |
1255 | channel = EDMA_CHAN_SLOT(channel); | |
1256 | ||
3f68b98a | 1257 | if (channel < edma_cc[ctlr]->num_channels) { |
a4768d22 | 1258 | int j = channel >> 5; |
d78a9494 | 1259 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 KH |
1260 | |
1261 | /* EDMA channels without event association */ | |
3f68b98a | 1262 | if (test_bit(channel, edma_cc[ctlr]->edma_unused)) { |
a4768d22 | 1263 | pr_debug("EDMA: ESR%d %08x\n", j, |
60902a2c SR |
1264 | edma_shadow0_read_array(ctlr, SH_ESR, j)); |
1265 | edma_shadow0_write_array(ctlr, SH_ESR, j, mask); | |
a4768d22 KH |
1266 | return 0; |
1267 | } | |
1268 | ||
1269 | /* EDMA channel with event association */ | |
1270 | pr_debug("EDMA: ER%d %08x\n", j, | |
60902a2c | 1271 | edma_shadow0_read_array(ctlr, SH_ER, j)); |
bb17ef10 BN |
1272 | /* Clear any pending event or error */ |
1273 | edma_write_array(ctlr, EDMA_ECR, j, mask); | |
60902a2c | 1274 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
a4768d22 | 1275 | /* Clear any SER */ |
60902a2c SR |
1276 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
1277 | edma_shadow0_write_array(ctlr, SH_EESR, j, mask); | |
a4768d22 | 1278 | pr_debug("EDMA: EER%d %08x\n", j, |
60902a2c | 1279 | edma_shadow0_read_array(ctlr, SH_EER, j)); |
a4768d22 KH |
1280 | return 0; |
1281 | } | |
1282 | ||
1283 | return -EINVAL; | |
1284 | } | |
1285 | EXPORT_SYMBOL(edma_start); | |
1286 | ||
1287 | /** | |
1288 | * edma_stop - stops dma on the channel passed | |
1289 | * @channel: channel being deactivated | |
1290 | * | |
1291 | * When @lch is a channel, any active transfer is paused and | |
1292 | * all pending hardware events are cleared. The current transfer | |
1293 | * may not be resumed, and the channel's Parameter RAM should be | |
1294 | * reinitialized before being reused. | |
1295 | */ | |
1296 | void edma_stop(unsigned channel) | |
1297 | { | |
60902a2c SR |
1298 | unsigned ctlr; |
1299 | ||
1300 | ctlr = EDMA_CTLR(channel); | |
1301 | channel = EDMA_CHAN_SLOT(channel); | |
1302 | ||
3f68b98a | 1303 | if (channel < edma_cc[ctlr]->num_channels) { |
a4768d22 | 1304 | int j = channel >> 5; |
d78a9494 | 1305 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 | 1306 | |
60902a2c SR |
1307 | edma_shadow0_write_array(ctlr, SH_EECR, j, mask); |
1308 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); | |
1309 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); | |
1310 | edma_write_array(ctlr, EDMA_EMCR, j, mask); | |
a4768d22 KH |
1311 | |
1312 | pr_debug("EDMA: EER%d %08x\n", j, | |
60902a2c | 1313 | edma_shadow0_read_array(ctlr, SH_EER, j)); |
a4768d22 KH |
1314 | |
1315 | /* REVISIT: consider guarding against inappropriate event | |
1316 | * chaining by overwriting with dummy_paramset. | |
1317 | */ | |
1318 | } | |
1319 | } | |
1320 | EXPORT_SYMBOL(edma_stop); | |
1321 | ||
1322 | /****************************************************************************** | |
1323 | * | |
1324 | * It cleans ParamEntry qand bring back EDMA to initial state if media has | |
1325 | * been removed before EDMA has finished.It is usedful for removable media. | |
1326 | * Arguments: | |
1327 | * ch_no - channel no | |
1328 | * | |
1329 | * Return: zero on success, or corresponding error no on failure | |
1330 | * | |
1331 | * FIXME this should not be needed ... edma_stop() should suffice. | |
1332 | * | |
1333 | *****************************************************************************/ | |
1334 | ||
1335 | void edma_clean_channel(unsigned channel) | |
1336 | { | |
60902a2c SR |
1337 | unsigned ctlr; |
1338 | ||
1339 | ctlr = EDMA_CTLR(channel); | |
1340 | channel = EDMA_CHAN_SLOT(channel); | |
1341 | ||
3f68b98a | 1342 | if (channel < edma_cc[ctlr]->num_channels) { |
a4768d22 | 1343 | int j = (channel >> 5); |
d78a9494 | 1344 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 KH |
1345 | |
1346 | pr_debug("EDMA: EMR%d %08x\n", j, | |
60902a2c SR |
1347 | edma_read_array(ctlr, EDMA_EMR, j)); |
1348 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); | |
a4768d22 | 1349 | /* Clear the corresponding EMR bits */ |
60902a2c | 1350 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
a4768d22 | 1351 | /* Clear any SER */ |
60902a2c | 1352 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
d78a9494 | 1353 | edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); |
a4768d22 KH |
1354 | } |
1355 | } | |
1356 | EXPORT_SYMBOL(edma_clean_channel); | |
1357 | ||
1358 | /* | |
1359 | * edma_clear_event - clear an outstanding event on the DMA channel | |
1360 | * Arguments: | |
1361 | * channel - channel number | |
1362 | */ | |
1363 | void edma_clear_event(unsigned channel) | |
1364 | { | |
60902a2c SR |
1365 | unsigned ctlr; |
1366 | ||
1367 | ctlr = EDMA_CTLR(channel); | |
1368 | channel = EDMA_CHAN_SLOT(channel); | |
1369 | ||
3f68b98a | 1370 | if (channel >= edma_cc[ctlr]->num_channels) |
a4768d22 KH |
1371 | return; |
1372 | if (channel < 32) | |
d78a9494 | 1373 | edma_write(ctlr, EDMA_ECR, BIT(channel)); |
a4768d22 | 1374 | else |
d78a9494 | 1375 | edma_write(ctlr, EDMA_ECRH, BIT(channel - 32)); |
a4768d22 KH |
1376 | } |
1377 | EXPORT_SYMBOL(edma_clear_event); | |
1378 | ||
6cba4355 MP |
1379 | #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES) |
1380 | ||
1381 | static int edma_of_parse_dt(struct device *dev, | |
1382 | struct device_node *node, | |
1383 | struct edma_soc_info *pdata) | |
1384 | { | |
1385 | int ret = 0, i; | |
1386 | u32 value; | |
1387 | struct edma_rsv_info *rsv_info; | |
1388 | s8 (*queue_tc_map)[2], (*queue_priority_map)[2]; | |
1389 | ||
1390 | memset(pdata, 0, sizeof(struct edma_soc_info)); | |
1391 | ||
1392 | ret = of_property_read_u32(node, "dma-channels", &value); | |
1393 | if (ret < 0) | |
1394 | return ret; | |
1395 | pdata->n_channel = value; | |
1396 | ||
1397 | ret = of_property_read_u32(node, "ti,edma-regions", &value); | |
1398 | if (ret < 0) | |
1399 | return ret; | |
1400 | pdata->n_region = value; | |
1401 | ||
1402 | ret = of_property_read_u32(node, "ti,edma-slots", &value); | |
1403 | if (ret < 0) | |
1404 | return ret; | |
1405 | pdata->n_slot = value; | |
1406 | ||
1407 | pdata->n_cc = 1; | |
1408 | ||
1409 | rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL); | |
1410 | if (!rsv_info) | |
1411 | return -ENOMEM; | |
1412 | pdata->rsv = rsv_info; | |
1413 | ||
1414 | queue_tc_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL); | |
1415 | if (!queue_tc_map) | |
1416 | return -ENOMEM; | |
1417 | ||
1418 | for (i = 0; i < 3; i++) { | |
1419 | queue_tc_map[i][0] = i; | |
1420 | queue_tc_map[i][1] = i; | |
1421 | } | |
1422 | queue_tc_map[i][0] = -1; | |
1423 | queue_tc_map[i][1] = -1; | |
1424 | ||
1425 | pdata->queue_tc_mapping = queue_tc_map; | |
1426 | ||
1427 | queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL); | |
1428 | if (!queue_priority_map) | |
1429 | return -ENOMEM; | |
1430 | ||
1431 | for (i = 0; i < 3; i++) { | |
1432 | queue_priority_map[i][0] = i; | |
1433 | queue_priority_map[i][1] = i; | |
1434 | } | |
1435 | queue_priority_map[i][0] = -1; | |
1436 | queue_priority_map[i][1] = -1; | |
1437 | ||
1438 | pdata->queue_priority_mapping = queue_priority_map; | |
1439 | ||
1440 | pdata->default_queue = 0; | |
a4768d22 | 1441 | |
6cba4355 MP |
1442 | return ret; |
1443 | } | |
1444 | ||
1445 | static struct of_dma_filter_info edma_filter_info = { | |
1446 | .filter_fn = edma_filter_fn, | |
1447 | }; | |
1448 | ||
1449 | static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, | |
1450 | struct device_node *node) | |
1451 | { | |
1452 | struct edma_soc_info *info; | |
1453 | int ret; | |
1454 | ||
1455 | info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL); | |
1456 | if (!info) | |
1457 | return ERR_PTR(-ENOMEM); | |
1458 | ||
1459 | ret = edma_of_parse_dt(dev, node, info); | |
1460 | if (ret) | |
1461 | return ERR_PTR(ret); | |
1462 | ||
1463 | dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap); | |
1464 | of_dma_controller_register(dev->of_node, of_dma_simple_xlate, | |
1465 | &edma_filter_info); | |
1466 | ||
1467 | return info; | |
1468 | } | |
1469 | #else | |
1470 | static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, | |
1471 | struct device_node *node) | |
1472 | { | |
1473 | return ERR_PTR(-ENOSYS); | |
1474 | } | |
1475 | #endif | |
1476 | ||
1477 | static int edma_probe(struct platform_device *pdev) | |
a4768d22 | 1478 | { |
bc3ac9f3 | 1479 | struct edma_soc_info **info = pdev->dev.platform_data; |
6cba4355 MP |
1480 | struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL}; |
1481 | s8 (*queue_priority_mapping)[2]; | |
1482 | s8 (*queue_tc_mapping)[2]; | |
90bd4e6d | 1483 | int i, j, off, ln, found = 0; |
60902a2c | 1484 | int status = -1; |
90bd4e6d RS |
1485 | const s16 (*rsv_chans)[2]; |
1486 | const s16 (*rsv_slots)[2]; | |
60902a2c SR |
1487 | int irq[EDMA_MAX_CC] = {0, 0}; |
1488 | int err_irq[EDMA_MAX_CC] = {0, 0}; | |
1489 | struct resource *r[EDMA_MAX_CC] = {NULL}; | |
6cba4355 | 1490 | struct resource res[EDMA_MAX_CC]; |
60902a2c SR |
1491 | char res_name[10]; |
1492 | char irq_name[10]; | |
6cba4355 MP |
1493 | struct device_node *node = pdev->dev.of_node; |
1494 | struct device *dev = &pdev->dev; | |
1495 | int ret; | |
1496 | ||
1497 | if (node) { | |
1498 | /* Check if this is a second instance registered */ | |
1499 | if (arch_num_cc) { | |
1500 | dev_err(dev, "only one EDMA instance is supported via DT\n"); | |
1501 | return -ENODEV; | |
1502 | } | |
1503 | ||
1504 | ninfo[0] = edma_setup_info_from_dt(dev, node); | |
1505 | if (IS_ERR(ninfo[0])) { | |
1506 | dev_err(dev, "failed to get DT data\n"); | |
1507 | return PTR_ERR(ninfo[0]); | |
1508 | } | |
1509 | ||
1510 | info = ninfo; | |
1511 | } | |
a4768d22 KH |
1512 | |
1513 | if (!info) | |
1514 | return -ENODEV; | |
1515 | ||
6cba4355 MP |
1516 | pm_runtime_enable(dev); |
1517 | ret = pm_runtime_get_sync(dev); | |
1518 | if (ret < 0) { | |
1519 | dev_err(dev, "pm_runtime_get_sync() failed\n"); | |
1520 | return ret; | |
1521 | } | |
1522 | ||
60902a2c | 1523 | for (j = 0; j < EDMA_MAX_CC; j++) { |
6cba4355 MP |
1524 | if (!info[j]) { |
1525 | if (!found) | |
1526 | return -ENODEV; | |
1527 | break; | |
1528 | } | |
1529 | if (node) { | |
1530 | ret = of_address_to_resource(node, j, &res[j]); | |
1531 | if (!ret) | |
1532 | r[j] = &res[j]; | |
1533 | } else { | |
1534 | sprintf(res_name, "edma_cc%d", j); | |
1535 | r[j] = platform_get_resource_byname(pdev, | |
1536 | IORESOURCE_MEM, | |
60902a2c | 1537 | res_name); |
6cba4355 MP |
1538 | } |
1539 | if (!r[j]) { | |
60902a2c SR |
1540 | if (found) |
1541 | break; | |
1542 | else | |
1543 | return -ENODEV; | |
243bc654 | 1544 | } else { |
60902a2c | 1545 | found = 1; |
243bc654 | 1546 | } |
60902a2c | 1547 | |
e7eff702 LP |
1548 | edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]); |
1549 | if (IS_ERR(edmacc_regs_base[j])) | |
1550 | return PTR_ERR(edmacc_regs_base[j]); | |
60902a2c | 1551 | |
e7eff702 LP |
1552 | edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma), |
1553 | GFP_KERNEL); | |
1554 | if (!edma_cc[j]) | |
1555 | return -ENOMEM; | |
60902a2c | 1556 | |
bc3ac9f3 | 1557 | edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel, |
60902a2c | 1558 | EDMA_MAX_DMACH); |
bc3ac9f3 | 1559 | edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot, |
60902a2c | 1560 | EDMA_MAX_PARAMENTRY); |
bc3ac9f3 SN |
1561 | edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc, |
1562 | EDMA_MAX_CC); | |
60902a2c | 1563 | |
bc3ac9f3 | 1564 | edma_cc[j]->default_queue = info[j]->default_queue; |
a0f0202e | 1565 | |
60902a2c SR |
1566 | dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", |
1567 | edmacc_regs_base[j]); | |
1568 | ||
3f68b98a | 1569 | for (i = 0; i < edma_cc[j]->num_slots; i++) |
60902a2c SR |
1570 | memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), |
1571 | &dummy_paramset, PARM_SIZE); | |
1572 | ||
f900d552 | 1573 | /* Mark all channels as unused */ |
3f68b98a SN |
1574 | memset(edma_cc[j]->edma_unused, 0xff, |
1575 | sizeof(edma_cc[j]->edma_unused)); | |
a4768d22 | 1576 | |
90bd4e6d RS |
1577 | if (info[j]->rsv) { |
1578 | ||
1579 | /* Clear the reserved channels in unused list */ | |
1580 | rsv_chans = info[j]->rsv->rsv_chans; | |
1581 | if (rsv_chans) { | |
1582 | for (i = 0; rsv_chans[i][0] != -1; i++) { | |
1583 | off = rsv_chans[i][0]; | |
1584 | ln = rsv_chans[i][1]; | |
1585 | clear_bits(off, ln, | |
6cba4355 | 1586 | edma_cc[j]->edma_unused); |
90bd4e6d RS |
1587 | } |
1588 | } | |
1589 | ||
1590 | /* Set the reserved slots in inuse list */ | |
1591 | rsv_slots = info[j]->rsv->rsv_slots; | |
1592 | if (rsv_slots) { | |
1593 | for (i = 0; rsv_slots[i][0] != -1; i++) { | |
1594 | off = rsv_slots[i][0]; | |
1595 | ln = rsv_slots[i][1]; | |
1596 | set_bits(off, ln, | |
1597 | edma_cc[j]->edma_inuse); | |
1598 | } | |
1599 | } | |
1600 | } | |
1601 | ||
6cba4355 MP |
1602 | |
1603 | if (node) { | |
1604 | irq[j] = irq_of_parse_and_map(node, 0); | |
1605 | } else { | |
1606 | sprintf(irq_name, "edma%d", j); | |
1607 | irq[j] = platform_get_irq_byname(pdev, irq_name); | |
1608 | } | |
3f68b98a | 1609 | edma_cc[j]->irq_res_start = irq[j]; |
e7eff702 LP |
1610 | status = devm_request_irq(&pdev->dev, irq[j], |
1611 | dma_irq_handler, 0, "edma", | |
1612 | &pdev->dev); | |
60902a2c | 1613 | if (status < 0) { |
e7eff702 LP |
1614 | dev_dbg(&pdev->dev, |
1615 | "devm_request_irq %d failed --> %d\n", | |
60902a2c | 1616 | irq[j], status); |
e7eff702 | 1617 | return status; |
60902a2c | 1618 | } |
a4768d22 | 1619 | |
6cba4355 MP |
1620 | if (node) { |
1621 | err_irq[j] = irq_of_parse_and_map(node, 2); | |
1622 | } else { | |
1623 | sprintf(irq_name, "edma%d_err", j); | |
1624 | err_irq[j] = platform_get_irq_byname(pdev, irq_name); | |
1625 | } | |
3f68b98a | 1626 | edma_cc[j]->irq_res_end = err_irq[j]; |
e7eff702 LP |
1627 | status = devm_request_irq(&pdev->dev, err_irq[j], |
1628 | dma_ccerr_handler, 0, | |
1629 | "edma_error", &pdev->dev); | |
60902a2c | 1630 | if (status < 0) { |
e7eff702 LP |
1631 | dev_dbg(&pdev->dev, |
1632 | "devm_request_irq %d failed --> %d\n", | |
60902a2c | 1633 | err_irq[j], status); |
e7eff702 | 1634 | return status; |
60902a2c | 1635 | } |
a4768d22 | 1636 | |
3f68b98a | 1637 | for (i = 0; i < edma_cc[j]->num_channels; i++) |
0b7580ba | 1638 | map_dmach_queue(j, i, info[j]->default_queue); |
a4768d22 | 1639 | |
bc3ac9f3 SN |
1640 | queue_tc_mapping = info[j]->queue_tc_mapping; |
1641 | queue_priority_mapping = info[j]->queue_priority_mapping; | |
a4768d22 | 1642 | |
60902a2c SR |
1643 | /* Event queue to TC mapping */ |
1644 | for (i = 0; queue_tc_mapping[i][0] != -1; i++) | |
1645 | map_queue_tc(j, queue_tc_mapping[i][0], | |
1646 | queue_tc_mapping[i][1]); | |
a4768d22 | 1647 | |
60902a2c SR |
1648 | /* Event queue priority mapping */ |
1649 | for (i = 0; queue_priority_mapping[i][0] != -1; i++) | |
1650 | assign_priority_to_queue(j, | |
1651 | queue_priority_mapping[i][0], | |
1652 | queue_priority_mapping[i][1]); | |
1653 | ||
1654 | /* Map the channel to param entry if channel mapping logic | |
1655 | * exist | |
1656 | */ | |
1657 | if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST) | |
1658 | map_dmach_param(j); | |
a4768d22 | 1659 | |
bc3ac9f3 | 1660 | for (i = 0; i < info[j]->n_region; i++) { |
60902a2c SR |
1661 | edma_write_array2(j, EDMA_DRAE, i, 0, 0x0); |
1662 | edma_write_array2(j, EDMA_DRAE, i, 1, 0x0); | |
1663 | edma_write_array(j, EDMA_QRAE, i, 0x0); | |
1664 | } | |
2d517508 | 1665 | arch_num_cc++; |
a4768d22 KH |
1666 | } |
1667 | ||
a4768d22 | 1668 | return 0; |
a4768d22 KH |
1669 | } |
1670 | ||
6cba4355 MP |
1671 | static const struct of_device_id edma_of_ids[] = { |
1672 | { .compatible = "ti,edma3", }, | |
1673 | {} | |
1674 | }; | |
a4768d22 KH |
1675 | |
1676 | static struct platform_driver edma_driver = { | |
6cba4355 MP |
1677 | .driver = { |
1678 | .name = "edma", | |
1679 | .of_match_table = edma_of_ids, | |
1680 | }, | |
1681 | .probe = edma_probe, | |
a4768d22 KH |
1682 | }; |
1683 | ||
1684 | static int __init edma_init(void) | |
1685 | { | |
1686 | return platform_driver_probe(&edma_driver, edma_probe); | |
1687 | } | |
1688 | arch_initcall(edma_init); | |
1689 |