Commit | Line | Data |
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a4768d22 KH |
1 | /* |
2 | * EDMA3 support for DaVinci | |
3 | * | |
4 | * Copyright (C) 2006-2009 Texas Instruments. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
e7eff702 | 20 | #include <linux/err.h> |
a4768d22 | 21 | #include <linux/kernel.h> |
a4768d22 KH |
22 | #include <linux/init.h> |
23 | #include <linux/module.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/platform_device.h> | |
a4768d22 | 26 | #include <linux/io.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
6cba4355 | 28 | #include <linux/edma.h> |
5305e4d6 | 29 | #include <linux/dma-mapping.h> |
6cba4355 MP |
30 | #include <linux/of_address.h> |
31 | #include <linux/of_device.h> | |
32 | #include <linux/of_dma.h> | |
33 | #include <linux/of_irq.h> | |
34 | #include <linux/pm_runtime.h> | |
a4768d22 | 35 | |
3ad7a42d | 36 | #include <linux/platform_data/edma.h> |
a4768d22 KH |
37 | |
38 | /* Offsets matching "struct edmacc_param" */ | |
39 | #define PARM_OPT 0x00 | |
40 | #define PARM_SRC 0x04 | |
41 | #define PARM_A_B_CNT 0x08 | |
42 | #define PARM_DST 0x0c | |
43 | #define PARM_SRC_DST_BIDX 0x10 | |
44 | #define PARM_LINK_BCNTRLD 0x14 | |
45 | #define PARM_SRC_DST_CIDX 0x18 | |
46 | #define PARM_CCNT 0x1c | |
47 | ||
48 | #define PARM_SIZE 0x20 | |
49 | ||
50 | /* Offsets for EDMA CC global channel registers and their shadows */ | |
51 | #define SH_ER 0x00 /* 64 bits */ | |
52 | #define SH_ECR 0x08 /* 64 bits */ | |
53 | #define SH_ESR 0x10 /* 64 bits */ | |
54 | #define SH_CER 0x18 /* 64 bits */ | |
55 | #define SH_EER 0x20 /* 64 bits */ | |
56 | #define SH_EECR 0x28 /* 64 bits */ | |
57 | #define SH_EESR 0x30 /* 64 bits */ | |
58 | #define SH_SER 0x38 /* 64 bits */ | |
59 | #define SH_SECR 0x40 /* 64 bits */ | |
60 | #define SH_IER 0x50 /* 64 bits */ | |
61 | #define SH_IECR 0x58 /* 64 bits */ | |
62 | #define SH_IESR 0x60 /* 64 bits */ | |
63 | #define SH_IPR 0x68 /* 64 bits */ | |
64 | #define SH_ICR 0x70 /* 64 bits */ | |
65 | #define SH_IEVAL 0x78 | |
66 | #define SH_QER 0x80 | |
67 | #define SH_QEER 0x84 | |
68 | #define SH_QEECR 0x88 | |
69 | #define SH_QEESR 0x8c | |
70 | #define SH_QSER 0x90 | |
71 | #define SH_QSECR 0x94 | |
72 | #define SH_SIZE 0x200 | |
73 | ||
74 | /* Offsets for EDMA CC global registers */ | |
75 | #define EDMA_REV 0x0000 | |
76 | #define EDMA_CCCFG 0x0004 | |
77 | #define EDMA_QCHMAP 0x0200 /* 8 registers */ | |
78 | #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ | |
79 | #define EDMA_QDMAQNUM 0x0260 | |
80 | #define EDMA_QUETCMAP 0x0280 | |
81 | #define EDMA_QUEPRI 0x0284 | |
82 | #define EDMA_EMR 0x0300 /* 64 bits */ | |
83 | #define EDMA_EMCR 0x0308 /* 64 bits */ | |
84 | #define EDMA_QEMR 0x0310 | |
85 | #define EDMA_QEMCR 0x0314 | |
86 | #define EDMA_CCERR 0x0318 | |
87 | #define EDMA_CCERRCLR 0x031c | |
88 | #define EDMA_EEVAL 0x0320 | |
89 | #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ | |
90 | #define EDMA_QRAE 0x0380 /* 4 registers */ | |
91 | #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ | |
92 | #define EDMA_QSTAT 0x0600 /* 2 registers */ | |
93 | #define EDMA_QWMTHRA 0x0620 | |
94 | #define EDMA_QWMTHRB 0x0624 | |
95 | #define EDMA_CCSTAT 0x0640 | |
96 | ||
97 | #define EDMA_M 0x1000 /* global channel registers */ | |
98 | #define EDMA_ECR 0x1008 | |
99 | #define EDMA_ECRH 0x100C | |
100 | #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ | |
101 | #define EDMA_PARM 0x4000 /* 128 param entries */ | |
102 | ||
a4768d22 KH |
103 | #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) |
104 | ||
60902a2c | 105 | #define EDMA_DCHMAP 0x0100 /* 64 registers */ |
6d10c395 PU |
106 | |
107 | /* CCCFG register */ | |
108 | #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */ | |
109 | #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */ | |
110 | #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */ | |
111 | #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */ | |
112 | #define CHMAP_EXIST BIT(24) | |
60902a2c | 113 | |
a4768d22 KH |
114 | #define EDMA_MAX_DMACH 64 |
115 | #define EDMA_MAX_PARAMENTRY 512 | |
a4768d22 KH |
116 | |
117 | /*****************************************************************************/ | |
118 | ||
60902a2c | 119 | static void __iomem *edmacc_regs_base[EDMA_MAX_CC]; |
a4768d22 | 120 | |
60902a2c | 121 | static inline unsigned int edma_read(unsigned ctlr, int offset) |
a4768d22 | 122 | { |
60902a2c | 123 | return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset); |
a4768d22 KH |
124 | } |
125 | ||
60902a2c | 126 | static inline void edma_write(unsigned ctlr, int offset, int val) |
a4768d22 | 127 | { |
60902a2c | 128 | __raw_writel(val, edmacc_regs_base[ctlr] + offset); |
a4768d22 | 129 | } |
60902a2c SR |
130 | static inline void edma_modify(unsigned ctlr, int offset, unsigned and, |
131 | unsigned or) | |
a4768d22 | 132 | { |
60902a2c | 133 | unsigned val = edma_read(ctlr, offset); |
a4768d22 KH |
134 | val &= and; |
135 | val |= or; | |
60902a2c | 136 | edma_write(ctlr, offset, val); |
a4768d22 | 137 | } |
60902a2c | 138 | static inline void edma_and(unsigned ctlr, int offset, unsigned and) |
a4768d22 | 139 | { |
60902a2c | 140 | unsigned val = edma_read(ctlr, offset); |
a4768d22 | 141 | val &= and; |
60902a2c | 142 | edma_write(ctlr, offset, val); |
a4768d22 | 143 | } |
60902a2c | 144 | static inline void edma_or(unsigned ctlr, int offset, unsigned or) |
a4768d22 | 145 | { |
60902a2c | 146 | unsigned val = edma_read(ctlr, offset); |
a4768d22 | 147 | val |= or; |
60902a2c | 148 | edma_write(ctlr, offset, val); |
a4768d22 | 149 | } |
60902a2c | 150 | static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i) |
a4768d22 | 151 | { |
60902a2c | 152 | return edma_read(ctlr, offset + (i << 2)); |
a4768d22 | 153 | } |
60902a2c SR |
154 | static inline void edma_write_array(unsigned ctlr, int offset, int i, |
155 | unsigned val) | |
a4768d22 | 156 | { |
60902a2c | 157 | edma_write(ctlr, offset + (i << 2), val); |
a4768d22 | 158 | } |
60902a2c | 159 | static inline void edma_modify_array(unsigned ctlr, int offset, int i, |
a4768d22 KH |
160 | unsigned and, unsigned or) |
161 | { | |
60902a2c | 162 | edma_modify(ctlr, offset + (i << 2), and, or); |
a4768d22 | 163 | } |
60902a2c | 164 | static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or) |
a4768d22 | 165 | { |
60902a2c | 166 | edma_or(ctlr, offset + (i << 2), or); |
a4768d22 | 167 | } |
60902a2c SR |
168 | static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j, |
169 | unsigned or) | |
a4768d22 | 170 | { |
60902a2c | 171 | edma_or(ctlr, offset + ((i*2 + j) << 2), or); |
a4768d22 | 172 | } |
60902a2c SR |
173 | static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j, |
174 | unsigned val) | |
a4768d22 | 175 | { |
60902a2c | 176 | edma_write(ctlr, offset + ((i*2 + j) << 2), val); |
a4768d22 | 177 | } |
60902a2c | 178 | static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset) |
a4768d22 | 179 | { |
60902a2c | 180 | return edma_read(ctlr, EDMA_SHADOW0 + offset); |
a4768d22 | 181 | } |
60902a2c SR |
182 | static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset, |
183 | int i) | |
a4768d22 | 184 | { |
60902a2c | 185 | return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); |
a4768d22 | 186 | } |
60902a2c | 187 | static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val) |
a4768d22 | 188 | { |
60902a2c | 189 | edma_write(ctlr, EDMA_SHADOW0 + offset, val); |
a4768d22 | 190 | } |
60902a2c SR |
191 | static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, |
192 | unsigned val) | |
a4768d22 | 193 | { |
60902a2c | 194 | edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); |
a4768d22 | 195 | } |
60902a2c SR |
196 | static inline unsigned int edma_parm_read(unsigned ctlr, int offset, |
197 | int param_no) | |
a4768d22 | 198 | { |
60902a2c | 199 | return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); |
a4768d22 | 200 | } |
60902a2c SR |
201 | static inline void edma_parm_write(unsigned ctlr, int offset, int param_no, |
202 | unsigned val) | |
a4768d22 | 203 | { |
60902a2c | 204 | edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); |
a4768d22 | 205 | } |
60902a2c | 206 | static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no, |
a4768d22 KH |
207 | unsigned and, unsigned or) |
208 | { | |
60902a2c | 209 | edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); |
a4768d22 | 210 | } |
60902a2c SR |
211 | static inline void edma_parm_and(unsigned ctlr, int offset, int param_no, |
212 | unsigned and) | |
a4768d22 | 213 | { |
60902a2c | 214 | edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); |
a4768d22 | 215 | } |
60902a2c SR |
216 | static inline void edma_parm_or(unsigned ctlr, int offset, int param_no, |
217 | unsigned or) | |
a4768d22 | 218 | { |
60902a2c | 219 | edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); |
a4768d22 KH |
220 | } |
221 | ||
90bd4e6d RS |
222 | static inline void set_bits(int offset, int len, unsigned long *p) |
223 | { | |
224 | for (; len > 0; len--) | |
225 | set_bit(offset + (len - 1), p); | |
226 | } | |
227 | ||
228 | static inline void clear_bits(int offset, int len, unsigned long *p) | |
229 | { | |
230 | for (; len > 0; len--) | |
231 | clear_bit(offset + (len - 1), p); | |
232 | } | |
233 | ||
a4768d22 KH |
234 | /*****************************************************************************/ |
235 | ||
236 | /* actual number of DMA channels and slots on this silicon */ | |
60902a2c SR |
237 | struct edma { |
238 | /* how many dma resources of each type */ | |
239 | unsigned num_channels; | |
240 | unsigned num_region; | |
241 | unsigned num_slots; | |
242 | unsigned num_tc; | |
a0f0202e | 243 | enum dma_event_q default_queue; |
60902a2c SR |
244 | |
245 | /* list of channels with no even trigger; terminated by "-1" */ | |
246 | const s8 *noevent; | |
247 | ||
a2b11751 DM |
248 | struct edma_soc_info *info; |
249 | ||
60902a2c SR |
250 | /* The edma_inuse bit for each PaRAM slot is clear unless the |
251 | * channel is in use ... by ARM or DSP, for QDMA, or whatever. | |
252 | */ | |
253 | DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); | |
a4768d22 | 254 | |
f900d552 SR |
255 | /* The edma_unused bit for each channel is clear unless |
256 | * it is not being used on this platform. It uses a bit | |
257 | * of SOC-specific initialization code. | |
60902a2c | 258 | */ |
f900d552 | 259 | DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH); |
a4768d22 | 260 | |
60902a2c SR |
261 | unsigned irq_res_start; |
262 | unsigned irq_res_end; | |
a4768d22 | 263 | |
60902a2c SR |
264 | struct dma_interrupt_data { |
265 | void (*callback)(unsigned channel, unsigned short ch_status, | |
266 | void *data); | |
267 | void *data; | |
268 | } intr_data[EDMA_MAX_DMACH]; | |
269 | }; | |
270 | ||
3f68b98a | 271 | static struct edma *edma_cc[EDMA_MAX_CC]; |
2d517508 | 272 | static int arch_num_cc; |
a4768d22 KH |
273 | |
274 | /* dummy param set used to (re)initialize parameter RAM slots */ | |
275 | static const struct edmacc_param dummy_paramset = { | |
276 | .link_bcntrld = 0xffff, | |
277 | .ccnt = 1, | |
278 | }; | |
279 | ||
6cdaca48 JF |
280 | static const struct of_device_id edma_of_ids[] = { |
281 | { .compatible = "ti,edma3", }, | |
282 | {} | |
283 | }; | |
284 | ||
a4768d22 KH |
285 | /*****************************************************************************/ |
286 | ||
60902a2c SR |
287 | static void map_dmach_queue(unsigned ctlr, unsigned ch_no, |
288 | enum dma_event_q queue_no) | |
a4768d22 KH |
289 | { |
290 | int bit = (ch_no & 0x7) * 4; | |
291 | ||
292 | /* default to low priority queue */ | |
293 | if (queue_no == EVENTQ_DEFAULT) | |
3f68b98a | 294 | queue_no = edma_cc[ctlr]->default_queue; |
a4768d22 KH |
295 | |
296 | queue_no &= 7; | |
60902a2c | 297 | edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), |
a4768d22 KH |
298 | ~(0x7 << bit), queue_no << bit); |
299 | } | |
300 | ||
a2b11751 | 301 | static void assign_priority_to_queue(unsigned ctlr, int queue_no, |
60902a2c | 302 | int priority) |
a4768d22 KH |
303 | { |
304 | int bit = queue_no * 4; | |
60902a2c SR |
305 | edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), |
306 | ((priority & 0x7) << bit)); | |
307 | } | |
308 | ||
309 | /** | |
310 | * map_dmach_param - Maps channel number to param entry number | |
311 | * | |
312 | * This maps the dma channel number to param entry numberter. In | |
313 | * other words using the DMA channel mapping registers a param entry | |
314 | * can be mapped to any channel | |
315 | * | |
316 | * Callers are responsible for ensuring the channel mapping logic is | |
317 | * included in that particular EDMA variant (Eg : dm646x) | |
318 | * | |
319 | */ | |
a2b11751 | 320 | static void map_dmach_param(unsigned ctlr) |
60902a2c SR |
321 | { |
322 | int i; | |
323 | for (i = 0; i < EDMA_MAX_DMACH; i++) | |
324 | edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); | |
a4768d22 KH |
325 | } |
326 | ||
327 | static inline void | |
328 | setup_dma_interrupt(unsigned lch, | |
329 | void (*callback)(unsigned channel, u16 ch_status, void *data), | |
330 | void *data) | |
331 | { | |
60902a2c SR |
332 | unsigned ctlr; |
333 | ||
334 | ctlr = EDMA_CTLR(lch); | |
335 | lch = EDMA_CHAN_SLOT(lch); | |
336 | ||
243bc654 | 337 | if (!callback) |
60902a2c | 338 | edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, |
d78a9494 | 339 | BIT(lch & 0x1f)); |
a4768d22 | 340 | |
3f68b98a SN |
341 | edma_cc[ctlr]->intr_data[lch].callback = callback; |
342 | edma_cc[ctlr]->intr_data[lch].data = data; | |
a4768d22 KH |
343 | |
344 | if (callback) { | |
60902a2c | 345 | edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, |
d78a9494 | 346 | BIT(lch & 0x1f)); |
60902a2c | 347 | edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, |
d78a9494 | 348 | BIT(lch & 0x1f)); |
a4768d22 KH |
349 | } |
350 | } | |
351 | ||
60902a2c SR |
352 | static int irq2ctlr(int irq) |
353 | { | |
3f68b98a | 354 | if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end) |
60902a2c | 355 | return 0; |
3f68b98a SN |
356 | else if (irq >= edma_cc[1]->irq_res_start && |
357 | irq <= edma_cc[1]->irq_res_end) | |
60902a2c SR |
358 | return 1; |
359 | ||
360 | return -1; | |
361 | } | |
362 | ||
a4768d22 KH |
363 | /****************************************************************************** |
364 | * | |
365 | * DMA interrupt handler | |
366 | * | |
367 | *****************************************************************************/ | |
368 | static irqreturn_t dma_irq_handler(int irq, void *data) | |
369 | { | |
93fe23d8 | 370 | int ctlr; |
bcd59b0f SAS |
371 | u32 sh_ier; |
372 | u32 sh_ipr; | |
373 | u32 bank; | |
a4768d22 | 374 | |
60902a2c | 375 | ctlr = irq2ctlr(irq); |
93fe23d8 KV |
376 | if (ctlr < 0) |
377 | return IRQ_NONE; | |
60902a2c | 378 | |
a4768d22 KH |
379 | dev_dbg(data, "dma_irq_handler\n"); |
380 | ||
bcd59b0f SAS |
381 | sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0); |
382 | if (!sh_ipr) { | |
383 | sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1); | |
384 | if (!sh_ipr) | |
385 | return IRQ_NONE; | |
386 | sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1); | |
387 | bank = 1; | |
388 | } else { | |
389 | sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0); | |
390 | bank = 0; | |
391 | } | |
392 | ||
393 | do { | |
394 | u32 slot; | |
395 | u32 channel; | |
a4768d22 | 396 | |
bcd59b0f SAS |
397 | dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr); |
398 | ||
399 | slot = __ffs(sh_ipr); | |
400 | sh_ipr &= ~(BIT(slot)); | |
401 | ||
402 | if (sh_ier & BIT(slot)) { | |
403 | channel = (bank << 5) | slot; | |
404 | /* Clear the corresponding IPR bits */ | |
405 | edma_shadow0_write_array(ctlr, SH_ICR, bank, | |
406 | BIT(slot)); | |
407 | if (edma_cc[ctlr]->intr_data[channel].callback) | |
408 | edma_cc[ctlr]->intr_data[channel].callback( | |
db60d8da | 409 | channel, EDMA_DMA_COMPLETE, |
bcd59b0f | 410 | edma_cc[ctlr]->intr_data[channel].data); |
a4768d22 | 411 | } |
bcd59b0f SAS |
412 | } while (sh_ipr); |
413 | ||
60902a2c | 414 | edma_shadow0_write(ctlr, SH_IEVAL, 1); |
a4768d22 KH |
415 | return IRQ_HANDLED; |
416 | } | |
417 | ||
418 | /****************************************************************************** | |
419 | * | |
420 | * DMA error interrupt handler | |
421 | * | |
422 | *****************************************************************************/ | |
423 | static irqreturn_t dma_ccerr_handler(int irq, void *data) | |
424 | { | |
425 | int i; | |
93fe23d8 | 426 | int ctlr; |
a4768d22 KH |
427 | unsigned int cnt = 0; |
428 | ||
60902a2c | 429 | ctlr = irq2ctlr(irq); |
93fe23d8 KV |
430 | if (ctlr < 0) |
431 | return IRQ_NONE; | |
60902a2c | 432 | |
a4768d22 KH |
433 | dev_dbg(data, "dma_ccerr_handler\n"); |
434 | ||
60902a2c SR |
435 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && |
436 | (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && | |
437 | (edma_read(ctlr, EDMA_QEMR) == 0) && | |
438 | (edma_read(ctlr, EDMA_CCERR) == 0)) | |
a4768d22 KH |
439 | return IRQ_NONE; |
440 | ||
441 | while (1) { | |
442 | int j = -1; | |
60902a2c | 443 | if (edma_read_array(ctlr, EDMA_EMR, 0)) |
a4768d22 | 444 | j = 0; |
60902a2c | 445 | else if (edma_read_array(ctlr, EDMA_EMR, 1)) |
a4768d22 KH |
446 | j = 1; |
447 | if (j >= 0) { | |
448 | dev_dbg(data, "EMR%d %08x\n", j, | |
60902a2c | 449 | edma_read_array(ctlr, EDMA_EMR, j)); |
a4768d22 KH |
450 | for (i = 0; i < 32; i++) { |
451 | int k = (j << 5) + i; | |
60902a2c | 452 | if (edma_read_array(ctlr, EDMA_EMR, j) & |
d78a9494 | 453 | BIT(i)) { |
a4768d22 | 454 | /* Clear the corresponding EMR bits */ |
60902a2c | 455 | edma_write_array(ctlr, EDMA_EMCR, j, |
d78a9494 | 456 | BIT(i)); |
a4768d22 | 457 | /* Clear any SER */ |
60902a2c | 458 | edma_shadow0_write_array(ctlr, SH_SECR, |
d78a9494 | 459 | j, BIT(i)); |
3f68b98a | 460 | if (edma_cc[ctlr]->intr_data[k]. |
60902a2c | 461 | callback) { |
3f68b98a | 462 | edma_cc[ctlr]->intr_data[k]. |
60902a2c | 463 | callback(k, |
db60d8da | 464 | EDMA_DMA_CC_ERROR, |
3f68b98a | 465 | edma_cc[ctlr]->intr_data |
60902a2c | 466 | [k].data); |
a4768d22 KH |
467 | } |
468 | } | |
469 | } | |
60902a2c | 470 | } else if (edma_read(ctlr, EDMA_QEMR)) { |
a4768d22 | 471 | dev_dbg(data, "QEMR %02x\n", |
60902a2c | 472 | edma_read(ctlr, EDMA_QEMR)); |
a4768d22 | 473 | for (i = 0; i < 8; i++) { |
d78a9494 | 474 | if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { |
a4768d22 | 475 | /* Clear the corresponding IPR bits */ |
d78a9494 | 476 | edma_write(ctlr, EDMA_QEMCR, BIT(i)); |
60902a2c | 477 | edma_shadow0_write(ctlr, SH_QSECR, |
d78a9494 | 478 | BIT(i)); |
a4768d22 KH |
479 | |
480 | /* NOTE: not reported!! */ | |
481 | } | |
482 | } | |
60902a2c | 483 | } else if (edma_read(ctlr, EDMA_CCERR)) { |
a4768d22 | 484 | dev_dbg(data, "CCERR %08x\n", |
60902a2c | 485 | edma_read(ctlr, EDMA_CCERR)); |
a4768d22 KH |
486 | /* FIXME: CCERR.BIT(16) ignored! much better |
487 | * to just write CCERRCLR with CCERR value... | |
488 | */ | |
489 | for (i = 0; i < 8; i++) { | |
d78a9494 | 490 | if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) { |
a4768d22 | 491 | /* Clear the corresponding IPR bits */ |
d78a9494 | 492 | edma_write(ctlr, EDMA_CCERRCLR, BIT(i)); |
a4768d22 KH |
493 | |
494 | /* NOTE: not reported!! */ | |
495 | } | |
496 | } | |
497 | } | |
a6374f53 SN |
498 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && |
499 | (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && | |
500 | (edma_read(ctlr, EDMA_QEMR) == 0) && | |
501 | (edma_read(ctlr, EDMA_CCERR) == 0)) | |
a4768d22 | 502 | break; |
a4768d22 KH |
503 | cnt++; |
504 | if (cnt > 10) | |
505 | break; | |
506 | } | |
60902a2c | 507 | edma_write(ctlr, EDMA_EEVAL, 1); |
a4768d22 KH |
508 | return IRQ_HANDLED; |
509 | } | |
510 | ||
134ce221 SP |
511 | static int reserve_contiguous_slots(int ctlr, unsigned int id, |
512 | unsigned int num_slots, | |
513 | unsigned int start_slot) | |
213765d7 SP |
514 | { |
515 | int i, j; | |
134ce221 SP |
516 | unsigned int count = num_slots; |
517 | int stop_slot = start_slot; | |
cc93fc3f | 518 | DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); |
213765d7 | 519 | |
3f68b98a | 520 | for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) { |
213765d7 | 521 | j = EDMA_CHAN_SLOT(i); |
3f68b98a | 522 | if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) { |
cc93fc3f | 523 | /* Record our current beginning slot */ |
134ce221 SP |
524 | if (count == num_slots) |
525 | stop_slot = i; | |
cc93fc3f | 526 | |
213765d7 | 527 | count--; |
cc93fc3f SP |
528 | set_bit(j, tmp_inuse); |
529 | ||
213765d7 SP |
530 | if (count == 0) |
531 | break; | |
cc93fc3f SP |
532 | } else { |
533 | clear_bit(j, tmp_inuse); | |
534 | ||
535 | if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { | |
134ce221 | 536 | stop_slot = i; |
cc93fc3f | 537 | break; |
243bc654 | 538 | } else { |
134ce221 | 539 | count = num_slots; |
243bc654 | 540 | } |
cc93fc3f | 541 | } |
213765d7 SP |
542 | } |
543 | ||
544 | /* | |
545 | * We have to clear any bits that we set | |
134ce221 SP |
546 | * if we run out parameter RAM slots, i.e we do find a set |
547 | * of contiguous parameter RAM slots but do not find the exact number | |
548 | * requested as we may reach the total number of parameter RAM slots | |
213765d7 | 549 | */ |
3f68b98a | 550 | if (i == edma_cc[ctlr]->num_slots) |
134ce221 | 551 | stop_slot = i; |
cc93fc3f | 552 | |
98e3b339 AM |
553 | j = start_slot; |
554 | for_each_set_bit_from(j, tmp_inuse, stop_slot) | |
555 | clear_bit(j, edma_cc[ctlr]->edma_inuse); | |
213765d7 | 556 | |
cc93fc3f | 557 | if (count) |
213765d7 | 558 | return -EBUSY; |
213765d7 | 559 | |
134ce221 | 560 | for (j = i - num_slots + 1; j <= i; ++j) |
213765d7 SP |
561 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j), |
562 | &dummy_paramset, PARM_SIZE); | |
563 | ||
134ce221 | 564 | return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1); |
213765d7 SP |
565 | } |
566 | ||
f900d552 SR |
567 | static int prepare_unused_channel_list(struct device *dev, void *data) |
568 | { | |
569 | struct platform_device *pdev = to_platform_device(dev); | |
6cdaca48 JF |
570 | int i, count, ctlr; |
571 | struct of_phandle_args dma_spec; | |
f900d552 | 572 | |
6cdaca48 JF |
573 | if (dev->of_node) { |
574 | count = of_property_count_strings(dev->of_node, "dma-names"); | |
575 | if (count < 0) | |
576 | return 0; | |
577 | for (i = 0; i < count; i++) { | |
578 | if (of_parse_phandle_with_args(dev->of_node, "dmas", | |
579 | "#dma-cells", i, | |
580 | &dma_spec)) | |
581 | continue; | |
582 | ||
583 | if (!of_match_node(edma_of_ids, dma_spec.np)) { | |
584 | of_node_put(dma_spec.np); | |
585 | continue; | |
586 | } | |
587 | ||
588 | clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]), | |
589 | edma_cc[0]->edma_unused); | |
590 | of_node_put(dma_spec.np); | |
591 | } | |
592 | return 0; | |
593 | } | |
594 | ||
595 | /* For non-OF case */ | |
f900d552 SR |
596 | for (i = 0; i < pdev->num_resources; i++) { |
597 | if ((pdev->resource[i].flags & IORESOURCE_DMA) && | |
598 | (int)pdev->resource[i].start >= 0) { | |
599 | ctlr = EDMA_CTLR(pdev->resource[i].start); | |
600 | clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), | |
6cdaca48 | 601 | edma_cc[ctlr]->edma_unused); |
f900d552 SR |
602 | } |
603 | } | |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
a4768d22 KH |
608 | /*-----------------------------------------------------------------------*/ |
609 | ||
f900d552 SR |
610 | static bool unused_chan_list_done; |
611 | ||
a4768d22 KH |
612 | /* Resource alloc/free: dma channels, parameter RAM slots */ |
613 | ||
614 | /** | |
615 | * edma_alloc_channel - allocate DMA channel and paired parameter RAM | |
616 | * @channel: specific channel to allocate; negative for "any unmapped channel" | |
617 | * @callback: optional; to be issued on DMA completion or errors | |
618 | * @data: passed to callback | |
619 | * @eventq_no: an EVENTQ_* constant, used to choose which Transfer | |
620 | * Controller (TC) executes requests using this channel. Use | |
621 | * EVENTQ_DEFAULT unless you really need a high priority queue. | |
622 | * | |
623 | * This allocates a DMA channel and its associated parameter RAM slot. | |
624 | * The parameter RAM is initialized to hold a dummy transfer. | |
625 | * | |
626 | * Normal use is to pass a specific channel number as @channel, to make | |
627 | * use of hardware events mapped to that channel. When the channel will | |
628 | * be used only for software triggering or event chaining, channels not | |
629 | * mapped to hardware events (or mapped to unused events) are preferable. | |
630 | * | |
631 | * DMA transfers start from a channel using edma_start(), or by | |
632 | * chaining. When the transfer described in that channel's parameter RAM | |
633 | * slot completes, that slot's data may be reloaded through a link. | |
634 | * | |
635 | * DMA errors are only reported to the @callback associated with the | |
636 | * channel driving that transfer, but transfer completion callbacks can | |
637 | * be sent to another channel under control of the TCC field in | |
638 | * the option word of the transfer's parameter RAM set. Drivers must not | |
639 | * use DMA transfer completion callbacks for channels they did not allocate. | |
640 | * (The same applies to TCC codes used in transfer chaining.) | |
641 | * | |
642 | * Returns the number of the channel, else negative errno. | |
643 | */ | |
644 | int edma_alloc_channel(int channel, | |
645 | void (*callback)(unsigned channel, u16 ch_status, void *data), | |
646 | void *data, | |
647 | enum dma_event_q eventq_no) | |
648 | { | |
447f18f1 | 649 | unsigned i, done = 0, ctlr = 0; |
f900d552 SR |
650 | int ret = 0; |
651 | ||
652 | if (!unused_chan_list_done) { | |
653 | /* | |
654 | * Scan all the platform devices to find out the EDMA channels | |
655 | * used and clear them in the unused list, making the rest | |
656 | * available for ARM usage. | |
657 | */ | |
658 | ret = bus_for_each_dev(&platform_bus_type, NULL, NULL, | |
659 | prepare_unused_channel_list); | |
660 | if (ret < 0) | |
661 | return ret; | |
662 | ||
663 | unused_chan_list_done = true; | |
664 | } | |
60902a2c SR |
665 | |
666 | if (channel >= 0) { | |
667 | ctlr = EDMA_CTLR(channel); | |
668 | channel = EDMA_CHAN_SLOT(channel); | |
669 | } | |
670 | ||
a4768d22 | 671 | if (channel < 0) { |
2d517508 | 672 | for (i = 0; i < arch_num_cc; i++) { |
60902a2c SR |
673 | channel = 0; |
674 | for (;;) { | |
3f68b98a SN |
675 | channel = find_next_bit(edma_cc[i]->edma_unused, |
676 | edma_cc[i]->num_channels, | |
60902a2c | 677 | channel); |
3f68b98a | 678 | if (channel == edma_cc[i]->num_channels) |
447f18f1 | 679 | break; |
60902a2c | 680 | if (!test_and_set_bit(channel, |
3f68b98a | 681 | edma_cc[i]->edma_inuse)) { |
60902a2c SR |
682 | done = 1; |
683 | ctlr = i; | |
684 | break; | |
685 | } | |
686 | channel++; | |
687 | } | |
688 | if (done) | |
a4768d22 | 689 | break; |
a4768d22 | 690 | } |
447f18f1 SR |
691 | if (!done) |
692 | return -ENOMEM; | |
3f68b98a | 693 | } else if (channel >= edma_cc[ctlr]->num_channels) { |
a4768d22 | 694 | return -EINVAL; |
3f68b98a | 695 | } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) { |
a4768d22 KH |
696 | return -EBUSY; |
697 | } | |
698 | ||
699 | /* ensure access through shadow region 0 */ | |
d78a9494 | 700 | edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); |
a4768d22 KH |
701 | |
702 | /* ensure no events are pending */ | |
60902a2c SR |
703 | edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); |
704 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), | |
a4768d22 KH |
705 | &dummy_paramset, PARM_SIZE); |
706 | ||
707 | if (callback) | |
60902a2c SR |
708 | setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), |
709 | callback, data); | |
a4768d22 | 710 | |
60902a2c | 711 | map_dmach_queue(ctlr, channel, eventq_no); |
a4768d22 | 712 | |
0e6cb8d2 | 713 | return EDMA_CTLR_CHAN(ctlr, channel); |
a4768d22 KH |
714 | } |
715 | EXPORT_SYMBOL(edma_alloc_channel); | |
716 | ||
717 | ||
718 | /** | |
719 | * edma_free_channel - deallocate DMA channel | |
720 | * @channel: dma channel returned from edma_alloc_channel() | |
721 | * | |
722 | * This deallocates the DMA channel and associated parameter RAM slot | |
723 | * allocated by edma_alloc_channel(). | |
724 | * | |
725 | * Callers are responsible for ensuring the channel is inactive, and | |
726 | * will not be reactivated by linking, chaining, or software calls to | |
727 | * edma_start(). | |
728 | */ | |
729 | void edma_free_channel(unsigned channel) | |
730 | { | |
60902a2c SR |
731 | unsigned ctlr; |
732 | ||
733 | ctlr = EDMA_CTLR(channel); | |
734 | channel = EDMA_CHAN_SLOT(channel); | |
735 | ||
3f68b98a | 736 | if (channel >= edma_cc[ctlr]->num_channels) |
a4768d22 KH |
737 | return; |
738 | ||
739 | setup_dma_interrupt(channel, NULL, NULL); | |
740 | /* REVISIT should probably take out of shadow region 0 */ | |
741 | ||
60902a2c | 742 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), |
a4768d22 | 743 | &dummy_paramset, PARM_SIZE); |
3f68b98a | 744 | clear_bit(channel, edma_cc[ctlr]->edma_inuse); |
a4768d22 KH |
745 | } |
746 | EXPORT_SYMBOL(edma_free_channel); | |
747 | ||
748 | /** | |
749 | * edma_alloc_slot - allocate DMA parameter RAM | |
750 | * @slot: specific slot to allocate; negative for "any unused slot" | |
751 | * | |
752 | * This allocates a parameter RAM slot, initializing it to hold a | |
753 | * dummy transfer. Slots allocated using this routine have not been | |
754 | * mapped to a hardware DMA channel, and will normally be used by | |
755 | * linking to them from a slot associated with a DMA channel. | |
756 | * | |
757 | * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific | |
758 | * slots may be allocated on behalf of DSP firmware. | |
759 | * | |
760 | * Returns the number of the slot, else negative errno. | |
761 | */ | |
60902a2c | 762 | int edma_alloc_slot(unsigned ctlr, int slot) |
a4768d22 | 763 | { |
06955277 MP |
764 | if (!edma_cc[ctlr]) |
765 | return -EINVAL; | |
766 | ||
60902a2c SR |
767 | if (slot >= 0) |
768 | slot = EDMA_CHAN_SLOT(slot); | |
769 | ||
a4768d22 | 770 | if (slot < 0) { |
3f68b98a | 771 | slot = edma_cc[ctlr]->num_channels; |
a4768d22 | 772 | for (;;) { |
3f68b98a SN |
773 | slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse, |
774 | edma_cc[ctlr]->num_slots, slot); | |
775 | if (slot == edma_cc[ctlr]->num_slots) | |
a4768d22 | 776 | return -ENOMEM; |
3f68b98a | 777 | if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) |
a4768d22 KH |
778 | break; |
779 | } | |
3f68b98a SN |
780 | } else if (slot < edma_cc[ctlr]->num_channels || |
781 | slot >= edma_cc[ctlr]->num_slots) { | |
a4768d22 | 782 | return -EINVAL; |
3f68b98a | 783 | } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) { |
a4768d22 KH |
784 | return -EBUSY; |
785 | } | |
786 | ||
60902a2c | 787 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
a4768d22 KH |
788 | &dummy_paramset, PARM_SIZE); |
789 | ||
60902a2c | 790 | return EDMA_CTLR_CHAN(ctlr, slot); |
a4768d22 KH |
791 | } |
792 | EXPORT_SYMBOL(edma_alloc_slot); | |
793 | ||
794 | /** | |
795 | * edma_free_slot - deallocate DMA parameter RAM | |
796 | * @slot: parameter RAM slot returned from edma_alloc_slot() | |
797 | * | |
798 | * This deallocates the parameter RAM slot allocated by edma_alloc_slot(). | |
799 | * Callers are responsible for ensuring the slot is inactive, and will | |
800 | * not be activated. | |
801 | */ | |
802 | void edma_free_slot(unsigned slot) | |
803 | { | |
60902a2c SR |
804 | unsigned ctlr; |
805 | ||
806 | ctlr = EDMA_CTLR(slot); | |
807 | slot = EDMA_CHAN_SLOT(slot); | |
808 | ||
3f68b98a SN |
809 | if (slot < edma_cc[ctlr]->num_channels || |
810 | slot >= edma_cc[ctlr]->num_slots) | |
a4768d22 KH |
811 | return; |
812 | ||
60902a2c | 813 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
a4768d22 | 814 | &dummy_paramset, PARM_SIZE); |
3f68b98a | 815 | clear_bit(slot, edma_cc[ctlr]->edma_inuse); |
a4768d22 KH |
816 | } |
817 | EXPORT_SYMBOL(edma_free_slot); | |
818 | ||
213765d7 SP |
819 | |
820 | /** | |
821 | * edma_alloc_cont_slots- alloc contiguous parameter RAM slots | |
822 | * The API will return the starting point of a set of | |
134ce221 | 823 | * contiguous parameter RAM slots that have been requested |
213765d7 SP |
824 | * |
825 | * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT | |
826 | * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT | |
134ce221 SP |
827 | * @count: number of contiguous Paramter RAM slots |
828 | * @slot - the start value of Parameter RAM slot that should be passed if id | |
213765d7 SP |
829 | * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT |
830 | * | |
831 | * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of | |
134ce221 SP |
832 | * contiguous Parameter RAM slots from parameter RAM 64 in the case of |
833 | * DaVinci SOCs and 32 in the case of DA8xx SOCs. | |
213765d7 SP |
834 | * |
835 | * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a | |
134ce221 | 836 | * set of contiguous parameter RAM slots from the "slot" that is passed as an |
213765d7 SP |
837 | * argument to the API. |
838 | * | |
839 | * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries | |
134ce221 | 840 | * starts looking for a set of contiguous parameter RAMs from the "slot" |
213765d7 | 841 | * that is passed as an argument to the API. On failure the API will try to |
134ce221 SP |
842 | * find a set of contiguous Parameter RAM slots from the remaining Parameter |
843 | * RAM slots | |
213765d7 SP |
844 | */ |
845 | int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) | |
846 | { | |
847 | /* | |
848 | * The start slot requested should be greater than | |
849 | * the number of channels and lesser than the total number | |
850 | * of slots | |
851 | */ | |
6b0cf4e9 | 852 | if ((id != EDMA_CONT_PARAMS_ANY) && |
3f68b98a SN |
853 | (slot < edma_cc[ctlr]->num_channels || |
854 | slot >= edma_cc[ctlr]->num_slots)) | |
213765d7 SP |
855 | return -EINVAL; |
856 | ||
857 | /* | |
134ce221 | 858 | * The number of parameter RAM slots requested cannot be less than 1 |
213765d7 SP |
859 | * and cannot be more than the number of slots minus the number of |
860 | * channels | |
861 | */ | |
862 | if (count < 1 || count > | |
3f68b98a | 863 | (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels)) |
213765d7 SP |
864 | return -EINVAL; |
865 | ||
866 | switch (id) { | |
867 | case EDMA_CONT_PARAMS_ANY: | |
134ce221 | 868 | return reserve_contiguous_slots(ctlr, id, count, |
3f68b98a | 869 | edma_cc[ctlr]->num_channels); |
213765d7 SP |
870 | case EDMA_CONT_PARAMS_FIXED_EXACT: |
871 | case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: | |
134ce221 | 872 | return reserve_contiguous_slots(ctlr, id, count, slot); |
213765d7 SP |
873 | default: |
874 | return -EINVAL; | |
875 | } | |
876 | ||
877 | } | |
878 | EXPORT_SYMBOL(edma_alloc_cont_slots); | |
879 | ||
880 | /** | |
134ce221 SP |
881 | * edma_free_cont_slots - deallocate DMA parameter RAM slots |
882 | * @slot: first parameter RAM of a set of parameter RAM slots to be freed | |
883 | * @count: the number of contiguous parameter RAM slots to be freed | |
213765d7 SP |
884 | * |
885 | * This deallocates the parameter RAM slots allocated by | |
886 | * edma_alloc_cont_slots. | |
887 | * Callers/applications need to keep track of sets of contiguous | |
134ce221 | 888 | * parameter RAM slots that have been allocated using the edma_alloc_cont_slots |
213765d7 SP |
889 | * API. |
890 | * Callers are responsible for ensuring the slots are inactive, and will | |
891 | * not be activated. | |
892 | */ | |
893 | int edma_free_cont_slots(unsigned slot, int count) | |
894 | { | |
51c99e04 | 895 | unsigned ctlr, slot_to_free; |
213765d7 SP |
896 | int i; |
897 | ||
898 | ctlr = EDMA_CTLR(slot); | |
899 | slot = EDMA_CHAN_SLOT(slot); | |
900 | ||
3f68b98a SN |
901 | if (slot < edma_cc[ctlr]->num_channels || |
902 | slot >= edma_cc[ctlr]->num_slots || | |
213765d7 SP |
903 | count < 1) |
904 | return -EINVAL; | |
905 | ||
906 | for (i = slot; i < slot + count; ++i) { | |
907 | ctlr = EDMA_CTLR(i); | |
51c99e04 | 908 | slot_to_free = EDMA_CHAN_SLOT(i); |
213765d7 | 909 | |
51c99e04 | 910 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free), |
213765d7 | 911 | &dummy_paramset, PARM_SIZE); |
3f68b98a | 912 | clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse); |
213765d7 SP |
913 | } |
914 | ||
915 | return 0; | |
916 | } | |
917 | EXPORT_SYMBOL(edma_free_cont_slots); | |
918 | ||
a4768d22 KH |
919 | /*-----------------------------------------------------------------------*/ |
920 | ||
921 | /* Parameter RAM operations (i) -- read/write partial slots */ | |
922 | ||
923 | /** | |
924 | * edma_set_src - set initial DMA source address in parameter RAM slot | |
925 | * @slot: parameter RAM slot being configured | |
926 | * @src_port: physical address of source (memory, controller FIFO, etc) | |
927 | * @addressMode: INCR, except in very rare cases | |
928 | * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the | |
929 | * width to use when addressing the fifo (e.g. W8BIT, W32BIT) | |
930 | * | |
931 | * Note that the source address is modified during the DMA transfer | |
932 | * according to edma_set_src_index(). | |
933 | */ | |
934 | void edma_set_src(unsigned slot, dma_addr_t src_port, | |
935 | enum address_mode mode, enum fifo_width width) | |
936 | { | |
60902a2c SR |
937 | unsigned ctlr; |
938 | ||
939 | ctlr = EDMA_CTLR(slot); | |
940 | slot = EDMA_CHAN_SLOT(slot); | |
941 | ||
3f68b98a | 942 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 943 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); |
a4768d22 KH |
944 | |
945 | if (mode) { | |
946 | /* set SAM and program FWID */ | |
947 | i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8)); | |
948 | } else { | |
949 | /* clear SAM */ | |
950 | i &= ~SAM; | |
951 | } | |
60902a2c | 952 | edma_parm_write(ctlr, PARM_OPT, slot, i); |
a4768d22 KH |
953 | |
954 | /* set the source port address | |
955 | in source register of param structure */ | |
60902a2c | 956 | edma_parm_write(ctlr, PARM_SRC, slot, src_port); |
a4768d22 KH |
957 | } |
958 | } | |
959 | EXPORT_SYMBOL(edma_set_src); | |
960 | ||
961 | /** | |
962 | * edma_set_dest - set initial DMA destination address in parameter RAM slot | |
963 | * @slot: parameter RAM slot being configured | |
964 | * @dest_port: physical address of destination (memory, controller FIFO, etc) | |
965 | * @addressMode: INCR, except in very rare cases | |
966 | * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the | |
967 | * width to use when addressing the fifo (e.g. W8BIT, W32BIT) | |
968 | * | |
969 | * Note that the destination address is modified during the DMA transfer | |
970 | * according to edma_set_dest_index(). | |
971 | */ | |
972 | void edma_set_dest(unsigned slot, dma_addr_t dest_port, | |
973 | enum address_mode mode, enum fifo_width width) | |
974 | { | |
60902a2c SR |
975 | unsigned ctlr; |
976 | ||
977 | ctlr = EDMA_CTLR(slot); | |
978 | slot = EDMA_CHAN_SLOT(slot); | |
979 | ||
3f68b98a | 980 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 981 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); |
a4768d22 KH |
982 | |
983 | if (mode) { | |
984 | /* set DAM and program FWID */ | |
985 | i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8)); | |
986 | } else { | |
987 | /* clear DAM */ | |
988 | i &= ~DAM; | |
989 | } | |
60902a2c | 990 | edma_parm_write(ctlr, PARM_OPT, slot, i); |
a4768d22 KH |
991 | /* set the destination port address |
992 | in dest register of param structure */ | |
60902a2c | 993 | edma_parm_write(ctlr, PARM_DST, slot, dest_port); |
a4768d22 KH |
994 | } |
995 | } | |
996 | EXPORT_SYMBOL(edma_set_dest); | |
997 | ||
998 | /** | |
cdae05a0 | 999 | * edma_get_position - returns the current transfer point |
a4768d22 | 1000 | * @slot: parameter RAM slot being examined |
cdae05a0 | 1001 | * @dst: true selects the dest position, false the source |
a4768d22 | 1002 | * |
cdae05a0 | 1003 | * Returns the position of the current active slot |
a4768d22 | 1004 | */ |
cdae05a0 | 1005 | dma_addr_t edma_get_position(unsigned slot, bool dst) |
a4768d22 | 1006 | { |
cdae05a0 | 1007 | u32 offs, ctlr = EDMA_CTLR(slot); |
60902a2c | 1008 | |
60902a2c | 1009 | slot = EDMA_CHAN_SLOT(slot); |
a4768d22 | 1010 | |
cdae05a0 TG |
1011 | offs = PARM_OFFSET(slot); |
1012 | offs += dst ? PARM_DST : PARM_SRC; | |
1013 | ||
1014 | return edma_read(ctlr, offs); | |
a4768d22 | 1015 | } |
a4768d22 KH |
1016 | |
1017 | /** | |
1018 | * edma_set_src_index - configure DMA source address indexing | |
1019 | * @slot: parameter RAM slot being configured | |
1020 | * @src_bidx: byte offset between source arrays in a frame | |
1021 | * @src_cidx: byte offset between source frames in a block | |
1022 | * | |
1023 | * Offsets are specified to support either contiguous or discontiguous | |
1024 | * memory transfers, or repeated access to a hardware register, as needed. | |
1025 | * When accessing hardware registers, both offsets are normally zero. | |
1026 | */ | |
1027 | void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx) | |
1028 | { | |
60902a2c SR |
1029 | unsigned ctlr; |
1030 | ||
1031 | ctlr = EDMA_CTLR(slot); | |
1032 | slot = EDMA_CHAN_SLOT(slot); | |
1033 | ||
3f68b98a | 1034 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 1035 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, |
a4768d22 | 1036 | 0xffff0000, src_bidx); |
60902a2c | 1037 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
a4768d22 KH |
1038 | 0xffff0000, src_cidx); |
1039 | } | |
1040 | } | |
1041 | EXPORT_SYMBOL(edma_set_src_index); | |
1042 | ||
1043 | /** | |
1044 | * edma_set_dest_index - configure DMA destination address indexing | |
1045 | * @slot: parameter RAM slot being configured | |
1046 | * @dest_bidx: byte offset between destination arrays in a frame | |
1047 | * @dest_cidx: byte offset between destination frames in a block | |
1048 | * | |
1049 | * Offsets are specified to support either contiguous or discontiguous | |
1050 | * memory transfers, or repeated access to a hardware register, as needed. | |
1051 | * When accessing hardware registers, both offsets are normally zero. | |
1052 | */ | |
1053 | void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx) | |
1054 | { | |
60902a2c SR |
1055 | unsigned ctlr; |
1056 | ||
1057 | ctlr = EDMA_CTLR(slot); | |
1058 | slot = EDMA_CHAN_SLOT(slot); | |
1059 | ||
3f68b98a | 1060 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 1061 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, |
a4768d22 | 1062 | 0x0000ffff, dest_bidx << 16); |
60902a2c | 1063 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
a4768d22 KH |
1064 | 0x0000ffff, dest_cidx << 16); |
1065 | } | |
1066 | } | |
1067 | EXPORT_SYMBOL(edma_set_dest_index); | |
1068 | ||
1069 | /** | |
1070 | * edma_set_transfer_params - configure DMA transfer parameters | |
1071 | * @slot: parameter RAM slot being configured | |
1072 | * @acnt: how many bytes per array (at least one) | |
1073 | * @bcnt: how many arrays per frame (at least one) | |
1074 | * @ccnt: how many frames per block (at least one) | |
1075 | * @bcnt_rld: used only for A-Synchronized transfers; this specifies | |
1076 | * the value to reload into bcnt when it decrements to zero | |
1077 | * @sync_mode: ASYNC or ABSYNC | |
1078 | * | |
1079 | * See the EDMA3 documentation to understand how to configure and link | |
1080 | * transfers using the fields in PaRAM slots. If you are not doing it | |
1081 | * all at once with edma_write_slot(), you will use this routine | |
1082 | * plus two calls each for source and destination, setting the initial | |
1083 | * address and saying how to index that address. | |
1084 | * | |
1085 | * An example of an A-Synchronized transfer is a serial link using a | |
1086 | * single word shift register. In that case, @acnt would be equal to | |
1087 | * that word size; the serial controller issues a DMA synchronization | |
1088 | * event to transfer each word, and memory access by the DMA transfer | |
1089 | * controller will be word-at-a-time. | |
1090 | * | |
1091 | * An example of an AB-Synchronized transfer is a device using a FIFO. | |
1092 | * In that case, @acnt equals the FIFO width and @bcnt equals its depth. | |
1093 | * The controller with the FIFO issues DMA synchronization events when | |
1094 | * the FIFO threshold is reached, and the DMA transfer controller will | |
1095 | * transfer one frame to (or from) the FIFO. It will probably use | |
1096 | * efficient burst modes to access memory. | |
1097 | */ | |
1098 | void edma_set_transfer_params(unsigned slot, | |
1099 | u16 acnt, u16 bcnt, u16 ccnt, | |
1100 | u16 bcnt_rld, enum sync_dimension sync_mode) | |
1101 | { | |
60902a2c SR |
1102 | unsigned ctlr; |
1103 | ||
1104 | ctlr = EDMA_CTLR(slot); | |
1105 | slot = EDMA_CHAN_SLOT(slot); | |
1106 | ||
3f68b98a | 1107 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 1108 | edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, |
a4768d22 KH |
1109 | 0x0000ffff, bcnt_rld << 16); |
1110 | if (sync_mode == ASYNC) | |
60902a2c | 1111 | edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); |
a4768d22 | 1112 | else |
60902a2c | 1113 | edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); |
a4768d22 | 1114 | /* Set the acount, bcount, ccount registers */ |
60902a2c SR |
1115 | edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); |
1116 | edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); | |
a4768d22 KH |
1117 | } |
1118 | } | |
1119 | EXPORT_SYMBOL(edma_set_transfer_params); | |
1120 | ||
1121 | /** | |
1122 | * edma_link - link one parameter RAM slot to another | |
1123 | * @from: parameter RAM slot originating the link | |
1124 | * @to: parameter RAM slot which is the link target | |
1125 | * | |
1126 | * The originating slot should not be part of any active DMA transfer. | |
1127 | */ | |
1128 | void edma_link(unsigned from, unsigned to) | |
1129 | { | |
60902a2c SR |
1130 | unsigned ctlr_from, ctlr_to; |
1131 | ||
1132 | ctlr_from = EDMA_CTLR(from); | |
1133 | from = EDMA_CHAN_SLOT(from); | |
1134 | ctlr_to = EDMA_CTLR(to); | |
1135 | to = EDMA_CHAN_SLOT(to); | |
1136 | ||
3f68b98a | 1137 | if (from >= edma_cc[ctlr_from]->num_slots) |
a4768d22 | 1138 | return; |
3f68b98a | 1139 | if (to >= edma_cc[ctlr_to]->num_slots) |
a4768d22 | 1140 | return; |
60902a2c SR |
1141 | edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, |
1142 | PARM_OFFSET(to)); | |
a4768d22 KH |
1143 | } |
1144 | EXPORT_SYMBOL(edma_link); | |
1145 | ||
1146 | /** | |
1147 | * edma_unlink - cut link from one parameter RAM slot | |
1148 | * @from: parameter RAM slot originating the link | |
1149 | * | |
1150 | * The originating slot should not be part of any active DMA transfer. | |
1151 | * Its link is set to 0xffff. | |
1152 | */ | |
1153 | void edma_unlink(unsigned from) | |
1154 | { | |
60902a2c SR |
1155 | unsigned ctlr; |
1156 | ||
1157 | ctlr = EDMA_CTLR(from); | |
1158 | from = EDMA_CHAN_SLOT(from); | |
1159 | ||
3f68b98a | 1160 | if (from >= edma_cc[ctlr]->num_slots) |
a4768d22 | 1161 | return; |
60902a2c | 1162 | edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); |
a4768d22 KH |
1163 | } |
1164 | EXPORT_SYMBOL(edma_unlink); | |
1165 | ||
1166 | /*-----------------------------------------------------------------------*/ | |
1167 | ||
1168 | /* Parameter RAM operations (ii) -- read/write whole parameter sets */ | |
1169 | ||
1170 | /** | |
1171 | * edma_write_slot - write parameter RAM data for slot | |
1172 | * @slot: number of parameter RAM slot being modified | |
1173 | * @param: data to be written into parameter RAM slot | |
1174 | * | |
1175 | * Use this to assign all parameters of a transfer at once. This | |
1176 | * allows more efficient setup of transfers than issuing multiple | |
1177 | * calls to set up those parameters in small pieces, and provides | |
1178 | * complete control over all transfer options. | |
1179 | */ | |
1180 | void edma_write_slot(unsigned slot, const struct edmacc_param *param) | |
1181 | { | |
60902a2c SR |
1182 | unsigned ctlr; |
1183 | ||
1184 | ctlr = EDMA_CTLR(slot); | |
1185 | slot = EDMA_CHAN_SLOT(slot); | |
1186 | ||
3f68b98a | 1187 | if (slot >= edma_cc[ctlr]->num_slots) |
a4768d22 | 1188 | return; |
60902a2c SR |
1189 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, |
1190 | PARM_SIZE); | |
a4768d22 KH |
1191 | } |
1192 | EXPORT_SYMBOL(edma_write_slot); | |
1193 | ||
1194 | /** | |
1195 | * edma_read_slot - read parameter RAM data from slot | |
1196 | * @slot: number of parameter RAM slot being copied | |
1197 | * @param: where to store copy of parameter RAM data | |
1198 | * | |
1199 | * Use this to read data from a parameter RAM slot, perhaps to | |
1200 | * save them as a template for later reuse. | |
1201 | */ | |
1202 | void edma_read_slot(unsigned slot, struct edmacc_param *param) | |
1203 | { | |
60902a2c SR |
1204 | unsigned ctlr; |
1205 | ||
1206 | ctlr = EDMA_CTLR(slot); | |
1207 | slot = EDMA_CHAN_SLOT(slot); | |
1208 | ||
3f68b98a | 1209 | if (slot >= edma_cc[ctlr]->num_slots) |
a4768d22 | 1210 | return; |
60902a2c SR |
1211 | memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
1212 | PARM_SIZE); | |
a4768d22 KH |
1213 | } |
1214 | EXPORT_SYMBOL(edma_read_slot); | |
1215 | ||
1216 | /*-----------------------------------------------------------------------*/ | |
1217 | ||
1218 | /* Various EDMA channel control operations */ | |
1219 | ||
1220 | /** | |
1221 | * edma_pause - pause dma on a channel | |
1222 | * @channel: on which edma_start() has been called | |
1223 | * | |
1224 | * This temporarily disables EDMA hardware events on the specified channel, | |
1225 | * preventing them from triggering new transfers on its behalf | |
1226 | */ | |
1227 | void edma_pause(unsigned channel) | |
1228 | { | |
60902a2c SR |
1229 | unsigned ctlr; |
1230 | ||
1231 | ctlr = EDMA_CTLR(channel); | |
1232 | channel = EDMA_CHAN_SLOT(channel); | |
1233 | ||
3f68b98a | 1234 | if (channel < edma_cc[ctlr]->num_channels) { |
d78a9494 | 1235 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 | 1236 | |
60902a2c | 1237 | edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); |
a4768d22 KH |
1238 | } |
1239 | } | |
1240 | EXPORT_SYMBOL(edma_pause); | |
1241 | ||
1242 | /** | |
1243 | * edma_resume - resumes dma on a paused channel | |
1244 | * @channel: on which edma_pause() has been called | |
1245 | * | |
1246 | * This re-enables EDMA hardware events on the specified channel. | |
1247 | */ | |
1248 | void edma_resume(unsigned channel) | |
1249 | { | |
60902a2c SR |
1250 | unsigned ctlr; |
1251 | ||
1252 | ctlr = EDMA_CTLR(channel); | |
1253 | channel = EDMA_CHAN_SLOT(channel); | |
1254 | ||
3f68b98a | 1255 | if (channel < edma_cc[ctlr]->num_channels) { |
d78a9494 | 1256 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 | 1257 | |
60902a2c | 1258 | edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); |
a4768d22 KH |
1259 | } |
1260 | } | |
1261 | EXPORT_SYMBOL(edma_resume); | |
1262 | ||
96874b9a JF |
1263 | int edma_trigger_channel(unsigned channel) |
1264 | { | |
1265 | unsigned ctlr; | |
1266 | unsigned int mask; | |
1267 | ||
1268 | ctlr = EDMA_CTLR(channel); | |
1269 | channel = EDMA_CHAN_SLOT(channel); | |
1270 | mask = BIT(channel & 0x1f); | |
1271 | ||
1272 | edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask); | |
1273 | ||
1274 | pr_debug("EDMA: ESR%d %08x\n", (channel >> 5), | |
1275 | edma_shadow0_read_array(ctlr, SH_ESR, (channel >> 5))); | |
1276 | return 0; | |
1277 | } | |
1278 | EXPORT_SYMBOL(edma_trigger_channel); | |
1279 | ||
a4768d22 KH |
1280 | /** |
1281 | * edma_start - start dma on a channel | |
1282 | * @channel: channel being activated | |
1283 | * | |
1284 | * Channels with event associations will be triggered by their hardware | |
1285 | * events, and channels without such associations will be triggered by | |
1286 | * software. (At this writing there is no interface for using software | |
1287 | * triggers except with channels that don't support hardware triggers.) | |
1288 | * | |
1289 | * Returns zero on success, else negative errno. | |
1290 | */ | |
1291 | int edma_start(unsigned channel) | |
1292 | { | |
60902a2c SR |
1293 | unsigned ctlr; |
1294 | ||
1295 | ctlr = EDMA_CTLR(channel); | |
1296 | channel = EDMA_CHAN_SLOT(channel); | |
1297 | ||
3f68b98a | 1298 | if (channel < edma_cc[ctlr]->num_channels) { |
a4768d22 | 1299 | int j = channel >> 5; |
d78a9494 | 1300 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 KH |
1301 | |
1302 | /* EDMA channels without event association */ | |
3f68b98a | 1303 | if (test_bit(channel, edma_cc[ctlr]->edma_unused)) { |
a4768d22 | 1304 | pr_debug("EDMA: ESR%d %08x\n", j, |
60902a2c SR |
1305 | edma_shadow0_read_array(ctlr, SH_ESR, j)); |
1306 | edma_shadow0_write_array(ctlr, SH_ESR, j, mask); | |
a4768d22 KH |
1307 | return 0; |
1308 | } | |
1309 | ||
1310 | /* EDMA channel with event association */ | |
1311 | pr_debug("EDMA: ER%d %08x\n", j, | |
60902a2c | 1312 | edma_shadow0_read_array(ctlr, SH_ER, j)); |
bb17ef10 BN |
1313 | /* Clear any pending event or error */ |
1314 | edma_write_array(ctlr, EDMA_ECR, j, mask); | |
60902a2c | 1315 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
a4768d22 | 1316 | /* Clear any SER */ |
60902a2c SR |
1317 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
1318 | edma_shadow0_write_array(ctlr, SH_EESR, j, mask); | |
a4768d22 | 1319 | pr_debug("EDMA: EER%d %08x\n", j, |
60902a2c | 1320 | edma_shadow0_read_array(ctlr, SH_EER, j)); |
a4768d22 KH |
1321 | return 0; |
1322 | } | |
1323 | ||
1324 | return -EINVAL; | |
1325 | } | |
1326 | EXPORT_SYMBOL(edma_start); | |
1327 | ||
1328 | /** | |
1329 | * edma_stop - stops dma on the channel passed | |
1330 | * @channel: channel being deactivated | |
1331 | * | |
1332 | * When @lch is a channel, any active transfer is paused and | |
1333 | * all pending hardware events are cleared. The current transfer | |
1334 | * may not be resumed, and the channel's Parameter RAM should be | |
1335 | * reinitialized before being reused. | |
1336 | */ | |
1337 | void edma_stop(unsigned channel) | |
1338 | { | |
60902a2c SR |
1339 | unsigned ctlr; |
1340 | ||
1341 | ctlr = EDMA_CTLR(channel); | |
1342 | channel = EDMA_CHAN_SLOT(channel); | |
1343 | ||
3f68b98a | 1344 | if (channel < edma_cc[ctlr]->num_channels) { |
a4768d22 | 1345 | int j = channel >> 5; |
d78a9494 | 1346 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 | 1347 | |
60902a2c SR |
1348 | edma_shadow0_write_array(ctlr, SH_EECR, j, mask); |
1349 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); | |
1350 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); | |
1351 | edma_write_array(ctlr, EDMA_EMCR, j, mask); | |
a4768d22 | 1352 | |
c2d4bb9d JO |
1353 | /* clear possibly pending completion interrupt */ |
1354 | edma_shadow0_write_array(ctlr, SH_ICR, j, mask); | |
1355 | ||
a4768d22 | 1356 | pr_debug("EDMA: EER%d %08x\n", j, |
60902a2c | 1357 | edma_shadow0_read_array(ctlr, SH_EER, j)); |
a4768d22 KH |
1358 | |
1359 | /* REVISIT: consider guarding against inappropriate event | |
1360 | * chaining by overwriting with dummy_paramset. | |
1361 | */ | |
1362 | } | |
1363 | } | |
1364 | EXPORT_SYMBOL(edma_stop); | |
1365 | ||
1366 | /****************************************************************************** | |
1367 | * | |
1368 | * It cleans ParamEntry qand bring back EDMA to initial state if media has | |
1369 | * been removed before EDMA has finished.It is usedful for removable media. | |
1370 | * Arguments: | |
1371 | * ch_no - channel no | |
1372 | * | |
1373 | * Return: zero on success, or corresponding error no on failure | |
1374 | * | |
1375 | * FIXME this should not be needed ... edma_stop() should suffice. | |
1376 | * | |
1377 | *****************************************************************************/ | |
1378 | ||
1379 | void edma_clean_channel(unsigned channel) | |
1380 | { | |
60902a2c SR |
1381 | unsigned ctlr; |
1382 | ||
1383 | ctlr = EDMA_CTLR(channel); | |
1384 | channel = EDMA_CHAN_SLOT(channel); | |
1385 | ||
3f68b98a | 1386 | if (channel < edma_cc[ctlr]->num_channels) { |
a4768d22 | 1387 | int j = (channel >> 5); |
d78a9494 | 1388 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 KH |
1389 | |
1390 | pr_debug("EDMA: EMR%d %08x\n", j, | |
60902a2c SR |
1391 | edma_read_array(ctlr, EDMA_EMR, j)); |
1392 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); | |
a4768d22 | 1393 | /* Clear the corresponding EMR bits */ |
60902a2c | 1394 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
a4768d22 | 1395 | /* Clear any SER */ |
60902a2c | 1396 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
d78a9494 | 1397 | edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); |
a4768d22 KH |
1398 | } |
1399 | } | |
1400 | EXPORT_SYMBOL(edma_clean_channel); | |
1401 | ||
1402 | /* | |
1403 | * edma_clear_event - clear an outstanding event on the DMA channel | |
1404 | * Arguments: | |
1405 | * channel - channel number | |
1406 | */ | |
1407 | void edma_clear_event(unsigned channel) | |
1408 | { | |
60902a2c SR |
1409 | unsigned ctlr; |
1410 | ||
1411 | ctlr = EDMA_CTLR(channel); | |
1412 | channel = EDMA_CHAN_SLOT(channel); | |
1413 | ||
3f68b98a | 1414 | if (channel >= edma_cc[ctlr]->num_channels) |
a4768d22 KH |
1415 | return; |
1416 | if (channel < 32) | |
d78a9494 | 1417 | edma_write(ctlr, EDMA_ECR, BIT(channel)); |
a4768d22 | 1418 | else |
d78a9494 | 1419 | edma_write(ctlr, EDMA_ECRH, BIT(channel - 32)); |
a4768d22 KH |
1420 | } |
1421 | EXPORT_SYMBOL(edma_clear_event); | |
1422 | ||
eb3fe7de PU |
1423 | /* |
1424 | * edma_assign_channel_eventq - move given channel to desired eventq | |
1425 | * Arguments: | |
1426 | * channel - channel number | |
1427 | * eventq_no - queue to move the channel | |
1428 | * | |
1429 | * Can be used to move a channel to a selected event queue. | |
1430 | */ | |
1431 | void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no) | |
1432 | { | |
1433 | unsigned ctlr; | |
1434 | ||
1435 | ctlr = EDMA_CTLR(channel); | |
1436 | channel = EDMA_CHAN_SLOT(channel); | |
1437 | ||
1438 | if (channel >= edma_cc[ctlr]->num_channels) | |
1439 | return; | |
1440 | ||
1441 | /* default to low priority queue */ | |
1442 | if (eventq_no == EVENTQ_DEFAULT) | |
1443 | eventq_no = edma_cc[ctlr]->default_queue; | |
1444 | if (eventq_no >= edma_cc[ctlr]->num_tc) | |
1445 | return; | |
1446 | ||
1447 | map_dmach_queue(ctlr, channel, eventq_no); | |
1448 | } | |
1449 | EXPORT_SYMBOL(edma_assign_channel_eventq); | |
1450 | ||
6d10c395 | 1451 | static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, |
929a015b | 1452 | struct edma *edma_cc, int cc_id) |
6d10c395 PU |
1453 | { |
1454 | int i; | |
1455 | u32 value, cccfg; | |
1456 | s8 (*queue_priority_map)[2]; | |
1457 | ||
1458 | /* Decode the eDMA3 configuration from CCCFG register */ | |
929a015b | 1459 | cccfg = edma_read(cc_id, EDMA_CCCFG); |
6d10c395 PU |
1460 | |
1461 | value = GET_NUM_REGN(cccfg); | |
1462 | edma_cc->num_region = BIT(value); | |
1463 | ||
1464 | value = GET_NUM_DMACH(cccfg); | |
1465 | edma_cc->num_channels = BIT(value + 1); | |
1466 | ||
1467 | value = GET_NUM_PAENTRY(cccfg); | |
1468 | edma_cc->num_slots = BIT(value + 4); | |
1469 | ||
1470 | value = GET_NUM_EVQUE(cccfg); | |
1471 | edma_cc->num_tc = value + 1; | |
1472 | ||
929a015b PU |
1473 | dev_dbg(dev, "eDMA3 CC%d HW configuration (cccfg: 0x%08x):\n", cc_id, |
1474 | cccfg); | |
6d10c395 PU |
1475 | dev_dbg(dev, "num_region: %u\n", edma_cc->num_region); |
1476 | dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels); | |
1477 | dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots); | |
1478 | dev_dbg(dev, "num_tc: %u\n", edma_cc->num_tc); | |
1479 | ||
1480 | /* Nothing need to be done if queue priority is provided */ | |
1481 | if (pdata->queue_priority_mapping) | |
1482 | return 0; | |
1483 | ||
1484 | /* | |
1485 | * Configure TC/queue priority as follows: | |
1486 | * Q0 - priority 0 | |
1487 | * Q1 - priority 1 | |
1488 | * Q2 - priority 2 | |
1489 | * ... | |
1490 | * The meaning of priority numbers: 0 highest priority, 7 lowest | |
1491 | * priority. So Q0 is the highest priority queue and the last queue has | |
1492 | * the lowest priority. | |
1493 | */ | |
1494 | queue_priority_map = devm_kzalloc(dev, | |
1495 | (edma_cc->num_tc + 1) * sizeof(s8), | |
1496 | GFP_KERNEL); | |
1497 | if (!queue_priority_map) | |
1498 | return -ENOMEM; | |
1499 | ||
1500 | for (i = 0; i < edma_cc->num_tc; i++) { | |
1501 | queue_priority_map[i][0] = i; | |
1502 | queue_priority_map[i][1] = i; | |
1503 | } | |
1504 | queue_priority_map[i][0] = -1; | |
1505 | queue_priority_map[i][1] = -1; | |
1506 | ||
1507 | pdata->queue_priority_mapping = queue_priority_map; | |
85a70762 PU |
1508 | /* Default queue has the lowest priority */ |
1509 | pdata->default_queue = i - 1; | |
6d10c395 PU |
1510 | |
1511 | return 0; | |
1512 | } | |
1513 | ||
6cba4355 MP |
1514 | #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES) |
1515 | ||
cf7eb979 TG |
1516 | static int edma_xbar_event_map(struct device *dev, struct device_node *node, |
1517 | struct edma_soc_info *pdata, size_t sz) | |
2646a0e5 | 1518 | { |
cf7eb979 | 1519 | const char pname[] = "ti,edma-xbar-event-map"; |
2646a0e5 MP |
1520 | struct resource res; |
1521 | void __iomem *xbar; | |
cf7eb979 TG |
1522 | s16 (*xbar_chans)[2]; |
1523 | size_t nelm = sz / sizeof(s16); | |
2646a0e5 | 1524 | u32 shift, offset, mux; |
cf7eb979 | 1525 | int ret, i; |
2646a0e5 | 1526 | |
cf7eb979 | 1527 | xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL); |
2646a0e5 MP |
1528 | if (!xbar_chans) |
1529 | return -ENOMEM; | |
1530 | ||
1531 | ret = of_address_to_resource(node, 1, &res); | |
1532 | if (ret) | |
cf7eb979 | 1533 | return -ENOMEM; |
2646a0e5 MP |
1534 | |
1535 | xbar = devm_ioremap(dev, res.start, resource_size(&res)); | |
1536 | if (!xbar) | |
1537 | return -ENOMEM; | |
1538 | ||
cf7eb979 | 1539 | ret = of_property_read_u16_array(node, pname, (u16 *)xbar_chans, nelm); |
2646a0e5 MP |
1540 | if (ret) |
1541 | return -EIO; | |
1542 | ||
cf7eb979 TG |
1543 | /* Invalidate last entry for the other user of this mess */ |
1544 | nelm >>= 1; | |
1545 | xbar_chans[nelm][0] = xbar_chans[nelm][1] = -1; | |
1546 | ||
1547 | for (i = 0; i < nelm; i++) { | |
2646a0e5 MP |
1548 | shift = (xbar_chans[i][1] & 0x03) << 3; |
1549 | offset = xbar_chans[i][1] & 0xfffffffc; | |
1550 | mux = readl(xbar + offset); | |
1551 | mux &= ~(0xff << shift); | |
1552 | mux |= xbar_chans[i][0] << shift; | |
1553 | writel(mux, (xbar + offset)); | |
1554 | } | |
1555 | ||
cf7eb979 | 1556 | pdata->xbar_chans = (const s16 (*)[2]) xbar_chans; |
2646a0e5 MP |
1557 | return 0; |
1558 | } | |
1559 | ||
6cba4355 MP |
1560 | static int edma_of_parse_dt(struct device *dev, |
1561 | struct device_node *node, | |
1562 | struct edma_soc_info *pdata) | |
1563 | { | |
6d10c395 | 1564 | int ret = 0; |
2646a0e5 MP |
1565 | struct property *prop; |
1566 | size_t sz; | |
6cba4355 | 1567 | struct edma_rsv_info *rsv_info; |
6cba4355 MP |
1568 | |
1569 | rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL); | |
1570 | if (!rsv_info) | |
1571 | return -ENOMEM; | |
1572 | pdata->rsv = rsv_info; | |
1573 | ||
2646a0e5 MP |
1574 | prop = of_find_property(node, "ti,edma-xbar-event-map", &sz); |
1575 | if (prop) | |
1576 | ret = edma_xbar_event_map(dev, node, pdata, sz); | |
1577 | ||
6cba4355 MP |
1578 | return ret; |
1579 | } | |
1580 | ||
1581 | static struct of_dma_filter_info edma_filter_info = { | |
1582 | .filter_fn = edma_filter_fn, | |
1583 | }; | |
1584 | ||
1585 | static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, | |
1586 | struct device_node *node) | |
1587 | { | |
1588 | struct edma_soc_info *info; | |
1589 | int ret; | |
1590 | ||
1591 | info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL); | |
1592 | if (!info) | |
1593 | return ERR_PTR(-ENOMEM); | |
1594 | ||
1595 | ret = edma_of_parse_dt(dev, node, info); | |
1596 | if (ret) | |
1597 | return ERR_PTR(ret); | |
1598 | ||
1599 | dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap); | |
232b223d | 1600 | dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap); |
6cba4355 MP |
1601 | of_dma_controller_register(dev->of_node, of_dma_simple_xlate, |
1602 | &edma_filter_info); | |
1603 | ||
1604 | return info; | |
1605 | } | |
1606 | #else | |
1607 | static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, | |
1608 | struct device_node *node) | |
1609 | { | |
1610 | return ERR_PTR(-ENOSYS); | |
1611 | } | |
1612 | #endif | |
1613 | ||
1614 | static int edma_probe(struct platform_device *pdev) | |
a4768d22 | 1615 | { |
bc3ac9f3 | 1616 | struct edma_soc_info **info = pdev->dev.platform_data; |
6cba4355 MP |
1617 | struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL}; |
1618 | s8 (*queue_priority_mapping)[2]; | |
90bd4e6d | 1619 | int i, j, off, ln, found = 0; |
60902a2c | 1620 | int status = -1; |
90bd4e6d RS |
1621 | const s16 (*rsv_chans)[2]; |
1622 | const s16 (*rsv_slots)[2]; | |
2646a0e5 | 1623 | const s16 (*xbar_chans)[2]; |
60902a2c SR |
1624 | int irq[EDMA_MAX_CC] = {0, 0}; |
1625 | int err_irq[EDMA_MAX_CC] = {0, 0}; | |
1626 | struct resource *r[EDMA_MAX_CC] = {NULL}; | |
6cba4355 | 1627 | struct resource res[EDMA_MAX_CC]; |
60902a2c | 1628 | char res_name[10]; |
6cba4355 MP |
1629 | struct device_node *node = pdev->dev.of_node; |
1630 | struct device *dev = &pdev->dev; | |
1631 | int ret; | |
5305e4d6 AB |
1632 | struct platform_device_info edma_dev_info = { |
1633 | .name = "edma-dma-engine", | |
1634 | .dma_mask = DMA_BIT_MASK(32), | |
1635 | .parent = &pdev->dev, | |
1636 | }; | |
6cba4355 MP |
1637 | |
1638 | if (node) { | |
1639 | /* Check if this is a second instance registered */ | |
1640 | if (arch_num_cc) { | |
1641 | dev_err(dev, "only one EDMA instance is supported via DT\n"); | |
1642 | return -ENODEV; | |
1643 | } | |
1644 | ||
1645 | ninfo[0] = edma_setup_info_from_dt(dev, node); | |
1646 | if (IS_ERR(ninfo[0])) { | |
1647 | dev_err(dev, "failed to get DT data\n"); | |
1648 | return PTR_ERR(ninfo[0]); | |
1649 | } | |
1650 | ||
1651 | info = ninfo; | |
1652 | } | |
a4768d22 KH |
1653 | |
1654 | if (!info) | |
1655 | return -ENODEV; | |
1656 | ||
6cba4355 MP |
1657 | pm_runtime_enable(dev); |
1658 | ret = pm_runtime_get_sync(dev); | |
1659 | if (ret < 0) { | |
1660 | dev_err(dev, "pm_runtime_get_sync() failed\n"); | |
1661 | return ret; | |
1662 | } | |
1663 | ||
60902a2c | 1664 | for (j = 0; j < EDMA_MAX_CC; j++) { |
6cba4355 MP |
1665 | if (!info[j]) { |
1666 | if (!found) | |
1667 | return -ENODEV; | |
1668 | break; | |
1669 | } | |
1670 | if (node) { | |
1671 | ret = of_address_to_resource(node, j, &res[j]); | |
1672 | if (!ret) | |
1673 | r[j] = &res[j]; | |
1674 | } else { | |
1675 | sprintf(res_name, "edma_cc%d", j); | |
1676 | r[j] = platform_get_resource_byname(pdev, | |
1677 | IORESOURCE_MEM, | |
60902a2c | 1678 | res_name); |
6cba4355 MP |
1679 | } |
1680 | if (!r[j]) { | |
60902a2c SR |
1681 | if (found) |
1682 | break; | |
1683 | else | |
1684 | return -ENODEV; | |
243bc654 | 1685 | } else { |
60902a2c | 1686 | found = 1; |
243bc654 | 1687 | } |
60902a2c | 1688 | |
e7eff702 LP |
1689 | edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]); |
1690 | if (IS_ERR(edmacc_regs_base[j])) | |
1691 | return PTR_ERR(edmacc_regs_base[j]); | |
60902a2c | 1692 | |
e7eff702 LP |
1693 | edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma), |
1694 | GFP_KERNEL); | |
1695 | if (!edma_cc[j]) | |
1696 | return -ENOMEM; | |
60902a2c | 1697 | |
6d10c395 | 1698 | /* Get eDMA3 configuration from IP */ |
929a015b | 1699 | ret = edma_setup_from_hw(dev, info[j], edma_cc[j], j); |
6d10c395 PU |
1700 | if (ret) |
1701 | return ret; | |
60902a2c | 1702 | |
bc3ac9f3 | 1703 | edma_cc[j]->default_queue = info[j]->default_queue; |
a0f0202e | 1704 | |
60902a2c SR |
1705 | dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", |
1706 | edmacc_regs_base[j]); | |
1707 | ||
3f68b98a | 1708 | for (i = 0; i < edma_cc[j]->num_slots; i++) |
60902a2c SR |
1709 | memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), |
1710 | &dummy_paramset, PARM_SIZE); | |
1711 | ||
f900d552 | 1712 | /* Mark all channels as unused */ |
3f68b98a SN |
1713 | memset(edma_cc[j]->edma_unused, 0xff, |
1714 | sizeof(edma_cc[j]->edma_unused)); | |
a4768d22 | 1715 | |
90bd4e6d RS |
1716 | if (info[j]->rsv) { |
1717 | ||
1718 | /* Clear the reserved channels in unused list */ | |
1719 | rsv_chans = info[j]->rsv->rsv_chans; | |
1720 | if (rsv_chans) { | |
1721 | for (i = 0; rsv_chans[i][0] != -1; i++) { | |
1722 | off = rsv_chans[i][0]; | |
1723 | ln = rsv_chans[i][1]; | |
1724 | clear_bits(off, ln, | |
6cba4355 | 1725 | edma_cc[j]->edma_unused); |
90bd4e6d RS |
1726 | } |
1727 | } | |
1728 | ||
1729 | /* Set the reserved slots in inuse list */ | |
1730 | rsv_slots = info[j]->rsv->rsv_slots; | |
1731 | if (rsv_slots) { | |
1732 | for (i = 0; rsv_slots[i][0] != -1; i++) { | |
1733 | off = rsv_slots[i][0]; | |
1734 | ln = rsv_slots[i][1]; | |
1735 | set_bits(off, ln, | |
1736 | edma_cc[j]->edma_inuse); | |
1737 | } | |
1738 | } | |
1739 | } | |
1740 | ||
2646a0e5 MP |
1741 | /* Clear the xbar mapped channels in unused list */ |
1742 | xbar_chans = info[j]->xbar_chans; | |
1743 | if (xbar_chans) { | |
1744 | for (i = 0; xbar_chans[i][1] != -1; i++) { | |
1745 | off = xbar_chans[i][1]; | |
1746 | clear_bits(off, 1, | |
1747 | edma_cc[j]->edma_unused); | |
1748 | } | |
1749 | } | |
6cba4355 MP |
1750 | |
1751 | if (node) { | |
1752 | irq[j] = irq_of_parse_and_map(node, 0); | |
44161767 | 1753 | err_irq[j] = irq_of_parse_and_map(node, 2); |
6cba4355 | 1754 | } else { |
44161767 PU |
1755 | char irq_name[10]; |
1756 | ||
6cba4355 MP |
1757 | sprintf(irq_name, "edma%d", j); |
1758 | irq[j] = platform_get_irq_byname(pdev, irq_name); | |
44161767 PU |
1759 | |
1760 | sprintf(irq_name, "edma%d_err", j); | |
1761 | err_irq[j] = platform_get_irq_byname(pdev, irq_name); | |
6cba4355 | 1762 | } |
3f68b98a | 1763 | edma_cc[j]->irq_res_start = irq[j]; |
44161767 PU |
1764 | edma_cc[j]->irq_res_end = err_irq[j]; |
1765 | ||
1766 | status = devm_request_irq(dev, irq[j], dma_irq_handler, 0, | |
1767 | "edma", dev); | |
60902a2c | 1768 | if (status < 0) { |
e7eff702 LP |
1769 | dev_dbg(&pdev->dev, |
1770 | "devm_request_irq %d failed --> %d\n", | |
60902a2c | 1771 | irq[j], status); |
e7eff702 | 1772 | return status; |
60902a2c | 1773 | } |
a4768d22 | 1774 | |
44161767 PU |
1775 | status = devm_request_irq(dev, err_irq[j], dma_ccerr_handler, 0, |
1776 | "edma_error", dev); | |
60902a2c | 1777 | if (status < 0) { |
e7eff702 LP |
1778 | dev_dbg(&pdev->dev, |
1779 | "devm_request_irq %d failed --> %d\n", | |
60902a2c | 1780 | err_irq[j], status); |
e7eff702 | 1781 | return status; |
60902a2c | 1782 | } |
a4768d22 | 1783 | |
3f68b98a | 1784 | for (i = 0; i < edma_cc[j]->num_channels; i++) |
0b7580ba | 1785 | map_dmach_queue(j, i, info[j]->default_queue); |
a4768d22 | 1786 | |
bc3ac9f3 | 1787 | queue_priority_mapping = info[j]->queue_priority_mapping; |
a4768d22 | 1788 | |
60902a2c SR |
1789 | /* Event queue priority mapping */ |
1790 | for (i = 0; queue_priority_mapping[i][0] != -1; i++) | |
1791 | assign_priority_to_queue(j, | |
1792 | queue_priority_mapping[i][0], | |
1793 | queue_priority_mapping[i][1]); | |
1794 | ||
1795 | /* Map the channel to param entry if channel mapping logic | |
1796 | * exist | |
1797 | */ | |
1798 | if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST) | |
1799 | map_dmach_param(j); | |
a4768d22 | 1800 | |
643efcff | 1801 | for (i = 0; i < edma_cc[j]->num_region; i++) { |
60902a2c SR |
1802 | edma_write_array2(j, EDMA_DRAE, i, 0, 0x0); |
1803 | edma_write_array2(j, EDMA_DRAE, i, 1, 0x0); | |
1804 | edma_write_array(j, EDMA_QRAE, i, 0x0); | |
1805 | } | |
a2b11751 | 1806 | edma_cc[j]->info = info[j]; |
2d517508 | 1807 | arch_num_cc++; |
5305e4d6 AB |
1808 | |
1809 | edma_dev_info.id = j; | |
1810 | platform_device_register_full(&edma_dev_info); | |
a4768d22 KH |
1811 | } |
1812 | ||
a4768d22 | 1813 | return 0; |
a4768d22 KH |
1814 | } |
1815 | ||
a850c427 | 1816 | #ifdef CONFIG_PM_SLEEP |
a2b11751 DM |
1817 | static int edma_pm_resume(struct device *dev) |
1818 | { | |
1819 | int i, j; | |
1820 | ||
1821 | for (j = 0; j < arch_num_cc; j++) { | |
1822 | struct edma *cc = edma_cc[j]; | |
1823 | ||
1824 | s8 (*queue_priority_mapping)[2]; | |
1825 | ||
1826 | queue_priority_mapping = cc->info->queue_priority_mapping; | |
1827 | ||
1828 | /* Event queue priority mapping */ | |
1829 | for (i = 0; queue_priority_mapping[i][0] != -1; i++) | |
1830 | assign_priority_to_queue(j, | |
1831 | queue_priority_mapping[i][0], | |
1832 | queue_priority_mapping[i][1]); | |
1833 | ||
1834 | /* | |
1835 | * Map the channel to param entry if channel mapping logic | |
1836 | * exist | |
1837 | */ | |
1838 | if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST) | |
1839 | map_dmach_param(j); | |
1840 | ||
1841 | for (i = 0; i < cc->num_channels; i++) { | |
1842 | if (test_bit(i, cc->edma_inuse)) { | |
1843 | /* ensure access through shadow region 0 */ | |
1844 | edma_or_array2(j, EDMA_DRAE, 0, i >> 5, | |
1845 | BIT(i & 0x1f)); | |
1846 | ||
1847 | setup_dma_interrupt(i, | |
1848 | cc->intr_data[i].callback, | |
1849 | cc->intr_data[i].data); | |
1850 | } | |
1851 | } | |
1852 | } | |
1853 | ||
1854 | return 0; | |
1855 | } | |
a850c427 | 1856 | #endif |
a2b11751 DM |
1857 | |
1858 | static const struct dev_pm_ops edma_pm_ops = { | |
1859 | SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, edma_pm_resume) | |
1860 | }; | |
1861 | ||
a4768d22 | 1862 | static struct platform_driver edma_driver = { |
6cba4355 MP |
1863 | .driver = { |
1864 | .name = "edma", | |
a2b11751 | 1865 | .pm = &edma_pm_ops, |
6cba4355 MP |
1866 | .of_match_table = edma_of_ids, |
1867 | }, | |
1868 | .probe = edma_probe, | |
a4768d22 KH |
1869 | }; |
1870 | ||
1871 | static int __init edma_init(void) | |
1872 | { | |
1873 | return platform_driver_probe(&edma_driver, edma_probe); | |
1874 | } | |
1875 | arch_initcall(edma_init); | |
1876 |