[deliverable/linux.git] / arch / arm / common / gic.c

/*
 *  linux/arch/arm/common/gic.c
 *
 *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Interrupt architecture for the GIC:
 *
 * o There is one Interrupt Distributor, which receives interrupts
 *   from system devices and sends them to the Interrupt Controllers.
 *
 * o There is one CPU Interface per CPU, which sends interrupts sent
 *   by the Distributor, and interrupts generated locally, to the
 *   associated CPU.
 *
 * Note that IRQs 0-31 are special - they are local to each CPU.
 * As such, the enable set/clear, pending set/clear and active bit
 * registers are banked per-cpu for these sources.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/smp.h>
#include <linux/cpumask.h>

#include <asm/irq.h>
#include <asm/io.h>
#include <asm/mach/irq.h>
#include <asm/hardware/gic.h>

static void __iomem *gic_dist_base;
static void __iomem *gic_cpu_base;

/*
 * Routines to acknowledge, disable and enable interrupts
 *
 * Linux assumes that when we're done with an interrupt we need to
 * unmask it, in the same way we need to unmask an interrupt when
 * we first enable it.
 *
 * The GIC has a seperate notion of "end of interrupt" to re-enable
 * an interrupt after handling, in order to support hardware
 * prioritisation.
 *
 * We can make the GIC behave in the way that Linux expects by making
 * our "acknowledge" routine disable the interrupt, then mark it as
 * complete.
 */
static void gic_ack_irq(unsigned int irq)
{
	u32 mask = 1 << (irq % 32);
	writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
	writel(irq, gic_cpu_base + GIC_CPU_EOI);
}

static void gic_mask_irq(unsigned int irq)
{
	u32 mask = 1 << (irq % 32);
	writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
}

static void gic_unmask_irq(unsigned int irq)
{
	u32 mask = 1 << (irq % 32);
	writel(mask, gic_dist_base + GIC_DIST_ENABLE_SET + (irq / 32) * 4);
}

#ifdef CONFIG_SMP
static void gic_set_cpu(struct irqdesc *desc, unsigned int irq, unsigned int cpu)
{
	void __iomem *reg = gic_dist_base + GIC_DIST_TARGET + (irq & ~3);
	unsigned int shift = (irq % 4) * 8;
	u32 val;

	val = readl(reg) & ~(0xff << shift);
	val |= 1 << (cpu + shift);
	writel(val, reg);
}
#endif

static struct irqchip gic_chip = {
	.ack		= gic_ack_irq,
	.mask		= gic_mask_irq,
	.unmask		= gic_unmask_irq,
#ifdef CONFIG_SMP
	.set_cpu	= gic_set_cpu,
#endif
};

void __init gic_dist_init(void __iomem *base)
{
	unsigned int max_irq, i;
	u32 cpumask = 1 << smp_processor_id();

	cpumask |= cpumask << 8;
	cpumask |= cpumask << 16;

	gic_dist_base = base;

	writel(0, base + GIC_DIST_CTRL);

	/*
	 * Find out how many interrupts are supported.
	 */
	max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
	max_irq = (max_irq + 1) * 32;

	/*
	 * The GIC only supports up to 1020 interrupt sources.
	 * Limit this to either the architected maximum, or the
	 * platform maximum.
	 */
	if (max_irq > max(1020, NR_IRQS))
		max_irq = max(1020, NR_IRQS);

	/*
	 * Set all global interrupts to be level triggered, active low.
	 */
	for (i = 32; i < max_irq; i += 16)
		writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);

	/*
	 * Set all global interrupts to this CPU only.
	 */
	for (i = 32; i < max_irq; i += 4)
		writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);

	/*
	 * Set priority on all interrupts.
	 */
	for (i = 0; i < max_irq; i += 4)
		writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);

	/*
	 * Disable all interrupts.
	 */
	for (i = 0; i < max_irq; i += 32)
		writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);

	/*
	 * Setup the Linux IRQ subsystem.
	 */
	for (i = 29; i < max_irq; i++) {
		set_irq_chip(i, &gic_chip);
		set_irq_handler(i, do_level_IRQ);
		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
	}

	writel(1, base + GIC_DIST_CTRL);
}

void __cpuinit gic_cpu_init(void __iomem *base)
{
	gic_cpu_base = base;
	writel(0xf0, base + GIC_CPU_PRIMASK);
	writel(1, base + GIC_CPU_CTRL);
}

#ifdef CONFIG_SMP
void gic_raise_softirq(cpumask_t cpumask, unsigned int irq)
{
	unsigned long map = *cpus_addr(cpumask);

	writel(map << 16 | irq, gic_dist_base + GIC_DIST_SOFTINT);
}
#endif
Commit	Line	Data
f27ecacc RK	1	/*
	2	* linux/arch/arm/common/gic.c
	3	*
	4	* Copyright (C) 2002 ARM Limited, All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Interrupt architecture for the GIC:
	11	*
	12	* o There is one Interrupt Distributor, which receives interrupts
	13	* from system devices and sends them to the Interrupt Controllers.
	14	*
	15	* o There is one CPU Interface per CPU, which sends interrupts sent
	16	* by the Distributor, and interrupts generated locally, to the
	17	* associated CPU.
	18	*
	19	* Note that IRQs 0-31 are special - they are local to each CPU.
	20	* As such, the enable set/clear, pending set/clear and active bit
	21	* registers are banked per-cpu for these sources.
	22	*/
	23	#include <linux/init.h>
	24	#include <linux/kernel.h>
	25	#include <linux/list.h>
	26	#include <linux/smp.h>
dcb86e8c	27	#include <linux/cpumask.h>
f27ecacc RK	28
	29	#include <asm/irq.h>
	30	#include <asm/io.h>
	31	#include <asm/mach/irq.h>
	32	#include <asm/hardware/gic.h>
	33
	34	static void __iomem *gic_dist_base;
	35	static void __iomem *gic_cpu_base;
	36
	37	/*
	38	* Routines to acknowledge, disable and enable interrupts
	39	*
	40	* Linux assumes that when we're done with an interrupt we need to
	41	* unmask it, in the same way we need to unmask an interrupt when
	42	* we first enable it.
	43	*
	44	* The GIC has a seperate notion of "end of interrupt" to re-enable
	45	* an interrupt after handling, in order to support hardware
	46	* prioritisation.
	47	*
	48	* We can make the GIC behave in the way that Linux expects by making
	49	* our "acknowledge" routine disable the interrupt, then mark it as
	50	* complete.
	51	*/
	52	static void gic_ack_irq(unsigned int irq)
	53	{
	54	u32 mask = 1 << (irq % 32);
	55	writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
	56	writel(irq, gic_cpu_base + GIC_CPU_EOI);
	57	}
	58
	59	static void gic_mask_irq(unsigned int irq)
	60	{
	61	u32 mask = 1 << (irq % 32);
	62	writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
	63	}
	64
	65	static void gic_unmask_irq(unsigned int irq)
	66	{
	67	u32 mask = 1 << (irq % 32);
	68	writel(mask, gic_dist_base + GIC_DIST_ENABLE_SET + (irq / 32) * 4);
	69	}
	70
a06f5466	71	#ifdef CONFIG_SMP
f27ecacc RK	72	static void gic_set_cpu(struct irqdesc *desc, unsigned int irq, unsigned int cpu)
	73	{
	74	void __iomem *reg = gic_dist_base + GIC_DIST_TARGET + (irq & ~3);
	75	unsigned int shift = (irq % 4) * 8;
	76	u32 val;
	77
	78	val = readl(reg) & ~(0xff << shift);
	79	val \|= 1 << (cpu + shift);
	80	writel(val, reg);
	81	}
a06f5466	82	#endif
f27ecacc RK	83
	84	static struct irqchip gic_chip = {
	85	.ack = gic_ack_irq,
	86	.mask = gic_mask_irq,
	87	.unmask = gic_unmask_irq,
	88	#ifdef CONFIG_SMP
	89	.set_cpu = gic_set_cpu,
	90	#endif
	91	};
	92
	93	void __init gic_dist_init(void __iomem *base)
	94	{
	95	unsigned int max_irq, i;
	96	u32 cpumask = 1 << smp_processor_id();
	97
	98	cpumask \|= cpumask << 8;
	99	cpumask \|= cpumask << 16;
	100
	101	gic_dist_base = base;
	102
	103	writel(0, base + GIC_DIST_CTRL);
	104
	105	/*
	106	* Find out how many interrupts are supported.
	107	*/
	108	max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
	109	max_irq = (max_irq + 1) * 32;
	110
	111	/*
	112	* The GIC only supports up to 1020 interrupt sources.
	113	* Limit this to either the architected maximum, or the
	114	* platform maximum.
	115	*/
	116	if (max_irq > max(1020, NR_IRQS))
	117	max_irq = max(1020, NR_IRQS);
	118
	119	/*
	120	* Set all global interrupts to be level triggered, active low.
	121	*/
	122	for (i = 32; i < max_irq; i += 16)
	123	writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
	124
	125	/*
	126	* Set all global interrupts to this CPU only.
	127	*/
	128	for (i = 32; i < max_irq; i += 4)
	129	writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
	130
	131	/*
	132	* Set priority on all interrupts.
	133	*/
	134	for (i = 0; i < max_irq; i += 4)
	135	writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
	136
	137	/*
	138	* Disable all interrupts.
	139	*/
	140	for (i = 0; i < max_irq; i += 32)
	141	writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
	142
	143	/*
	144	* Setup the Linux IRQ subsystem.
	145	*/
	146	for (i = 29; i < max_irq; i++) {
147	set_irq_chip(i, &gic_chip);
148	set_irq_handler(i, do_level_IRQ);
149	set_irq_flags(i, IRQF_VALID \| IRQF_PROBE);
150	}
151
152	writel(1, base + GIC_DIST_CTRL);
153	}
154
155	void __cpuinit gic_cpu_init(void __iomem *base)
156	{
157	gic_cpu_base = base;
158	writel(0xf0, base + GIC_CPU_PRIMASK);
159	writel(1, base + GIC_CPU_CTRL);
160	}
161
162	#ifdef CONFIG_SMP
163	void gic_raise_softirq(cpumask_t cpumask, unsigned int irq)
164	{
165	unsigned long map = *cpus_addr(cpumask);
166
167	writel(map << 16 \| irq, gic_dist_base + GIC_DIST_SOFTINT);
168	}
169	#endif