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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/common/icst307.c | |
3 | * | |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Support functions for calculating clocks/divisors for the ICST307 | |
11 | * clock generators. See http://www.icst.com/ for more information | |
12 | * on these devices. | |
13 | * | |
14 | * This is an almost identical implementation to the ICST525 clock generator. | |
15 | * The s2div and idx2s files are different | |
16 | */ | |
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | ||
20 | #include <asm/hardware/icst307.h> | |
21 | ||
22 | /* | |
23 | * Divisors for each OD setting. | |
24 | */ | |
232eaf7f RK |
25 | const unsigned char icst307_s2div[8] = { 10, 2, 8, 4, 5, 7, 3, 6 }; |
26 | ||
27 | EXPORT_SYMBOL(icst307_s2div); | |
1da177e4 | 28 | |
64fceb1d | 29 | unsigned long icst307_hz(const struct icst_params *p, struct icst_vco vco) |
1da177e4 | 30 | { |
232eaf7f | 31 | return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * p->s2div[vco.s]); |
1da177e4 LT |
32 | } |
33 | ||
64fceb1d | 34 | EXPORT_SYMBOL(icst307_hz); |
1da177e4 LT |
35 | |
36 | /* | |
37 | * Ascending divisor S values. | |
38 | */ | |
232eaf7f RK |
39 | const unsigned char icst307_idx2s[8] = { 1, 6, 3, 4, 7, 5, 2, 0 }; |
40 | ||
41 | EXPORT_SYMBOL(icst307_idx2s); | |
1da177e4 | 42 | |
39c0cb02 | 43 | struct icst_vco |
64fceb1d | 44 | icst307_hz_to_vco(const struct icst_params *p, unsigned long freq) |
1da177e4 | 45 | { |
39c0cb02 | 46 | struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max }; |
1da177e4 LT |
47 | unsigned long f; |
48 | unsigned int i = 0, rd, best = (unsigned int)-1; | |
49 | ||
50 | /* | |
51 | * First, find the PLL output divisor such | |
52 | * that the PLL output is within spec. | |
53 | */ | |
54 | do { | |
232eaf7f | 55 | f = freq * p->s2div[p->idx2s[i]]; |
1da177e4 LT |
56 | |
57 | /* | |
58 | * f must be between 6MHz and 200MHz (3.3 or 5V) | |
59 | */ | |
e73a46a3 | 60 | if (f > p->vco_min && f <= p->vco_max) |
1da177e4 | 61 | break; |
232eaf7f | 62 | } while (i < 8); |
1da177e4 | 63 | |
232eaf7f | 64 | if (i >= 8) |
1da177e4 LT |
65 | return vco; |
66 | ||
232eaf7f | 67 | vco.s = p->idx2s[i]; |
1da177e4 LT |
68 | |
69 | /* | |
70 | * Now find the closest divisor combination | |
71 | * which gives a PLL output of 'f'. | |
72 | */ | |
73 | for (rd = p->rd_min; rd <= p->rd_max; rd++) { | |
74 | unsigned long fref_div, f_pll; | |
75 | unsigned int vd; | |
76 | int f_diff; | |
77 | ||
78 | fref_div = (2 * p->ref) / rd; | |
79 | ||
80 | vd = (f + fref_div / 2) / fref_div; | |
81 | if (vd < p->vd_min || vd > p->vd_max) | |
82 | continue; | |
83 | ||
84 | f_pll = fref_div * vd; | |
85 | f_diff = f_pll - f; | |
86 | if (f_diff < 0) | |
87 | f_diff = -f_diff; | |
88 | ||
89 | if ((unsigned)f_diff < best) { | |
90 | vco.v = vd - 8; | |
91 | vco.r = rd - 2; | |
92 | if (f_diff == 0) | |
93 | break; | |
94 | best = f_diff; | |
95 | } | |
96 | } | |
97 | ||
98 | return vco; | |
99 | } | |
100 | ||
64fceb1d | 101 | EXPORT_SYMBOL(icst307_hz_to_vco); |