Commit | Line | Data |
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1da177e4 | 1 | /* |
f30c2269 | 2 | * linux/arch/arm/common/sa1111.c |
1da177e4 LT |
3 | * |
4 | * SA1111 support | |
5 | * | |
6 | * Original code by John Dorsey | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This file contains all generic SA1111 support. | |
13 | * | |
14 | * All initialization functions provided here are intended to be called | |
15 | * from machine specific code with proper arguments when required. | |
16 | */ | |
1da177e4 LT |
17 | #include <linux/module.h> |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/delay.h> | |
1da177e4 LT |
21 | #include <linux/errno.h> |
22 | #include <linux/ioport.h> | |
d052d1be | 23 | #include <linux/platform_device.h> |
1da177e4 LT |
24 | #include <linux/slab.h> |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/dma-mapping.h> | |
97d654f8 | 27 | #include <linux/clk.h> |
fced80c7 | 28 | #include <linux/io.h> |
1da177e4 | 29 | |
a09e64fb | 30 | #include <mach/hardware.h> |
1da177e4 | 31 | #include <asm/mach-types.h> |
1da177e4 LT |
32 | #include <asm/irq.h> |
33 | #include <asm/mach/irq.h> | |
45e109d0 | 34 | #include <asm/sizes.h> |
1da177e4 LT |
35 | |
36 | #include <asm/hardware/sa1111.h> | |
37 | ||
19851c58 EM |
38 | /* SA1111 IRQs */ |
39 | #define IRQ_GPAIN0 (0) | |
40 | #define IRQ_GPAIN1 (1) | |
41 | #define IRQ_GPAIN2 (2) | |
42 | #define IRQ_GPAIN3 (3) | |
43 | #define IRQ_GPBIN0 (4) | |
44 | #define IRQ_GPBIN1 (5) | |
45 | #define IRQ_GPBIN2 (6) | |
46 | #define IRQ_GPBIN3 (7) | |
47 | #define IRQ_GPBIN4 (8) | |
48 | #define IRQ_GPBIN5 (9) | |
49 | #define IRQ_GPCIN0 (10) | |
50 | #define IRQ_GPCIN1 (11) | |
51 | #define IRQ_GPCIN2 (12) | |
52 | #define IRQ_GPCIN3 (13) | |
53 | #define IRQ_GPCIN4 (14) | |
54 | #define IRQ_GPCIN5 (15) | |
55 | #define IRQ_GPCIN6 (16) | |
56 | #define IRQ_GPCIN7 (17) | |
57 | #define IRQ_MSTXINT (18) | |
58 | #define IRQ_MSRXINT (19) | |
59 | #define IRQ_MSSTOPERRINT (20) | |
60 | #define IRQ_TPTXINT (21) | |
61 | #define IRQ_TPRXINT (22) | |
62 | #define IRQ_TPSTOPERRINT (23) | |
63 | #define SSPXMTINT (24) | |
64 | #define SSPRCVINT (25) | |
65 | #define SSPROR (26) | |
66 | #define AUDXMTDMADONEA (32) | |
67 | #define AUDRCVDMADONEA (33) | |
68 | #define AUDXMTDMADONEB (34) | |
69 | #define AUDRCVDMADONEB (35) | |
70 | #define AUDTFSR (36) | |
71 | #define AUDRFSR (37) | |
72 | #define AUDTUR (38) | |
73 | #define AUDROR (39) | |
74 | #define AUDDTS (40) | |
75 | #define AUDRDD (41) | |
76 | #define AUDSTO (42) | |
77 | #define IRQ_USBPWR (43) | |
78 | #define IRQ_HCIM (44) | |
79 | #define IRQ_HCIBUFFACC (45) | |
80 | #define IRQ_HCIRMTWKP (46) | |
81 | #define IRQ_NHCIMFCIR (47) | |
82 | #define IRQ_USB_PORT_RESUME (48) | |
83 | #define IRQ_S0_READY_NINT (49) | |
84 | #define IRQ_S1_READY_NINT (50) | |
85 | #define IRQ_S0_CD_VALID (51) | |
86 | #define IRQ_S1_CD_VALID (52) | |
87 | #define IRQ_S0_BVD1_STSCHG (53) | |
88 | #define IRQ_S1_BVD1_STSCHG (54) | |
89 | ||
1da177e4 LT |
90 | extern void __init sa1110_mb_enable(void); |
91 | ||
92 | /* | |
93 | * We keep the following data for the overall SA1111. Note that the | |
94 | * struct device and struct resource are "fake"; they should be supplied | |
95 | * by the bus above us. However, in the interests of getting all SA1111 | |
96 | * drivers converted over to the device model, we provide this as an | |
97 | * anchor point for all the other drivers. | |
98 | */ | |
99 | struct sa1111 { | |
100 | struct device *dev; | |
97d654f8 | 101 | struct clk *clk; |
1da177e4 LT |
102 | unsigned long phys; |
103 | int irq; | |
19851c58 | 104 | int irq_base; /* base for cascaded on-chip IRQs */ |
1da177e4 LT |
105 | spinlock_t lock; |
106 | void __iomem *base; | |
93160c63 RW |
107 | #ifdef CONFIG_PM |
108 | void *saved_state; | |
109 | #endif | |
1da177e4 LT |
110 | }; |
111 | ||
112 | /* | |
113 | * We _really_ need to eliminate this. Its only users | |
114 | * are the PWM and DMA checking code. | |
115 | */ | |
116 | static struct sa1111 *g_sa1111; | |
117 | ||
118 | struct sa1111_dev_info { | |
119 | unsigned long offset; | |
120 | unsigned long skpcr_mask; | |
121 | unsigned int devid; | |
122 | unsigned int irq[6]; | |
123 | }; | |
124 | ||
125 | static struct sa1111_dev_info sa1111_devices[] = { | |
126 | { | |
127 | .offset = SA1111_USB, | |
128 | .skpcr_mask = SKPCR_UCLKEN, | |
129 | .devid = SA1111_DEVID_USB, | |
130 | .irq = { | |
131 | IRQ_USBPWR, | |
132 | IRQ_HCIM, | |
133 | IRQ_HCIBUFFACC, | |
134 | IRQ_HCIRMTWKP, | |
135 | IRQ_NHCIMFCIR, | |
136 | IRQ_USB_PORT_RESUME | |
137 | }, | |
138 | }, | |
139 | { | |
140 | .offset = 0x0600, | |
141 | .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN, | |
142 | .devid = SA1111_DEVID_SAC, | |
143 | .irq = { | |
144 | AUDXMTDMADONEA, | |
145 | AUDXMTDMADONEB, | |
146 | AUDRCVDMADONEA, | |
147 | AUDRCVDMADONEB | |
148 | }, | |
149 | }, | |
150 | { | |
151 | .offset = 0x0800, | |
152 | .skpcr_mask = SKPCR_SCLKEN, | |
153 | .devid = SA1111_DEVID_SSP, | |
154 | }, | |
155 | { | |
156 | .offset = SA1111_KBD, | |
157 | .skpcr_mask = SKPCR_PTCLKEN, | |
158 | .devid = SA1111_DEVID_PS2, | |
159 | .irq = { | |
160 | IRQ_TPRXINT, | |
161 | IRQ_TPTXINT | |
162 | }, | |
163 | }, | |
164 | { | |
165 | .offset = SA1111_MSE, | |
166 | .skpcr_mask = SKPCR_PMCLKEN, | |
167 | .devid = SA1111_DEVID_PS2, | |
168 | .irq = { | |
169 | IRQ_MSRXINT, | |
170 | IRQ_MSTXINT | |
171 | }, | |
172 | }, | |
173 | { | |
174 | .offset = 0x1800, | |
175 | .skpcr_mask = 0, | |
176 | .devid = SA1111_DEVID_PCMCIA, | |
177 | .irq = { | |
178 | IRQ_S0_READY_NINT, | |
179 | IRQ_S0_CD_VALID, | |
180 | IRQ_S0_BVD1_STSCHG, | |
181 | IRQ_S1_READY_NINT, | |
182 | IRQ_S1_CD_VALID, | |
183 | IRQ_S1_BVD1_STSCHG, | |
184 | }, | |
185 | }, | |
186 | }; | |
187 | ||
188 | /* | |
189 | * SA1111 interrupt support. Since clearing an IRQ while there are | |
190 | * active IRQs causes the interrupt output to pulse, the upper levels | |
191 | * will call us again if there are more interrupts to process. | |
192 | */ | |
193 | static void | |
10dd5ce2 | 194 | sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) |
1da177e4 LT |
195 | { |
196 | unsigned int stat0, stat1, i; | |
6845664a | 197 | struct sa1111 *sachip = irq_get_handler_data(irq); |
19851c58 | 198 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
1da177e4 | 199 | |
19851c58 EM |
200 | stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0); |
201 | stat1 = sa1111_readl(mapbase + SA1111_INTSTATCLR1); | |
1da177e4 | 202 | |
19851c58 | 203 | sa1111_writel(stat0, mapbase + SA1111_INTSTATCLR0); |
1da177e4 | 204 | |
8231e741 | 205 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
1da177e4 | 206 | |
19851c58 | 207 | sa1111_writel(stat1, mapbase + SA1111_INTSTATCLR1); |
1da177e4 LT |
208 | |
209 | if (stat0 == 0 && stat1 == 0) { | |
0cd61b68 | 210 | do_bad_IRQ(irq, desc); |
1da177e4 LT |
211 | return; |
212 | } | |
213 | ||
19851c58 | 214 | for (i = 0; stat0; i++, stat0 >>= 1) |
1da177e4 | 215 | if (stat0 & 1) |
19851c58 | 216 | generic_handle_irq(i + sachip->irq_base); |
1da177e4 | 217 | |
19851c58 | 218 | for (i = 32; stat1; i++, stat1 >>= 1) |
1da177e4 | 219 | if (stat1 & 1) |
19851c58 | 220 | generic_handle_irq(i + sachip->irq_base); |
1da177e4 LT |
221 | |
222 | /* For level-based interrupts */ | |
8231e741 | 223 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
1da177e4 LT |
224 | } |
225 | ||
19851c58 EM |
226 | #define SA1111_IRQMASK_LO(x) (1 << (x - sachip->irq_base)) |
227 | #define SA1111_IRQMASK_HI(x) (1 << (x - sachip->irq_base - 32)) | |
1da177e4 | 228 | |
8231e741 | 229 | static void sa1111_ack_irq(struct irq_data *d) |
1da177e4 LT |
230 | { |
231 | } | |
232 | ||
8231e741 | 233 | static void sa1111_mask_lowirq(struct irq_data *d) |
1da177e4 | 234 | { |
8231e741 | 235 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 236 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
1da177e4 LT |
237 | unsigned long ie0; |
238 | ||
239 | ie0 = sa1111_readl(mapbase + SA1111_INTEN0); | |
8231e741 | 240 | ie0 &= ~SA1111_IRQMASK_LO(d->irq); |
1da177e4 LT |
241 | writel(ie0, mapbase + SA1111_INTEN0); |
242 | } | |
243 | ||
8231e741 | 244 | static void sa1111_unmask_lowirq(struct irq_data *d) |
1da177e4 | 245 | { |
8231e741 | 246 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 247 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
1da177e4 LT |
248 | unsigned long ie0; |
249 | ||
250 | ie0 = sa1111_readl(mapbase + SA1111_INTEN0); | |
8231e741 | 251 | ie0 |= SA1111_IRQMASK_LO(d->irq); |
1da177e4 LT |
252 | sa1111_writel(ie0, mapbase + SA1111_INTEN0); |
253 | } | |
254 | ||
255 | /* | |
256 | * Attempt to re-trigger the interrupt. The SA1111 contains a register | |
257 | * (INTSET) which claims to do this. However, in practice no amount of | |
258 | * manipulation of INTEN and INTSET guarantees that the interrupt will | |
259 | * be triggered. In fact, its very difficult, if not impossible to get | |
260 | * INTSET to re-trigger the interrupt. | |
261 | */ | |
8231e741 | 262 | static int sa1111_retrigger_lowirq(struct irq_data *d) |
1da177e4 | 263 | { |
8231e741 | 264 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 265 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
8231e741 | 266 | unsigned int mask = SA1111_IRQMASK_LO(d->irq); |
1da177e4 LT |
267 | unsigned long ip0; |
268 | int i; | |
269 | ||
270 | ip0 = sa1111_readl(mapbase + SA1111_INTPOL0); | |
271 | for (i = 0; i < 8; i++) { | |
272 | sa1111_writel(ip0 ^ mask, mapbase + SA1111_INTPOL0); | |
273 | sa1111_writel(ip0, mapbase + SA1111_INTPOL0); | |
cae39988 | 274 | if (sa1111_readl(mapbase + SA1111_INTSTATCLR0) & mask) |
1da177e4 LT |
275 | break; |
276 | } | |
277 | ||
278 | if (i == 8) | |
279 | printk(KERN_ERR "Danger Will Robinson: failed to " | |
8231e741 | 280 | "re-trigger IRQ%d\n", d->irq); |
1da177e4 LT |
281 | return i == 8 ? -1 : 0; |
282 | } | |
283 | ||
8231e741 | 284 | static int sa1111_type_lowirq(struct irq_data *d, unsigned int flags) |
1da177e4 | 285 | { |
8231e741 | 286 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 287 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
8231e741 | 288 | unsigned int mask = SA1111_IRQMASK_LO(d->irq); |
1da177e4 LT |
289 | unsigned long ip0; |
290 | ||
6cab4860 | 291 | if (flags == IRQ_TYPE_PROBE) |
1da177e4 LT |
292 | return 0; |
293 | ||
6cab4860 | 294 | if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0) |
1da177e4 LT |
295 | return -EINVAL; |
296 | ||
297 | ip0 = sa1111_readl(mapbase + SA1111_INTPOL0); | |
6cab4860 | 298 | if (flags & IRQ_TYPE_EDGE_RISING) |
1da177e4 LT |
299 | ip0 &= ~mask; |
300 | else | |
301 | ip0 |= mask; | |
302 | sa1111_writel(ip0, mapbase + SA1111_INTPOL0); | |
303 | sa1111_writel(ip0, mapbase + SA1111_WAKEPOL0); | |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
8231e741 | 308 | static int sa1111_wake_lowirq(struct irq_data *d, unsigned int on) |
1da177e4 | 309 | { |
8231e741 | 310 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 311 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
8231e741 | 312 | unsigned int mask = SA1111_IRQMASK_LO(d->irq); |
1da177e4 LT |
313 | unsigned long we0; |
314 | ||
315 | we0 = sa1111_readl(mapbase + SA1111_WAKEEN0); | |
316 | if (on) | |
317 | we0 |= mask; | |
318 | else | |
319 | we0 &= ~mask; | |
320 | sa1111_writel(we0, mapbase + SA1111_WAKEEN0); | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
38c677cb DB |
325 | static struct irq_chip sa1111_low_chip = { |
326 | .name = "SA1111-l", | |
8231e741 LB |
327 | .irq_ack = sa1111_ack_irq, |
328 | .irq_mask = sa1111_mask_lowirq, | |
329 | .irq_unmask = sa1111_unmask_lowirq, | |
330 | .irq_retrigger = sa1111_retrigger_lowirq, | |
331 | .irq_set_type = sa1111_type_lowirq, | |
332 | .irq_set_wake = sa1111_wake_lowirq, | |
1da177e4 LT |
333 | }; |
334 | ||
8231e741 | 335 | static void sa1111_mask_highirq(struct irq_data *d) |
1da177e4 | 336 | { |
8231e741 | 337 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 338 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
1da177e4 LT |
339 | unsigned long ie1; |
340 | ||
341 | ie1 = sa1111_readl(mapbase + SA1111_INTEN1); | |
8231e741 | 342 | ie1 &= ~SA1111_IRQMASK_HI(d->irq); |
1da177e4 LT |
343 | sa1111_writel(ie1, mapbase + SA1111_INTEN1); |
344 | } | |
345 | ||
8231e741 | 346 | static void sa1111_unmask_highirq(struct irq_data *d) |
1da177e4 | 347 | { |
8231e741 | 348 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 349 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
1da177e4 LT |
350 | unsigned long ie1; |
351 | ||
352 | ie1 = sa1111_readl(mapbase + SA1111_INTEN1); | |
8231e741 | 353 | ie1 |= SA1111_IRQMASK_HI(d->irq); |
1da177e4 LT |
354 | sa1111_writel(ie1, mapbase + SA1111_INTEN1); |
355 | } | |
356 | ||
357 | /* | |
358 | * Attempt to re-trigger the interrupt. The SA1111 contains a register | |
359 | * (INTSET) which claims to do this. However, in practice no amount of | |
360 | * manipulation of INTEN and INTSET guarantees that the interrupt will | |
361 | * be triggered. In fact, its very difficult, if not impossible to get | |
362 | * INTSET to re-trigger the interrupt. | |
363 | */ | |
8231e741 | 364 | static int sa1111_retrigger_highirq(struct irq_data *d) |
1da177e4 | 365 | { |
8231e741 | 366 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 367 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
8231e741 | 368 | unsigned int mask = SA1111_IRQMASK_HI(d->irq); |
1da177e4 LT |
369 | unsigned long ip1; |
370 | int i; | |
371 | ||
372 | ip1 = sa1111_readl(mapbase + SA1111_INTPOL1); | |
373 | for (i = 0; i < 8; i++) { | |
374 | sa1111_writel(ip1 ^ mask, mapbase + SA1111_INTPOL1); | |
375 | sa1111_writel(ip1, mapbase + SA1111_INTPOL1); | |
376 | if (sa1111_readl(mapbase + SA1111_INTSTATCLR1) & mask) | |
377 | break; | |
378 | } | |
379 | ||
380 | if (i == 8) | |
381 | printk(KERN_ERR "Danger Will Robinson: failed to " | |
8231e741 | 382 | "re-trigger IRQ%d\n", d->irq); |
1da177e4 LT |
383 | return i == 8 ? -1 : 0; |
384 | } | |
385 | ||
8231e741 | 386 | static int sa1111_type_highirq(struct irq_data *d, unsigned int flags) |
1da177e4 | 387 | { |
8231e741 | 388 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 389 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
8231e741 | 390 | unsigned int mask = SA1111_IRQMASK_HI(d->irq); |
1da177e4 LT |
391 | unsigned long ip1; |
392 | ||
6cab4860 | 393 | if (flags == IRQ_TYPE_PROBE) |
1da177e4 LT |
394 | return 0; |
395 | ||
6cab4860 | 396 | if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0) |
1da177e4 LT |
397 | return -EINVAL; |
398 | ||
399 | ip1 = sa1111_readl(mapbase + SA1111_INTPOL1); | |
6cab4860 | 400 | if (flags & IRQ_TYPE_EDGE_RISING) |
1da177e4 LT |
401 | ip1 &= ~mask; |
402 | else | |
403 | ip1 |= mask; | |
404 | sa1111_writel(ip1, mapbase + SA1111_INTPOL1); | |
405 | sa1111_writel(ip1, mapbase + SA1111_WAKEPOL1); | |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
8231e741 | 410 | static int sa1111_wake_highirq(struct irq_data *d, unsigned int on) |
1da177e4 | 411 | { |
8231e741 | 412 | struct sa1111 *sachip = irq_data_get_irq_chip_data(d); |
19851c58 | 413 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
8231e741 | 414 | unsigned int mask = SA1111_IRQMASK_HI(d->irq); |
1da177e4 LT |
415 | unsigned long we1; |
416 | ||
417 | we1 = sa1111_readl(mapbase + SA1111_WAKEEN1); | |
418 | if (on) | |
419 | we1 |= mask; | |
420 | else | |
421 | we1 &= ~mask; | |
422 | sa1111_writel(we1, mapbase + SA1111_WAKEEN1); | |
423 | ||
424 | return 0; | |
425 | } | |
426 | ||
38c677cb DB |
427 | static struct irq_chip sa1111_high_chip = { |
428 | .name = "SA1111-h", | |
8231e741 LB |
429 | .irq_ack = sa1111_ack_irq, |
430 | .irq_mask = sa1111_mask_highirq, | |
431 | .irq_unmask = sa1111_unmask_highirq, | |
432 | .irq_retrigger = sa1111_retrigger_highirq, | |
433 | .irq_set_type = sa1111_type_highirq, | |
434 | .irq_set_wake = sa1111_wake_highirq, | |
1da177e4 LT |
435 | }; |
436 | ||
437 | static void sa1111_setup_irq(struct sa1111 *sachip) | |
438 | { | |
439 | void __iomem *irqbase = sachip->base + SA1111_INTC; | |
440 | unsigned int irq; | |
441 | ||
442 | /* | |
443 | * We're guaranteed that this region hasn't been taken. | |
444 | */ | |
445 | request_mem_region(sachip->phys + SA1111_INTC, 512, "irq"); | |
446 | ||
447 | /* disable all IRQs */ | |
448 | sa1111_writel(0, irqbase + SA1111_INTEN0); | |
449 | sa1111_writel(0, irqbase + SA1111_INTEN1); | |
450 | sa1111_writel(0, irqbase + SA1111_WAKEEN0); | |
451 | sa1111_writel(0, irqbase + SA1111_WAKEEN1); | |
452 | ||
453 | /* | |
454 | * detect on rising edge. Note: Feb 2001 Errata for SA1111 | |
455 | * specifies that S0ReadyInt and S1ReadyInt should be '1'. | |
456 | */ | |
457 | sa1111_writel(0, irqbase + SA1111_INTPOL0); | |
458 | sa1111_writel(SA1111_IRQMASK_HI(IRQ_S0_READY_NINT) | | |
459 | SA1111_IRQMASK_HI(IRQ_S1_READY_NINT), | |
460 | irqbase + SA1111_INTPOL1); | |
461 | ||
462 | /* clear all IRQs */ | |
463 | sa1111_writel(~0, irqbase + SA1111_INTSTATCLR0); | |
464 | sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); | |
465 | ||
466 | for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { | |
f38c02f3 TG |
467 | irq_set_chip_and_handler(irq, &sa1111_low_chip, |
468 | handle_edge_irq); | |
9323f261 | 469 | irq_set_chip_data(irq, sachip); |
1da177e4 LT |
470 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
471 | } | |
472 | ||
473 | for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { | |
f38c02f3 TG |
474 | irq_set_chip_and_handler(irq, &sa1111_high_chip, |
475 | handle_edge_irq); | |
9323f261 | 476 | irq_set_chip_data(irq, sachip); |
1da177e4 LT |
477 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
478 | } | |
479 | ||
480 | /* | |
481 | * Register SA1111 interrupt | |
482 | */ | |
6845664a TG |
483 | irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); |
484 | irq_set_handler_data(sachip->irq, sachip); | |
485 | irq_set_chained_handler(sachip->irq, sa1111_irq_handler); | |
1da177e4 LT |
486 | } |
487 | ||
488 | /* | |
489 | * Bring the SA1111 out of reset. This requires a set procedure: | |
490 | * 1. nRESET asserted (by hardware) | |
491 | * 2. CLK turned on from SA1110 | |
492 | * 3. nRESET deasserted | |
493 | * 4. VCO turned on, PLL_BYPASS turned off | |
494 | * 5. Wait lock time, then assert RCLKEn | |
495 | * 7. PCR set to allow clocking of individual functions | |
496 | * | |
497 | * Until we've done this, the only registers we can access are: | |
498 | * SBI_SKCR | |
499 | * SBI_SMCR | |
500 | * SBI_SKID | |
501 | */ | |
502 | static void sa1111_wake(struct sa1111 *sachip) | |
503 | { | |
504 | unsigned long flags, r; | |
505 | ||
506 | spin_lock_irqsave(&sachip->lock, flags); | |
507 | ||
97d654f8 | 508 | clk_enable(sachip->clk); |
1da177e4 LT |
509 | |
510 | /* | |
511 | * Turn VCO on, and disable PLL Bypass. | |
512 | */ | |
513 | r = sa1111_readl(sachip->base + SA1111_SKCR); | |
514 | r &= ~SKCR_VCO_OFF; | |
515 | sa1111_writel(r, sachip->base + SA1111_SKCR); | |
516 | r |= SKCR_PLL_BYPASS | SKCR_OE_EN; | |
517 | sa1111_writel(r, sachip->base + SA1111_SKCR); | |
518 | ||
519 | /* | |
520 | * Wait lock time. SA1111 manual _doesn't_ | |
521 | * specify a figure for this! We choose 100us. | |
522 | */ | |
523 | udelay(100); | |
524 | ||
525 | /* | |
526 | * Enable RCLK. We also ensure that RDYEN is set. | |
527 | */ | |
528 | r |= SKCR_RCLKEN | SKCR_RDYEN; | |
529 | sa1111_writel(r, sachip->base + SA1111_SKCR); | |
530 | ||
531 | /* | |
532 | * Wait 14 RCLK cycles for the chip to finish coming out | |
533 | * of reset. (RCLK=24MHz). This is 590ns. | |
534 | */ | |
535 | udelay(1); | |
536 | ||
537 | /* | |
538 | * Ensure all clocks are initially off. | |
539 | */ | |
540 | sa1111_writel(0, sachip->base + SA1111_SKPCR); | |
541 | ||
542 | spin_unlock_irqrestore(&sachip->lock, flags); | |
543 | } | |
544 | ||
545 | #ifdef CONFIG_ARCH_SA1100 | |
546 | ||
547 | static u32 sa1111_dma_mask[] = { | |
548 | ~0, | |
549 | ~(1 << 20), | |
550 | ~(1 << 23), | |
551 | ~(1 << 24), | |
552 | ~(1 << 25), | |
553 | ~(1 << 20), | |
554 | ~(1 << 20), | |
555 | 0, | |
556 | }; | |
557 | ||
558 | /* | |
559 | * Configure the SA1111 shared memory controller. | |
560 | */ | |
561 | void | |
562 | sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac, | |
563 | unsigned int cas_latency) | |
564 | { | |
565 | unsigned int smcr = SMCR_DTIM | SMCR_MBGE | FInsrt(drac, SMCR_DRAC); | |
566 | ||
567 | if (cas_latency == 3) | |
568 | smcr |= SMCR_CLAT; | |
569 | ||
570 | sa1111_writel(smcr, sachip->base + SA1111_SMCR); | |
571 | ||
572 | /* | |
573 | * Now clear the bits in the DMA mask to work around the SA1111 | |
574 | * DMA erratum (Intel StrongARM SA-1111 Microprocessor Companion | |
575 | * Chip Specification Update, June 2000, Erratum #7). | |
576 | */ | |
577 | if (sachip->dev->dma_mask) | |
578 | *sachip->dev->dma_mask &= sa1111_dma_mask[drac >> 2]; | |
579 | ||
580 | sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2]; | |
581 | } | |
0703ed2a | 582 | #endif |
1da177e4 | 583 | |
0703ed2a RK |
584 | #ifdef CONFIG_DMABOUNCE |
585 | /* | |
586 | * According to the "Intel StrongARM SA-1111 Microprocessor Companion | |
587 | * Chip Specification Update" (June 2000), erratum #7, there is a | |
588 | * significant bug in the SA1111 SDRAM shared memory controller. If | |
589 | * an access to a region of memory above 1MB relative to the bank base, | |
590 | * it is important that address bit 10 _NOT_ be asserted. Depending | |
591 | * on the configuration of the RAM, bit 10 may correspond to one | |
592 | * of several different (processor-relative) address bits. | |
593 | * | |
594 | * This routine only identifies whether or not a given DMA address | |
595 | * is susceptible to the bug. | |
596 | * | |
597 | * This should only get called for sa1111_device types due to the | |
598 | * way we configure our device dma_masks. | |
599 | */ | |
600 | static int sa1111_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) | |
601 | { | |
602 | /* | |
603 | * Section 4.6 of the "Intel StrongARM SA-1111 Development Module | |
604 | * User's Guide" mentions that jumpers R51 and R52 control the | |
605 | * target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or | |
606 | * SDRAM bank 1 on Neponset). The default configuration selects | |
607 | * Assabet, so any address in bank 1 is necessarily invalid. | |
608 | */ | |
609 | return (machine_is_assabet() || machine_is_pfs168()) && | |
610 | (addr >= 0xc8000000 || (addr + size) >= 0xc8000000); | |
611 | } | |
1da177e4 LT |
612 | #endif |
613 | ||
614 | static void sa1111_dev_release(struct device *_dev) | |
615 | { | |
616 | struct sa1111_dev *dev = SA1111_DEV(_dev); | |
617 | ||
618 | release_resource(&dev->res); | |
619 | kfree(dev); | |
620 | } | |
621 | ||
622 | static int | |
623 | sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent, | |
624 | struct sa1111_dev_info *info) | |
625 | { | |
626 | struct sa1111_dev *dev; | |
627 | int ret; | |
628 | ||
d2a02b93 | 629 | dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL); |
1da177e4 LT |
630 | if (!dev) { |
631 | ret = -ENOMEM; | |
632 | goto out; | |
633 | } | |
1da177e4 | 634 | |
3f978704 | 635 | dev_set_name(&dev->dev, "%4.4lx", info->offset); |
1da177e4 LT |
636 | dev->devid = info->devid; |
637 | dev->dev.parent = sachip->dev; | |
638 | dev->dev.bus = &sa1111_bus_type; | |
639 | dev->dev.release = sa1111_dev_release; | |
640 | dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask; | |
641 | dev->res.start = sachip->phys + info->offset; | |
642 | dev->res.end = dev->res.start + 511; | |
3f978704 | 643 | dev->res.name = dev_name(&dev->dev); |
1da177e4 LT |
644 | dev->res.flags = IORESOURCE_MEM; |
645 | dev->mapbase = sachip->base + info->offset; | |
646 | dev->skpcr_mask = info->skpcr_mask; | |
647 | memmove(dev->irq, info->irq, sizeof(dev->irq)); | |
648 | ||
649 | ret = request_resource(parent, &dev->res); | |
650 | if (ret) { | |
651 | printk("SA1111: failed to allocate resource for %s\n", | |
652 | dev->res.name); | |
3f978704 | 653 | dev_set_name(&dev->dev, NULL); |
1da177e4 LT |
654 | kfree(dev); |
655 | goto out; | |
656 | } | |
657 | ||
658 | ||
659 | ret = device_register(&dev->dev); | |
660 | if (ret) { | |
661 | release_resource(&dev->res); | |
662 | kfree(dev); | |
663 | goto out; | |
664 | } | |
665 | ||
957cf333 | 666 | #ifdef CONFIG_DMABOUNCE |
1da177e4 LT |
667 | /* |
668 | * If the parent device has a DMA mask associated with it, | |
669 | * propagate it down to the children. | |
670 | */ | |
671 | if (sachip->dev->dma_mask) { | |
672 | dev->dma_mask = *sachip->dev->dma_mask; | |
673 | dev->dev.dma_mask = &dev->dma_mask; | |
674 | ||
675 | if (dev->dma_mask != 0xffffffffUL) { | |
0703ed2a RK |
676 | ret = dmabounce_register_dev(&dev->dev, 1024, 4096, |
677 | sa1111_needs_bounce); | |
1da177e4 | 678 | if (ret) { |
fc3a8828 GKH |
679 | dev_err(&dev->dev, "SA1111: Failed to register" |
680 | " with dmabounce\n"); | |
1da177e4 LT |
681 | device_unregister(&dev->dev); |
682 | } | |
683 | } | |
684 | } | |
957cf333 | 685 | #endif |
1da177e4 LT |
686 | |
687 | out: | |
688 | return ret; | |
689 | } | |
690 | ||
691 | /** | |
692 | * sa1111_probe - probe for a single SA1111 chip. | |
693 | * @phys_addr: physical address of device. | |
694 | * | |
695 | * Probe for a SA1111 chip. This must be called | |
696 | * before any other SA1111-specific code. | |
697 | * | |
698 | * Returns: | |
699 | * %-ENODEV device not found. | |
700 | * %-EBUSY physical address already marked in-use. | |
701 | * %0 successful. | |
702 | */ | |
055d1965 | 703 | static int __devinit |
1da177e4 LT |
704 | __sa1111_probe(struct device *me, struct resource *mem, int irq) |
705 | { | |
706 | struct sa1111 *sachip; | |
707 | unsigned long id; | |
416112f8 | 708 | unsigned int has_devs; |
1da177e4 LT |
709 | int i, ret = -ENODEV; |
710 | ||
d2a02b93 | 711 | sachip = kzalloc(sizeof(struct sa1111), GFP_KERNEL); |
1da177e4 LT |
712 | if (!sachip) |
713 | return -ENOMEM; | |
714 | ||
13f75582 | 715 | sachip->clk = clk_get(me, "SA1111_CLK"); |
442a9022 | 716 | if (IS_ERR(sachip->clk)) { |
97d654f8 RK |
717 | ret = PTR_ERR(sachip->clk); |
718 | goto err_free; | |
719 | } | |
720 | ||
72ae00c9 RK |
721 | ret = clk_prepare(sachip->clk); |
722 | if (ret) | |
723 | goto err_clkput; | |
724 | ||
1da177e4 LT |
725 | spin_lock_init(&sachip->lock); |
726 | ||
727 | sachip->dev = me; | |
728 | dev_set_drvdata(sachip->dev, sachip); | |
729 | ||
730 | sachip->phys = mem->start; | |
731 | sachip->irq = irq; | |
732 | ||
733 | /* | |
734 | * Map the whole region. This also maps the | |
735 | * registers for our children. | |
736 | */ | |
737 | sachip->base = ioremap(mem->start, PAGE_SIZE * 2); | |
738 | if (!sachip->base) { | |
739 | ret = -ENOMEM; | |
72ae00c9 | 740 | goto err_clk_unprep; |
1da177e4 LT |
741 | } |
742 | ||
743 | /* | |
744 | * Probe for the chip. Only touch the SBI registers. | |
745 | */ | |
746 | id = sa1111_readl(sachip->base + SA1111_SKID); | |
747 | if ((id & SKID_ID_MASK) != SKID_SA1111_ID) { | |
748 | printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id); | |
749 | ret = -ENODEV; | |
97d654f8 | 750 | goto err_unmap; |
1da177e4 LT |
751 | } |
752 | ||
753 | printk(KERN_INFO "SA1111 Microprocessor Companion Chip: " | |
754 | "silicon revision %lx, metal revision %lx\n", | |
755 | (id & SKID_SIREV_MASK)>>4, (id & SKID_MTREV_MASK)); | |
756 | ||
757 | /* | |
758 | * We found it. Wake the chip up, and initialise. | |
759 | */ | |
760 | sa1111_wake(sachip); | |
761 | ||
762 | #ifdef CONFIG_ARCH_SA1100 | |
416112f8 DB |
763 | { |
764 | unsigned int val; | |
765 | ||
1da177e4 LT |
766 | /* |
767 | * The SDRAM configuration of the SA1110 and the SA1111 must | |
768 | * match. This is very important to ensure that SA1111 accesses | |
769 | * don't corrupt the SDRAM. Note that this ungates the SA1111's | |
770 | * MBGNT signal, so we must have called sa1110_mb_disable() | |
771 | * beforehand. | |
772 | */ | |
773 | sa1111_configure_smc(sachip, 1, | |
774 | FExtr(MDCNFG, MDCNFG_SA1110_DRAC0), | |
775 | FExtr(MDCNFG, MDCNFG_SA1110_TDL0)); | |
776 | ||
777 | /* | |
778 | * We only need to turn on DCLK whenever we want to use the | |
779 | * DMA. It can otherwise be held firmly in the off position. | |
780 | * (currently, we always enable it.) | |
781 | */ | |
782 | val = sa1111_readl(sachip->base + SA1111_SKPCR); | |
783 | sa1111_writel(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR); | |
784 | ||
785 | /* | |
786 | * Enable the SA1110 memory bus request and grant signals. | |
787 | */ | |
788 | sa1110_mb_enable(); | |
416112f8 | 789 | } |
1da177e4 LT |
790 | #endif |
791 | ||
792 | /* | |
793 | * The interrupt controller must be initialised before any | |
794 | * other device to ensure that the interrupts are available. | |
795 | */ | |
796 | if (sachip->irq != NO_IRQ) | |
797 | sa1111_setup_irq(sachip); | |
798 | ||
799 | g_sa1111 = sachip; | |
800 | ||
801 | has_devs = ~0; | |
802 | if (machine_is_assabet() || machine_is_jornada720() || | |
803 | machine_is_badge4()) | |
804 | has_devs &= ~(1 << 4); | |
805 | else | |
806 | has_devs &= ~(1 << 1); | |
807 | ||
808 | for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++) | |
809 | if (has_devs & (1 << i)) | |
810 | sa1111_init_one_child(sachip, mem, &sa1111_devices[i]); | |
811 | ||
812 | return 0; | |
813 | ||
97d654f8 | 814 | err_unmap: |
1da177e4 | 815 | iounmap(sachip->base); |
72ae00c9 RK |
816 | err_clk_unprep: |
817 | clk_unprepare(sachip->clk); | |
97d654f8 RK |
818 | err_clkput: |
819 | clk_put(sachip->clk); | |
820 | err_free: | |
1da177e4 LT |
821 | kfree(sachip); |
822 | return ret; | |
823 | } | |
824 | ||
522c37b9 RK |
825 | static int sa1111_remove_one(struct device *dev, void *data) |
826 | { | |
827 | device_unregister(dev); | |
828 | return 0; | |
829 | } | |
830 | ||
1da177e4 LT |
831 | static void __sa1111_remove(struct sa1111 *sachip) |
832 | { | |
1da177e4 LT |
833 | void __iomem *irqbase = sachip->base + SA1111_INTC; |
834 | ||
522c37b9 | 835 | device_for_each_child(sachip->dev, NULL, sa1111_remove_one); |
1da177e4 LT |
836 | |
837 | /* disable all IRQs */ | |
838 | sa1111_writel(0, irqbase + SA1111_INTEN0); | |
839 | sa1111_writel(0, irqbase + SA1111_INTEN1); | |
840 | sa1111_writel(0, irqbase + SA1111_WAKEEN0); | |
841 | sa1111_writel(0, irqbase + SA1111_WAKEEN1); | |
842 | ||
97d654f8 | 843 | clk_disable(sachip->clk); |
72ae00c9 | 844 | clk_unprepare(sachip->clk); |
97d654f8 | 845 | |
1da177e4 | 846 | if (sachip->irq != NO_IRQ) { |
6845664a TG |
847 | irq_set_chained_handler(sachip->irq, NULL); |
848 | irq_set_handler_data(sachip->irq, NULL); | |
1da177e4 LT |
849 | |
850 | release_mem_region(sachip->phys + SA1111_INTC, 512); | |
851 | } | |
852 | ||
853 | iounmap(sachip->base); | |
97d654f8 | 854 | clk_put(sachip->clk); |
1da177e4 LT |
855 | kfree(sachip); |
856 | } | |
857 | ||
1da177e4 LT |
858 | struct sa1111_save_data { |
859 | unsigned int skcr; | |
860 | unsigned int skpcr; | |
861 | unsigned int skcdr; | |
862 | unsigned char skaud; | |
863 | unsigned char skpwm0; | |
864 | unsigned char skpwm1; | |
865 | ||
866 | /* | |
867 | * Interrupt controller | |
868 | */ | |
869 | unsigned int intpol0; | |
870 | unsigned int intpol1; | |
871 | unsigned int inten0; | |
872 | unsigned int inten1; | |
873 | unsigned int wakepol0; | |
874 | unsigned int wakepol1; | |
875 | unsigned int wakeen0; | |
876 | unsigned int wakeen1; | |
877 | }; | |
878 | ||
879 | #ifdef CONFIG_PM | |
880 | ||
3ae5eaec | 881 | static int sa1111_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 882 | { |
3ae5eaec | 883 | struct sa1111 *sachip = platform_get_drvdata(dev); |
1da177e4 LT |
884 | struct sa1111_save_data *save; |
885 | unsigned long flags; | |
886 | unsigned int val; | |
887 | void __iomem *base; | |
888 | ||
1da177e4 LT |
889 | save = kmalloc(sizeof(struct sa1111_save_data), GFP_KERNEL); |
890 | if (!save) | |
891 | return -ENOMEM; | |
93160c63 | 892 | sachip->saved_state = save; |
1da177e4 LT |
893 | |
894 | spin_lock_irqsave(&sachip->lock, flags); | |
895 | ||
896 | /* | |
897 | * Save state. | |
898 | */ | |
899 | base = sachip->base; | |
900 | save->skcr = sa1111_readl(base + SA1111_SKCR); | |
901 | save->skpcr = sa1111_readl(base + SA1111_SKPCR); | |
902 | save->skcdr = sa1111_readl(base + SA1111_SKCDR); | |
903 | save->skaud = sa1111_readl(base + SA1111_SKAUD); | |
904 | save->skpwm0 = sa1111_readl(base + SA1111_SKPWM0); | |
905 | save->skpwm1 = sa1111_readl(base + SA1111_SKPWM1); | |
906 | ||
907 | base = sachip->base + SA1111_INTC; | |
908 | save->intpol0 = sa1111_readl(base + SA1111_INTPOL0); | |
909 | save->intpol1 = sa1111_readl(base + SA1111_INTPOL1); | |
910 | save->inten0 = sa1111_readl(base + SA1111_INTEN0); | |
911 | save->inten1 = sa1111_readl(base + SA1111_INTEN1); | |
912 | save->wakepol0 = sa1111_readl(base + SA1111_WAKEPOL0); | |
913 | save->wakepol1 = sa1111_readl(base + SA1111_WAKEPOL1); | |
914 | save->wakeen0 = sa1111_readl(base + SA1111_WAKEEN0); | |
915 | save->wakeen1 = sa1111_readl(base + SA1111_WAKEEN1); | |
916 | ||
917 | /* | |
918 | * Disable. | |
919 | */ | |
920 | val = sa1111_readl(sachip->base + SA1111_SKCR); | |
921 | sa1111_writel(val | SKCR_SLEEP, sachip->base + SA1111_SKCR); | |
922 | sa1111_writel(0, sachip->base + SA1111_SKPWM0); | |
923 | sa1111_writel(0, sachip->base + SA1111_SKPWM1); | |
924 | ||
97d654f8 RK |
925 | clk_disable(sachip->clk); |
926 | ||
1da177e4 LT |
927 | spin_unlock_irqrestore(&sachip->lock, flags); |
928 | ||
929 | return 0; | |
930 | } | |
931 | ||
932 | /* | |
933 | * sa1111_resume - Restore the SA1111 device state. | |
934 | * @dev: device to restore | |
1da177e4 LT |
935 | * |
936 | * Restore the general state of the SA1111; clock control and | |
937 | * interrupt controller. Other parts of the SA1111 must be | |
938 | * restored by their respective drivers, and must be called | |
939 | * via LDM after this function. | |
940 | */ | |
3ae5eaec | 941 | static int sa1111_resume(struct platform_device *dev) |
1da177e4 | 942 | { |
3ae5eaec | 943 | struct sa1111 *sachip = platform_get_drvdata(dev); |
1da177e4 LT |
944 | struct sa1111_save_data *save; |
945 | unsigned long flags, id; | |
946 | void __iomem *base; | |
947 | ||
93160c63 | 948 | save = sachip->saved_state; |
1da177e4 LT |
949 | if (!save) |
950 | return 0; | |
951 | ||
1da177e4 LT |
952 | /* |
953 | * Ensure that the SA1111 is still here. | |
954 | * FIXME: shouldn't do this here. | |
955 | */ | |
956 | id = sa1111_readl(sachip->base + SA1111_SKID); | |
957 | if ((id & SKID_ID_MASK) != SKID_SA1111_ID) { | |
958 | __sa1111_remove(sachip); | |
3ae5eaec | 959 | platform_set_drvdata(dev, NULL); |
1da177e4 LT |
960 | kfree(save); |
961 | return 0; | |
962 | } | |
963 | ||
964 | /* | |
965 | * First of all, wake up the chip. | |
966 | */ | |
967 | sa1111_wake(sachip); | |
3defb247 MV |
968 | |
969 | /* | |
970 | * Only lock for write ops. Also, sa1111_wake must be called with | |
971 | * released spinlock! | |
972 | */ | |
973 | spin_lock_irqsave(&sachip->lock, flags); | |
974 | ||
1da177e4 LT |
975 | sa1111_writel(0, sachip->base + SA1111_INTC + SA1111_INTEN0); |
976 | sa1111_writel(0, sachip->base + SA1111_INTC + SA1111_INTEN1); | |
977 | ||
978 | base = sachip->base; | |
979 | sa1111_writel(save->skcr, base + SA1111_SKCR); | |
980 | sa1111_writel(save->skpcr, base + SA1111_SKPCR); | |
981 | sa1111_writel(save->skcdr, base + SA1111_SKCDR); | |
982 | sa1111_writel(save->skaud, base + SA1111_SKAUD); | |
983 | sa1111_writel(save->skpwm0, base + SA1111_SKPWM0); | |
984 | sa1111_writel(save->skpwm1, base + SA1111_SKPWM1); | |
985 | ||
986 | base = sachip->base + SA1111_INTC; | |
987 | sa1111_writel(save->intpol0, base + SA1111_INTPOL0); | |
988 | sa1111_writel(save->intpol1, base + SA1111_INTPOL1); | |
989 | sa1111_writel(save->inten0, base + SA1111_INTEN0); | |
990 | sa1111_writel(save->inten1, base + SA1111_INTEN1); | |
991 | sa1111_writel(save->wakepol0, base + SA1111_WAKEPOL0); | |
992 | sa1111_writel(save->wakepol1, base + SA1111_WAKEPOL1); | |
993 | sa1111_writel(save->wakeen0, base + SA1111_WAKEEN0); | |
994 | sa1111_writel(save->wakeen1, base + SA1111_WAKEEN1); | |
995 | ||
996 | spin_unlock_irqrestore(&sachip->lock, flags); | |
997 | ||
93160c63 | 998 | sachip->saved_state = NULL; |
1da177e4 LT |
999 | kfree(save); |
1000 | ||
1001 | return 0; | |
1002 | } | |
1003 | ||
1004 | #else | |
1005 | #define sa1111_suspend NULL | |
1006 | #define sa1111_resume NULL | |
1007 | #endif | |
1008 | ||
5d43839a | 1009 | static int __devinit sa1111_probe(struct platform_device *pdev) |
1da177e4 | 1010 | { |
1da177e4 LT |
1011 | struct resource *mem; |
1012 | int irq; | |
1013 | ||
1014 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1015 | if (!mem) | |
1016 | return -EINVAL; | |
1017 | irq = platform_get_irq(pdev, 0); | |
48944738 DV |
1018 | if (irq < 0) |
1019 | return -ENXIO; | |
1da177e4 | 1020 | |
3ae5eaec | 1021 | return __sa1111_probe(&pdev->dev, mem, irq); |
1da177e4 LT |
1022 | } |
1023 | ||
3ae5eaec | 1024 | static int sa1111_remove(struct platform_device *pdev) |
1da177e4 | 1025 | { |
3ae5eaec | 1026 | struct sa1111 *sachip = platform_get_drvdata(pdev); |
1da177e4 LT |
1027 | |
1028 | if (sachip) { | |
1da177e4 | 1029 | #ifdef CONFIG_PM |
93160c63 RW |
1030 | kfree(sachip->saved_state); |
1031 | sachip->saved_state = NULL; | |
1da177e4 | 1032 | #endif |
f2d2420b JL |
1033 | __sa1111_remove(sachip); |
1034 | platform_set_drvdata(pdev, NULL); | |
1da177e4 LT |
1035 | } |
1036 | ||
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | /* | |
1041 | * Not sure if this should be on the system bus or not yet. | |
1042 | * We really want some way to register a system device at | |
1043 | * the per-machine level, and then have this driver pick | |
1044 | * up the registered devices. | |
1045 | * | |
1046 | * We also need to handle the SDRAM configuration for | |
1047 | * PXA250/SA1110 machine classes. | |
1048 | */ | |
3ae5eaec | 1049 | static struct platform_driver sa1111_device_driver = { |
1da177e4 LT |
1050 | .probe = sa1111_probe, |
1051 | .remove = sa1111_remove, | |
1052 | .suspend = sa1111_suspend, | |
1053 | .resume = sa1111_resume, | |
3ae5eaec RK |
1054 | .driver = { |
1055 | .name = "sa1111", | |
1056 | }, | |
1da177e4 LT |
1057 | }; |
1058 | ||
1059 | /* | |
1060 | * Get the parent device driver (us) structure | |
1061 | * from a child function device | |
1062 | */ | |
1063 | static inline struct sa1111 *sa1111_chip_driver(struct sa1111_dev *sadev) | |
1064 | { | |
1065 | return (struct sa1111 *)dev_get_drvdata(sadev->dev.parent); | |
1066 | } | |
1067 | ||
1068 | /* | |
1069 | * The bits in the opdiv field are non-linear. | |
1070 | */ | |
1071 | static unsigned char opdiv_table[] = { 1, 4, 2, 8 }; | |
1072 | ||
1073 | static unsigned int __sa1111_pll_clock(struct sa1111 *sachip) | |
1074 | { | |
1075 | unsigned int skcdr, fbdiv, ipdiv, opdiv; | |
1076 | ||
1077 | skcdr = sa1111_readl(sachip->base + SA1111_SKCDR); | |
1078 | ||
1079 | fbdiv = (skcdr & 0x007f) + 2; | |
1080 | ipdiv = ((skcdr & 0x0f80) >> 7) + 2; | |
1081 | opdiv = opdiv_table[(skcdr & 0x3000) >> 12]; | |
1082 | ||
1083 | return 3686400 * fbdiv / (ipdiv * opdiv); | |
1084 | } | |
1085 | ||
1086 | /** | |
1087 | * sa1111_pll_clock - return the current PLL clock frequency. | |
1088 | * @sadev: SA1111 function block | |
1089 | * | |
1090 | * BUG: we should look at SKCR. We also blindly believe that | |
1091 | * the chip is being fed with the 3.6864MHz clock. | |
1092 | * | |
1093 | * Returns the PLL clock in Hz. | |
1094 | */ | |
1095 | unsigned int sa1111_pll_clock(struct sa1111_dev *sadev) | |
1096 | { | |
1097 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1098 | ||
1099 | return __sa1111_pll_clock(sachip); | |
1100 | } | |
0a4bc5e8 | 1101 | EXPORT_SYMBOL(sa1111_pll_clock); |
1da177e4 LT |
1102 | |
1103 | /** | |
1104 | * sa1111_select_audio_mode - select I2S or AC link mode | |
1105 | * @sadev: SA1111 function block | |
1106 | * @mode: One of %SA1111_AUDIO_ACLINK or %SA1111_AUDIO_I2S | |
1107 | * | |
1108 | * Frob the SKCR to select AC Link mode or I2S mode for | |
1109 | * the audio block. | |
1110 | */ | |
1111 | void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode) | |
1112 | { | |
1113 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1114 | unsigned long flags; | |
1115 | unsigned int val; | |
1116 | ||
1117 | spin_lock_irqsave(&sachip->lock, flags); | |
1118 | ||
1119 | val = sa1111_readl(sachip->base + SA1111_SKCR); | |
1120 | if (mode == SA1111_AUDIO_I2S) { | |
1121 | val &= ~SKCR_SELAC; | |
1122 | } else { | |
1123 | val |= SKCR_SELAC; | |
1124 | } | |
1125 | sa1111_writel(val, sachip->base + SA1111_SKCR); | |
1126 | ||
1127 | spin_unlock_irqrestore(&sachip->lock, flags); | |
1128 | } | |
0a4bc5e8 | 1129 | EXPORT_SYMBOL(sa1111_select_audio_mode); |
1da177e4 LT |
1130 | |
1131 | /** | |
1132 | * sa1111_set_audio_rate - set the audio sample rate | |
1133 | * @sadev: SA1111 SAC function block | |
1134 | * @rate: sample rate to select | |
1135 | */ | |
1136 | int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate) | |
1137 | { | |
1138 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1139 | unsigned int div; | |
1140 | ||
1141 | if (sadev->devid != SA1111_DEVID_SAC) | |
1142 | return -EINVAL; | |
1143 | ||
1144 | div = (__sa1111_pll_clock(sachip) / 256 + rate / 2) / rate; | |
1145 | if (div == 0) | |
1146 | div = 1; | |
1147 | if (div > 128) | |
1148 | div = 128; | |
1149 | ||
1150 | sa1111_writel(div - 1, sachip->base + SA1111_SKAUD); | |
1151 | ||
1152 | return 0; | |
1153 | } | |
0a4bc5e8 | 1154 | EXPORT_SYMBOL(sa1111_set_audio_rate); |
1da177e4 LT |
1155 | |
1156 | /** | |
1157 | * sa1111_get_audio_rate - get the audio sample rate | |
1158 | * @sadev: SA1111 SAC function block device | |
1159 | */ | |
1160 | int sa1111_get_audio_rate(struct sa1111_dev *sadev) | |
1161 | { | |
1162 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1163 | unsigned long div; | |
1164 | ||
1165 | if (sadev->devid != SA1111_DEVID_SAC) | |
1166 | return -EINVAL; | |
1167 | ||
1168 | div = sa1111_readl(sachip->base + SA1111_SKAUD) + 1; | |
1169 | ||
1170 | return __sa1111_pll_clock(sachip) / (256 * div); | |
1171 | } | |
0a4bc5e8 | 1172 | EXPORT_SYMBOL(sa1111_get_audio_rate); |
1da177e4 LT |
1173 | |
1174 | void sa1111_set_io_dir(struct sa1111_dev *sadev, | |
1175 | unsigned int bits, unsigned int dir, | |
1176 | unsigned int sleep_dir) | |
1177 | { | |
1178 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1179 | unsigned long flags; | |
1180 | unsigned int val; | |
1181 | void __iomem *gpio = sachip->base + SA1111_GPIO; | |
1182 | ||
1183 | #define MODIFY_BITS(port, mask, dir) \ | |
1184 | if (mask) { \ | |
1185 | val = sa1111_readl(port); \ | |
1186 | val &= ~(mask); \ | |
1187 | val |= (dir) & (mask); \ | |
1188 | sa1111_writel(val, port); \ | |
1189 | } | |
1190 | ||
1191 | spin_lock_irqsave(&sachip->lock, flags); | |
1192 | MODIFY_BITS(gpio + SA1111_GPIO_PADDR, bits & 15, dir); | |
1193 | MODIFY_BITS(gpio + SA1111_GPIO_PBDDR, (bits >> 8) & 255, dir >> 8); | |
1194 | MODIFY_BITS(gpio + SA1111_GPIO_PCDDR, (bits >> 16) & 255, dir >> 16); | |
1195 | ||
1196 | MODIFY_BITS(gpio + SA1111_GPIO_PASDR, bits & 15, sleep_dir); | |
1197 | MODIFY_BITS(gpio + SA1111_GPIO_PBSDR, (bits >> 8) & 255, sleep_dir >> 8); | |
1198 | MODIFY_BITS(gpio + SA1111_GPIO_PCSDR, (bits >> 16) & 255, sleep_dir >> 16); | |
1199 | spin_unlock_irqrestore(&sachip->lock, flags); | |
1200 | } | |
0a4bc5e8 | 1201 | EXPORT_SYMBOL(sa1111_set_io_dir); |
1da177e4 LT |
1202 | |
1203 | void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v) | |
1204 | { | |
1205 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1206 | unsigned long flags; | |
1207 | unsigned int val; | |
1208 | void __iomem *gpio = sachip->base + SA1111_GPIO; | |
1209 | ||
1210 | spin_lock_irqsave(&sachip->lock, flags); | |
1211 | MODIFY_BITS(gpio + SA1111_GPIO_PADWR, bits & 15, v); | |
1212 | MODIFY_BITS(gpio + SA1111_GPIO_PBDWR, (bits >> 8) & 255, v >> 8); | |
1213 | MODIFY_BITS(gpio + SA1111_GPIO_PCDWR, (bits >> 16) & 255, v >> 16); | |
1214 | spin_unlock_irqrestore(&sachip->lock, flags); | |
1215 | } | |
0a4bc5e8 | 1216 | EXPORT_SYMBOL(sa1111_set_io); |
1da177e4 LT |
1217 | |
1218 | void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v) | |
1219 | { | |
1220 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1221 | unsigned long flags; | |
1222 | unsigned int val; | |
1223 | void __iomem *gpio = sachip->base + SA1111_GPIO; | |
1224 | ||
1225 | spin_lock_irqsave(&sachip->lock, flags); | |
1226 | MODIFY_BITS(gpio + SA1111_GPIO_PASSR, bits & 15, v); | |
1227 | MODIFY_BITS(gpio + SA1111_GPIO_PBSSR, (bits >> 8) & 255, v >> 8); | |
1228 | MODIFY_BITS(gpio + SA1111_GPIO_PCSSR, (bits >> 16) & 255, v >> 16); | |
1229 | spin_unlock_irqrestore(&sachip->lock, flags); | |
1230 | } | |
0a4bc5e8 | 1231 | EXPORT_SYMBOL(sa1111_set_sleep_io); |
1da177e4 LT |
1232 | |
1233 | /* | |
1234 | * Individual device operations. | |
1235 | */ | |
1236 | ||
1237 | /** | |
1238 | * sa1111_enable_device - enable an on-chip SA1111 function block | |
1239 | * @sadev: SA1111 function block device to enable | |
1240 | */ | |
1241 | void sa1111_enable_device(struct sa1111_dev *sadev) | |
1242 | { | |
1243 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1244 | unsigned long flags; | |
1245 | unsigned int val; | |
1246 | ||
1247 | spin_lock_irqsave(&sachip->lock, flags); | |
1248 | val = sa1111_readl(sachip->base + SA1111_SKPCR); | |
1249 | sa1111_writel(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR); | |
1250 | spin_unlock_irqrestore(&sachip->lock, flags); | |
1251 | } | |
0a4bc5e8 | 1252 | EXPORT_SYMBOL(sa1111_enable_device); |
1da177e4 LT |
1253 | |
1254 | /** | |
1255 | * sa1111_disable_device - disable an on-chip SA1111 function block | |
1256 | * @sadev: SA1111 function block device to disable | |
1257 | */ | |
1258 | void sa1111_disable_device(struct sa1111_dev *sadev) | |
1259 | { | |
1260 | struct sa1111 *sachip = sa1111_chip_driver(sadev); | |
1261 | unsigned long flags; | |
1262 | unsigned int val; | |
1263 | ||
1264 | spin_lock_irqsave(&sachip->lock, flags); | |
1265 | val = sa1111_readl(sachip->base + SA1111_SKPCR); | |
1266 | sa1111_writel(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR); | |
1267 | spin_unlock_irqrestore(&sachip->lock, flags); | |
1268 | } | |
0a4bc5e8 | 1269 | EXPORT_SYMBOL(sa1111_disable_device); |
1da177e4 LT |
1270 | |
1271 | /* | |
1272 | * SA1111 "Register Access Bus." | |
1273 | * | |
1274 | * We model this as a regular bus type, and hang devices directly | |
1275 | * off this. | |
1276 | */ | |
1277 | static int sa1111_match(struct device *_dev, struct device_driver *_drv) | |
1278 | { | |
1279 | struct sa1111_dev *dev = SA1111_DEV(_dev); | |
1280 | struct sa1111_driver *drv = SA1111_DRV(_drv); | |
1281 | ||
1282 | return dev->devid == drv->devid; | |
1283 | } | |
1284 | ||
1285 | static int sa1111_bus_suspend(struct device *dev, pm_message_t state) | |
1286 | { | |
1287 | struct sa1111_dev *sadev = SA1111_DEV(dev); | |
1288 | struct sa1111_driver *drv = SA1111_DRV(dev->driver); | |
1289 | int ret = 0; | |
1290 | ||
1291 | if (drv && drv->suspend) | |
1292 | ret = drv->suspend(sadev, state); | |
1293 | return ret; | |
1294 | } | |
1295 | ||
1296 | static int sa1111_bus_resume(struct device *dev) | |
1297 | { | |
1298 | struct sa1111_dev *sadev = SA1111_DEV(dev); | |
1299 | struct sa1111_driver *drv = SA1111_DRV(dev->driver); | |
1300 | int ret = 0; | |
1301 | ||
1302 | if (drv && drv->resume) | |
1303 | ret = drv->resume(sadev); | |
1304 | return ret; | |
1305 | } | |
1306 | ||
1307 | static int sa1111_bus_probe(struct device *dev) | |
1308 | { | |
1309 | struct sa1111_dev *sadev = SA1111_DEV(dev); | |
1310 | struct sa1111_driver *drv = SA1111_DRV(dev->driver); | |
1311 | int ret = -ENODEV; | |
1312 | ||
1313 | if (drv->probe) | |
1314 | ret = drv->probe(sadev); | |
1315 | return ret; | |
1316 | } | |
1317 | ||
1318 | static int sa1111_bus_remove(struct device *dev) | |
1319 | { | |
1320 | struct sa1111_dev *sadev = SA1111_DEV(dev); | |
1321 | struct sa1111_driver *drv = SA1111_DRV(dev->driver); | |
1322 | int ret = 0; | |
1323 | ||
1324 | if (drv->remove) | |
1325 | ret = drv->remove(sadev); | |
1326 | return ret; | |
1327 | } | |
1328 | ||
1329 | struct bus_type sa1111_bus_type = { | |
1330 | .name = "sa1111-rab", | |
1331 | .match = sa1111_match, | |
2876ba43 RK |
1332 | .probe = sa1111_bus_probe, |
1333 | .remove = sa1111_bus_remove, | |
1da177e4 LT |
1334 | .suspend = sa1111_bus_suspend, |
1335 | .resume = sa1111_bus_resume, | |
1336 | }; | |
0a4bc5e8 | 1337 | EXPORT_SYMBOL(sa1111_bus_type); |
1da177e4 LT |
1338 | |
1339 | int sa1111_driver_register(struct sa1111_driver *driver) | |
1340 | { | |
1da177e4 LT |
1341 | driver->drv.bus = &sa1111_bus_type; |
1342 | return driver_register(&driver->drv); | |
1343 | } | |
0a4bc5e8 | 1344 | EXPORT_SYMBOL(sa1111_driver_register); |
1da177e4 LT |
1345 | |
1346 | void sa1111_driver_unregister(struct sa1111_driver *driver) | |
1347 | { | |
1348 | driver_unregister(&driver->drv); | |
1349 | } | |
0a4bc5e8 | 1350 | EXPORT_SYMBOL(sa1111_driver_unregister); |
1da177e4 LT |
1351 | |
1352 | static int __init sa1111_init(void) | |
1353 | { | |
1354 | int ret = bus_register(&sa1111_bus_type); | |
1355 | if (ret == 0) | |
3ae5eaec | 1356 | platform_driver_register(&sa1111_device_driver); |
1da177e4 LT |
1357 | return ret; |
1358 | } | |
1359 | ||
1360 | static void __exit sa1111_exit(void) | |
1361 | { | |
3ae5eaec | 1362 | platform_driver_unregister(&sa1111_device_driver); |
1da177e4 LT |
1363 | bus_unregister(&sa1111_bus_type); |
1364 | } | |
1365 | ||
72724382 | 1366 | subsys_initcall(sa1111_init); |
1da177e4 LT |
1367 | module_exit(sa1111_exit); |
1368 | ||
1369 | MODULE_DESCRIPTION("Intel Corporation SA1111 core driver"); | |
1370 | MODULE_LICENSE("GPL"); |