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fa0fe48f RK |
1 | /* |
2 | * linux/arch/arm/common/vic.c | |
3 | * | |
4 | * Copyright (C) 1999 - 2003 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
bb06b737 | 21 | |
fa0fe48f RK |
22 | #include <linux/init.h> |
23 | #include <linux/list.h> | |
fced80c7 | 24 | #include <linux/io.h> |
328f5cc3 | 25 | #include <linux/syscore_ops.h> |
59fcf48f | 26 | #include <linux/device.h> |
f17a1f06 | 27 | #include <linux/amba/bus.h> |
fa0fe48f | 28 | |
fa0fe48f RK |
29 | #include <asm/mach/irq.h> |
30 | #include <asm/hardware/vic.h> | |
31 | ||
328f5cc3 | 32 | #ifdef CONFIG_PM |
c07f87f2 BD |
33 | /** |
34 | * struct vic_device - VIC PM device | |
c07f87f2 BD |
35 | * @irq: The IRQ number for the base of the VIC. |
36 | * @base: The register base for the VIC. | |
37 | * @resume_sources: A bitmask of interrupts for resume. | |
38 | * @resume_irqs: The IRQs enabled for resume. | |
39 | * @int_select: Save for VIC_INT_SELECT. | |
40 | * @int_enable: Save for VIC_INT_ENABLE. | |
41 | * @soft_int: Save for VIC_INT_SOFT. | |
42 | * @protect: Save for VIC_PROTECT. | |
43 | */ | |
44 | struct vic_device { | |
c07f87f2 BD |
45 | void __iomem *base; |
46 | int irq; | |
47 | u32 resume_sources; | |
48 | u32 resume_irqs; | |
49 | u32 int_select; | |
50 | u32 int_enable; | |
51 | u32 soft_int; | |
52 | u32 protect; | |
53 | }; | |
54 | ||
55 | /* we cannot allocate memory when VICs are initially registered */ | |
56 | static struct vic_device vic_devices[CONFIG_ARM_VIC_NR]; | |
57 | ||
bb06b737 | 58 | static int vic_id; |
bb06b737 | 59 | #endif /* CONFIG_PM */ |
c07f87f2 | 60 | |
bb06b737 HS |
61 | /** |
62 | * vic_init2 - common initialisation code | |
63 | * @base: Base of the VIC. | |
64 | * | |
b595076a | 65 | * Common initialisation code for registration |
bb06b737 HS |
66 | * and resume. |
67 | */ | |
68 | static void vic_init2(void __iomem *base) | |
69 | { | |
70 | int i; | |
71 | ||
72 | for (i = 0; i < 16; i++) { | |
73 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); | |
74 | writel(VIC_VECT_CNTL_ENABLE | i, reg); | |
75 | } | |
76 | ||
77 | writel(32, base + VIC_PL190_DEF_VECT_ADDR); | |
78 | } | |
c07f87f2 | 79 | |
328f5cc3 RW |
80 | #ifdef CONFIG_PM |
81 | static void resume_one_vic(struct vic_device *vic) | |
c07f87f2 | 82 | { |
c07f87f2 BD |
83 | void __iomem *base = vic->base; |
84 | ||
85 | printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); | |
86 | ||
87 | /* re-initialise static settings */ | |
88 | vic_init2(base); | |
89 | ||
90 | writel(vic->int_select, base + VIC_INT_SELECT); | |
91 | writel(vic->protect, base + VIC_PROTECT); | |
92 | ||
93 | /* set the enabled ints and then clear the non-enabled */ | |
94 | writel(vic->int_enable, base + VIC_INT_ENABLE); | |
95 | writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); | |
96 | ||
97 | /* and the same for the soft-int register */ | |
98 | ||
99 | writel(vic->soft_int, base + VIC_INT_SOFT); | |
100 | writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); | |
328f5cc3 | 101 | } |
c07f87f2 | 102 | |
328f5cc3 RW |
103 | static void vic_resume(void) |
104 | { | |
105 | int id; | |
106 | ||
107 | for (id = vic_id - 1; id >= 0; id--) | |
108 | resume_one_vic(vic_devices + id); | |
c07f87f2 BD |
109 | } |
110 | ||
328f5cc3 | 111 | static void suspend_one_vic(struct vic_device *vic) |
c07f87f2 | 112 | { |
c07f87f2 BD |
113 | void __iomem *base = vic->base; |
114 | ||
115 | printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base); | |
116 | ||
117 | vic->int_select = readl(base + VIC_INT_SELECT); | |
118 | vic->int_enable = readl(base + VIC_INT_ENABLE); | |
119 | vic->soft_int = readl(base + VIC_INT_SOFT); | |
120 | vic->protect = readl(base + VIC_PROTECT); | |
121 | ||
122 | /* set the interrupts (if any) that are used for | |
123 | * resuming the system */ | |
124 | ||
125 | writel(vic->resume_irqs, base + VIC_INT_ENABLE); | |
126 | writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); | |
328f5cc3 RW |
127 | } |
128 | ||
129 | static int vic_suspend(void) | |
130 | { | |
131 | int id; | |
132 | ||
133 | for (id = 0; id < vic_id; id++) | |
134 | suspend_one_vic(vic_devices + id); | |
c07f87f2 BD |
135 | |
136 | return 0; | |
137 | } | |
138 | ||
328f5cc3 RW |
139 | struct syscore_ops vic_syscore_ops = { |
140 | .suspend = vic_suspend, | |
141 | .resume = vic_resume, | |
c07f87f2 BD |
142 | }; |
143 | ||
c07f87f2 BD |
144 | /** |
145 | * vic_pm_init - initicall to register VIC pm | |
146 | * | |
147 | * This is called via late_initcall() to register | |
148 | * the resources for the VICs due to the early | |
149 | * nature of the VIC's registration. | |
150 | */ | |
151 | static int __init vic_pm_init(void) | |
152 | { | |
328f5cc3 RW |
153 | if (vic_id > 0) |
154 | register_syscore_ops(&vic_syscore_ops); | |
c07f87f2 BD |
155 | |
156 | return 0; | |
157 | } | |
c07f87f2 BD |
158 | late_initcall(vic_pm_init); |
159 | ||
bb06b737 HS |
160 | /** |
161 | * vic_pm_register - Register a VIC for later power management control | |
162 | * @base: The base address of the VIC. | |
163 | * @irq: The base IRQ for the VIC. | |
164 | * @resume_sources: bitmask of interrupts allowed for resume sources. | |
165 | * | |
166 | * Register the VIC with the system device tree so that it can be notified | |
167 | * of suspend and resume requests and ensure that the correct actions are | |
168 | * taken to re-instate the settings on resume. | |
169 | */ | |
170 | static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources) | |
171 | { | |
172 | struct vic_device *v; | |
173 | ||
174 | if (vic_id >= ARRAY_SIZE(vic_devices)) | |
175 | printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); | |
176 | else { | |
177 | v = &vic_devices[vic_id]; | |
178 | v->base = base; | |
179 | v->resume_sources = resume_sources; | |
180 | v->irq = irq; | |
181 | vic_id++; | |
182 | } | |
183 | } | |
184 | #else | |
185 | static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { } | |
186 | #endif /* CONFIG_PM */ | |
187 | ||
f013c98d | 188 | static void vic_ack_irq(struct irq_data *d) |
bb06b737 | 189 | { |
f013c98d LB |
190 | void __iomem *base = irq_data_get_irq_chip_data(d); |
191 | unsigned int irq = d->irq & 31; | |
bb06b737 HS |
192 | writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); |
193 | /* moreover, clear the soft-triggered, in case it was the reason */ | |
194 | writel(1 << irq, base + VIC_INT_SOFT_CLEAR); | |
195 | } | |
196 | ||
f013c98d | 197 | static void vic_mask_irq(struct irq_data *d) |
bb06b737 | 198 | { |
f013c98d LB |
199 | void __iomem *base = irq_data_get_irq_chip_data(d); |
200 | unsigned int irq = d->irq & 31; | |
bb06b737 HS |
201 | writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); |
202 | } | |
203 | ||
f013c98d | 204 | static void vic_unmask_irq(struct irq_data *d) |
bb06b737 | 205 | { |
f013c98d LB |
206 | void __iomem *base = irq_data_get_irq_chip_data(d); |
207 | unsigned int irq = d->irq & 31; | |
bb06b737 HS |
208 | writel(1 << irq, base + VIC_INT_ENABLE); |
209 | } | |
210 | ||
211 | #if defined(CONFIG_PM) | |
c07f87f2 BD |
212 | static struct vic_device *vic_from_irq(unsigned int irq) |
213 | { | |
214 | struct vic_device *v = vic_devices; | |
215 | unsigned int base_irq = irq & ~31; | |
216 | int id; | |
217 | ||
218 | for (id = 0; id < vic_id; id++, v++) { | |
219 | if (v->irq == base_irq) | |
220 | return v; | |
221 | } | |
222 | ||
223 | return NULL; | |
224 | } | |
225 | ||
f013c98d | 226 | static int vic_set_wake(struct irq_data *d, unsigned int on) |
c07f87f2 | 227 | { |
f013c98d LB |
228 | struct vic_device *v = vic_from_irq(d->irq); |
229 | unsigned int off = d->irq & 31; | |
3f1a567d | 230 | u32 bit = 1 << off; |
c07f87f2 BD |
231 | |
232 | if (!v) | |
233 | return -EINVAL; | |
234 | ||
3f1a567d BD |
235 | if (!(bit & v->resume_sources)) |
236 | return -EINVAL; | |
237 | ||
c07f87f2 | 238 | if (on) |
3f1a567d | 239 | v->resume_irqs |= bit; |
c07f87f2 | 240 | else |
3f1a567d | 241 | v->resume_irqs &= ~bit; |
c07f87f2 BD |
242 | |
243 | return 0; | |
244 | } | |
c07f87f2 | 245 | #else |
c07f87f2 BD |
246 | #define vic_set_wake NULL |
247 | #endif /* CONFIG_PM */ | |
248 | ||
38c677cb | 249 | static struct irq_chip vic_chip = { |
b0c4c898 | 250 | .name = "VIC", |
f013c98d LB |
251 | .irq_ack = vic_ack_irq, |
252 | .irq_mask = vic_mask_irq, | |
253 | .irq_unmask = vic_unmask_irq, | |
254 | .irq_set_wake = vic_set_wake, | |
fa0fe48f RK |
255 | }; |
256 | ||
b0c4c898 HS |
257 | static void __init vic_disable(void __iomem *base) |
258 | { | |
259 | writel(0, base + VIC_INT_SELECT); | |
260 | writel(0, base + VIC_INT_ENABLE); | |
261 | writel(~0, base + VIC_INT_ENABLE_CLEAR); | |
b0c4c898 HS |
262 | writel(0, base + VIC_ITCR); |
263 | writel(~0, base + VIC_INT_SOFT_CLEAR); | |
264 | } | |
265 | ||
266 | static void __init vic_clear_interrupts(void __iomem *base) | |
267 | { | |
268 | unsigned int i; | |
269 | ||
270 | writel(0, base + VIC_PL190_VECT_ADDR); | |
271 | for (i = 0; i < 19; i++) { | |
272 | unsigned int value; | |
273 | ||
274 | value = readl(base + VIC_PL190_VECT_ADDR); | |
275 | writel(value, base + VIC_PL190_VECT_ADDR); | |
276 | } | |
277 | } | |
278 | ||
279 | static void __init vic_set_irq_sources(void __iomem *base, | |
280 | unsigned int irq_start, u32 vic_sources) | |
281 | { | |
282 | unsigned int i; | |
283 | ||
284 | for (i = 0; i < 32; i++) { | |
285 | if (vic_sources & (1 << i)) { | |
286 | unsigned int irq = irq_start + i; | |
287 | ||
f38c02f3 TG |
288 | irq_set_chip_and_handler(irq, &vic_chip, |
289 | handle_level_irq); | |
9323f261 | 290 | irq_set_chip_data(irq, base); |
b0c4c898 HS |
291 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
292 | } | |
293 | } | |
294 | } | |
295 | ||
bb06b737 HS |
296 | /* |
297 | * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. | |
298 | * The original cell has 32 interrupts, while the modified one has 64, | |
299 | * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case | |
300 | * the probe function is called twice, with base set to offset 000 | |
301 | * and 020 within the page. We call this "second block". | |
302 | */ | |
303 | static void __init vic_init_st(void __iomem *base, unsigned int irq_start, | |
304 | u32 vic_sources) | |
305 | { | |
306 | unsigned int i; | |
307 | int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0; | |
308 | ||
309 | /* Disable all interrupts initially. */ | |
b0c4c898 | 310 | vic_disable(base); |
bb06b737 HS |
311 | |
312 | /* | |
313 | * Make sure we clear all existing interrupts. The vector registers | |
314 | * in this cell are after the second block of general registers, | |
315 | * so we can address them using standard offsets, but only from | |
316 | * the second base address, which is 0x20 in the page | |
317 | */ | |
318 | if (vic_2nd_block) { | |
b0c4c898 | 319 | vic_clear_interrupts(base); |
bb06b737 | 320 | |
bb06b737 HS |
321 | /* ST has 16 vectors as well, but we don't enable them by now */ |
322 | for (i = 0; i < 16; i++) { | |
323 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); | |
324 | writel(0, reg); | |
325 | } | |
326 | ||
327 | writel(32, base + VIC_PL190_DEF_VECT_ADDR); | |
328 | } | |
329 | ||
b0c4c898 | 330 | vic_set_irq_sources(base, irq_start, vic_sources); |
bb06b737 | 331 | } |
87e8824b | 332 | |
824b5b5e RK |
333 | /** |
334 | * vic_init - initialise a vectored interrupt controller | |
335 | * @base: iomem base address | |
336 | * @irq_start: starting interrupt number, must be muliple of 32 | |
337 | * @vic_sources: bitmask of interrupt sources to allow | |
c07f87f2 | 338 | * @resume_sources: bitmask of interrupt sources to allow for resume |
824b5b5e RK |
339 | */ |
340 | void __init vic_init(void __iomem *base, unsigned int irq_start, | |
c07f87f2 | 341 | u32 vic_sources, u32 resume_sources) |
fa0fe48f RK |
342 | { |
343 | unsigned int i; | |
87e8824b | 344 | u32 cellid = 0; |
f17a1f06 | 345 | enum amba_vendor vendor; |
87e8824b AR |
346 | |
347 | /* Identify which VIC cell this one is, by reading the ID */ | |
348 | for (i = 0; i < 4; i++) { | |
d4f3add2 AB |
349 | void __iomem *addr; |
350 | addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); | |
87e8824b AR |
351 | cellid |= (readl(addr) & 0xff) << (8 * i); |
352 | } | |
353 | vendor = (cellid >> 12) & 0xff; | |
354 | printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n", | |
355 | base, cellid, vendor); | |
356 | ||
357 | switch(vendor) { | |
f17a1f06 | 358 | case AMBA_VENDOR_ST: |
bb06b737 | 359 | vic_init_st(base, irq_start, vic_sources); |
87e8824b AR |
360 | return; |
361 | default: | |
362 | printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n"); | |
363 | /* fall through */ | |
f17a1f06 | 364 | case AMBA_VENDOR_ARM: |
87e8824b AR |
365 | break; |
366 | } | |
fa0fe48f | 367 | |
fa0fe48f | 368 | /* Disable all interrupts initially. */ |
b0c4c898 | 369 | vic_disable(base); |
fa0fe48f | 370 | |
b0c4c898 HS |
371 | /* Make sure we clear all existing interrupts */ |
372 | vic_clear_interrupts(base); | |
fa0fe48f | 373 | |
c07f87f2 | 374 | vic_init2(base); |
fa0fe48f | 375 | |
b0c4c898 | 376 | vic_set_irq_sources(base, irq_start, vic_sources); |
c07f87f2 BD |
377 | |
378 | vic_pm_register(base, irq_start, resume_sources); | |
fa0fe48f | 379 | } |