[deliverable/linux.git] / arch / arm / common / vic.c

/*
 *  linux/arch/arm/common/vic.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/sysdev.h>

#include <asm/mach/irq.h>
#include <asm/hardware/vic.h>

static void vic_ack_irq(unsigned int irq)
{
	void __iomem *base = get_irq_chip_data(irq);
	irq &= 31;
	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
	/* moreover, clear the soft-triggered, in case it was the reason */
	writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
}

static void vic_mask_irq(unsigned int irq)
{
	void __iomem *base = get_irq_chip_data(irq);
	irq &= 31;
	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
}

static void vic_unmask_irq(unsigned int irq)
{
	void __iomem *base = get_irq_chip_data(irq);
	irq &= 31;
	writel(1 << irq, base + VIC_INT_ENABLE);
}

/**
 * vic_init2 - common initialisation code
 * @base: Base of the VIC.
 *
 * Common initialisation code for registeration
 * and resume.
*/
static void vic_init2(void __iomem *base)
{
	int i;

	for (i = 0; i < 16; i++) {
		void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
		writel(VIC_VECT_CNTL_ENABLE | i, reg);
	}

	writel(32, base + VIC_PL190_DEF_VECT_ADDR);
}

#if defined(CONFIG_PM)
/**
 * struct vic_device - VIC PM device
 * @sysdev: The system device which is registered.
 * @irq: The IRQ number for the base of the VIC.
 * @base: The register base for the VIC.
 * @resume_sources: A bitmask of interrupts for resume.
 * @resume_irqs: The IRQs enabled for resume.
 * @int_select: Save for VIC_INT_SELECT.
 * @int_enable: Save for VIC_INT_ENABLE.
 * @soft_int: Save for VIC_INT_SOFT.
 * @protect: Save for VIC_PROTECT.
 */
struct vic_device {
	struct sys_device sysdev;

	void __iomem	*base;
	int		irq;
	u32		resume_sources;
	u32		resume_irqs;
	u32		int_select;
	u32		int_enable;
	u32		soft_int;
	u32		protect;
};

/* we cannot allocate memory when VICs are initially registered */
static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];

static inline struct vic_device *to_vic(struct sys_device *sys)
{
	return container_of(sys, struct vic_device, sysdev);
}

static int vic_id;

static int vic_class_resume(struct sys_device *dev)
{
	struct vic_device *vic = to_vic(dev);
	void __iomem *base = vic->base;

	printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);

	/* re-initialise static settings */
	vic_init2(base);

	writel(vic->int_select, base + VIC_INT_SELECT);
	writel(vic->protect, base + VIC_PROTECT);

	/* set the enabled ints and then clear the non-enabled */
	writel(vic->int_enable, base + VIC_INT_ENABLE);
	writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);

	/* and the same for the soft-int register */

	writel(vic->soft_int, base + VIC_INT_SOFT);
	writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);

	return 0;
}

static int vic_class_suspend(struct sys_device *dev, pm_message_t state)
{
	struct vic_device *vic = to_vic(dev);
	void __iomem *base = vic->base;

	printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);

	vic->int_select = readl(base + VIC_INT_SELECT);
	vic->int_enable = readl(base + VIC_INT_ENABLE);
	vic->soft_int = readl(base + VIC_INT_SOFT);
	vic->protect = readl(base + VIC_PROTECT);

	/* set the interrupts (if any) that are used for
	 * resuming the system */

	writel(vic->resume_irqs, base + VIC_INT_ENABLE);
	writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);

	return 0;
}

struct sysdev_class vic_class = {
	.name		= "vic",
	.suspend	= vic_class_suspend,
	.resume		= vic_class_resume,
};

/**
 * vic_pm_register - Register a VIC for later power management control
 * @base: The base address of the VIC.
 * @irq: The base IRQ for the VIC.
 * @resume_sources: bitmask of interrupts allowed for resume sources.
 *
 * Register the VIC with the system device tree so that it can be notified
 * of suspend and resume requests and ensure that the correct actions are
 * taken to re-instate the settings on resume.
 */
static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
{
	struct vic_device *v;

	if (vic_id >= ARRAY_SIZE(vic_devices))
		printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
	else {
		v = &vic_devices[vic_id];
		v->base = base;
		v->resume_sources = resume_sources;
		v->irq = irq;
		vic_id++;
	}
}

/**
 * vic_pm_init - initicall to register VIC pm
 *
 * This is called via late_initcall() to register
 * the resources for the VICs due to the early
 * nature of the VIC's registration.
*/
static int __init vic_pm_init(void)
{
	struct vic_device *dev = vic_devices;
	int err;
	int id;

	if (vic_id == 0)
		return 0;

	err = sysdev_class_register(&vic_class);
	if (err) {
		printk(KERN_ERR "%s: cannot register class\n", __func__);
		return err;
	}

	for (id = 0; id < vic_id; id++, dev++) {
		dev->sysdev.id = id;
		dev->sysdev.cls = &vic_class;

		err = sysdev_register(&dev->sysdev);
		if (err) {
			printk(KERN_ERR "%s: failed to register device\n",
			       __func__);
			return err;
		}
	}

	return 0;
}

late_initcall(vic_pm_init);

static struct vic_device *vic_from_irq(unsigned int irq)
{
        struct vic_device *v = vic_devices;
	unsigned int base_irq = irq & ~31;
	int id;

	for (id = 0; id < vic_id; id++, v++) {
		if (v->irq == base_irq)
			return v;
	}

	return NULL;
}

static int vic_set_wake(unsigned int irq, unsigned int on)
{
	struct vic_device *v = vic_from_irq(irq);
	unsigned int off = irq & 31;
	u32 bit = 1 << off;

	if (!v)
		return -EINVAL;

	if (!(bit & v->resume_sources))
		return -EINVAL;

	if (on)
		v->resume_irqs |= bit;
	else
		v->resume_irqs &= ~bit;

	return 0;
}

#else
static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }

#define vic_set_wake NULL
#endif /* CONFIG_PM */

static struct irq_chip vic_chip = {
	.name	= "VIC",
	.ack	= vic_ack_irq,
	.mask	= vic_mask_irq,
	.unmask	= vic_unmask_irq,
	.set_wake = vic_set_wake,
};

/* The PL190 cell from ARM has been modified by ST, so handle both here */
static void vik_init_st(void __iomem *base, unsigned int irq_start,
			 u32 vic_sources);

enum vic_vendor {
	VENDOR_ARM = 0x41,
	VENDOR_ST = 0x80,
};

/**
 * vic_init - initialise a vectored interrupt controller
 * @base: iomem base address
 * @irq_start: starting interrupt number, must be muliple of 32
 * @vic_sources: bitmask of interrupt sources to allow
 * @resume_sources: bitmask of interrupt sources to allow for resume
 */
void __init vic_init(void __iomem *base, unsigned int irq_start,
		     u32 vic_sources, u32 resume_sources)
{
	unsigned int i;
	u32 cellid = 0;
	enum vic_vendor vendor;

	/* Identify which VIC cell this one is, by reading the ID */
	for (i = 0; i < 4; i++) {
		u32 addr = ((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
		cellid |= (readl(addr) & 0xff) << (8 * i);
	}
	vendor = (cellid >> 12) & 0xff;
	printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
	       base, cellid, vendor);

	switch(vendor) {
	case VENDOR_ST:
		vik_init_st(base, irq_start, vic_sources);
		return;
	default:
		printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
		/* fall through */
	case VENDOR_ARM:
		break;
	}

	/* Disable all interrupts initially. */

	writel(0, base + VIC_INT_SELECT);
	writel(0, base + VIC_INT_ENABLE);
	writel(~0, base + VIC_INT_ENABLE_CLEAR);
	writel(0, base + VIC_IRQ_STATUS);
	writel(0, base + VIC_ITCR);
	writel(~0, base + VIC_INT_SOFT_CLEAR);

	/*
	 * Make sure we clear all existing interrupts
	 */
	writel(0, base + VIC_PL190_VECT_ADDR);
	for (i = 0; i < 19; i++) {
		unsigned int value;

		value = readl(base + VIC_PL190_VECT_ADDR);
		writel(value, base + VIC_PL190_VECT_ADDR);
	}

	vic_init2(base);

	for (i = 0; i < 32; i++) {
		if (vic_sources & (1 << i)) {
			unsigned int irq = irq_start + i;

			set_irq_chip(irq, &vic_chip);
			set_irq_chip_data(irq, base);
			set_irq_handler(irq, handle_level_irq);
			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
		}
	}

	vic_pm_register(base, irq_start, resume_sources);
}

/*
 * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
 * The original cell has 32 interrupts, while the modified one has 64,
 * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
 * the probe function is called twice, with base set to offset 000
 *  and 020 within the page. We call this "second block".
 */
static void __init vik_init_st(void __iomem *base, unsigned int irq_start,
				u32 vic_sources)
{
	unsigned int i;
	int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;

	/* Disable all interrupts initially. */

	writel(0, base + VIC_INT_SELECT);
	writel(0, base + VIC_INT_ENABLE);
	writel(~0, base + VIC_INT_ENABLE_CLEAR);
	writel(0, base + VIC_IRQ_STATUS);
	writel(0, base + VIC_ITCR);
	writel(~0, base + VIC_INT_SOFT_CLEAR);

	/*
	 * Make sure we clear all existing interrupts. The vector registers
	 * in this cell are after the second block of general registers,
	 * so we can address them using standard offsets, but only from
	 * the second base address, which is 0x20 in the page
	 */
	if (vic_2nd_block) {
		writel(0, base + VIC_PL190_VECT_ADDR);
		for (i = 0; i < 19; i++) {
			unsigned int value;

			value = readl(base + VIC_PL190_VECT_ADDR);
			writel(value, base + VIC_PL190_VECT_ADDR);
		}
		/* ST has 16 vectors as well, but we don't enable them by now */
		for (i = 0; i < 16; i++) {
			void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
			writel(0, reg);
		}

		writel(32, base + VIC_PL190_DEF_VECT_ADDR);
	}

	for (i = 0; i < 32; i++) {
		if (vic_sources & (1 << i)) {
			unsigned int irq = irq_start + i;

			set_irq_chip(irq, &vic_chip);
			set_irq_chip_data(irq, base);
			set_irq_handler(irq, handle_level_irq);
			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
		}
	}
}
Commit	Line	Data
fa0fe48f RK	1	/*
	2	* linux/arch/arm/common/vic.c
	3	*
	4	* Copyright (C) 1999 - 2003 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21	#include <linux/init.h>
	22	#include <linux/list.h>
fced80c7	23	#include <linux/io.h>
c07f87f2	24	#include <linux/sysdev.h>
fa0fe48f	25
fa0fe48f RK	26	#include <asm/mach/irq.h>
	27	#include <asm/hardware/vic.h>
	28
8c81b524 AR	29	static void vic_ack_irq(unsigned int irq)
	30	{
	31	void __iomem *base = get_irq_chip_data(irq);
	32	irq &= 31;
	33	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
	34	/* moreover, clear the soft-triggered, in case it was the reason */
	35	writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
	36	}
	37
fa0fe48f RK	38	static void vic_mask_irq(unsigned int irq)
fa0fe48f RK	39	{
10dd5ce2	40	void __iomem *base = get_irq_chip_data(irq);
824b5b5e RK	41	irq &= 31;
824b5b5e RK	42	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
fa0fe48f RK	43	}
	44
	45	static void vic_unmask_irq(unsigned int irq)
	46	{
10dd5ce2	47	void __iomem *base = get_irq_chip_data(irq);
824b5b5e RK	48	irq &= 31;
824b5b5e RK	49	writel(1 << irq, base + VIC_INT_ENABLE);
fa0fe48f RK	50	}
fa0fe48f RK	51
c07f87f2 BD	52	/**
	53	* vic_init2 - common initialisation code
	54	* @base: Base of the VIC.
	55	*
	56	* Common initialisation code for registeration
	57	* and resume.
	58	*/
	59	static void vic_init2(void __iomem *base)
	60	{
	61	int i;
	62
	63	for (i = 0; i < 16; i++) {
	64	void __iomem reg = base + VIC_VECT_CNTL0 + (i 4);
	65	writel(VIC_VECT_CNTL_ENABLE \| i, reg);
	66	}
	67
	68	writel(32, base + VIC_PL190_DEF_VECT_ADDR);
	69	}
	70
	71	#if defined(CONFIG_PM)
	72	/**
	73	* struct vic_device - VIC PM device
	74	* @sysdev: The system device which is registered.
	75	* @irq: The IRQ number for the base of the VIC.
	76	* @base: The register base for the VIC.
	77	* @resume_sources: A bitmask of interrupts for resume.
	78	* @resume_irqs: The IRQs enabled for resume.
	79	* @int_select: Save for VIC_INT_SELECT.
	80	* @int_enable: Save for VIC_INT_ENABLE.
	81	* @soft_int: Save for VIC_INT_SOFT.
	82	* @protect: Save for VIC_PROTECT.
	83	*/
	84	struct vic_device {
	85	struct sys_device sysdev;
	86
	87	void __iomem *base;
	88	int irq;
	89	u32 resume_sources;
	90	u32 resume_irqs;
	91	u32 int_select;
	92	u32 int_enable;
	93	u32 soft_int;
	94	u32 protect;
	95	};
	96
	97	/* we cannot allocate memory when VICs are initially registered */
	98	static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
	99
	100	static inline struct vic_device to_vic(struct sys_device sys)
	101	{
	102	return container_of(sys, struct vic_device, sysdev);
	103	}
	104
	105	static int vic_id;
	106
	107	static int vic_class_resume(struct sys_device *dev)
	108	{
	109	struct vic_device *vic = to_vic(dev);
	110	void __iomem *base = vic->base;
	111
	112	printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
	113
	114	/* re-initialise static settings */
	115	vic_init2(base);
116
117	writel(vic->int_select, base + VIC_INT_SELECT);
118	writel(vic->protect, base + VIC_PROTECT);
119
120	/* set the enabled ints and then clear the non-enabled */
121	writel(vic->int_enable, base + VIC_INT_ENABLE);
122	writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
123
124	/* and the same for the soft-int register */
125
126	writel(vic->soft_int, base + VIC_INT_SOFT);
127	writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
128
129	return 0;
130	}
131
132	static int vic_class_suspend(struct sys_device *dev, pm_message_t state)
133	{
134	struct vic_device *vic = to_vic(dev);
135	void __iomem *base = vic->base;
136
137	printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
138
139	vic->int_select = readl(base + VIC_INT_SELECT);
140	vic->int_enable = readl(base + VIC_INT_ENABLE);
141	vic->soft_int = readl(base + VIC_INT_SOFT);
142	vic->protect = readl(base + VIC_PROTECT);
143
144	/* set the interrupts (if any) that are used for
145	* resuming the system */
146
147	writel(vic->resume_irqs, base + VIC_INT_ENABLE);
148	writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
149
150	return 0;
151	}
152
153	struct sysdev_class vic_class = {
154	.name = "vic",
155	.suspend = vic_class_suspend,
156	.resume = vic_class_resume,
157	};
158
159	/**
160	* vic_pm_register - Register a VIC for later power management control
161	* @base: The base address of the VIC.
162	* @irq: The base IRQ for the VIC.
163	* @resume_sources: bitmask of interrupts allowed for resume sources.
164	*
165	* Register the VIC with the system device tree so that it can be notified
166	* of suspend and resume requests and ensure that the correct actions are
167	* taken to re-instate the settings on resume.
168	*/
169	static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
170	{
171	struct vic_device *v;
172
173	if (vic_id >= ARRAY_SIZE(vic_devices))
174	printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
175	else {
176	v = &vic_devices[vic_id];
177	v->base = base;
178	v->resume_sources = resume_sources;
179	v->irq = irq;
180	vic_id++;
181	}
182	}
183
184	/**
185	* vic_pm_init - initicall to register VIC pm
186	*
187	* This is called via late_initcall() to register
188	* the resources for the VICs due to the early
189	* nature of the VIC's registration.
190	*/
191	static int __init vic_pm_init(void)
192	{
193	struct vic_device *dev = vic_devices;
194	int err;
195	int id;
196
197	if (vic_id == 0)
198	return 0;
199
200	err = sysdev_class_register(&vic_class);
201	if (err) {
202	printk(KERN_ERR "%s: cannot register class\n", __func__);
203	return err;
204	}
205
206	for (id = 0; id < vic_id; id++, dev++) {
207	dev->sysdev.id = id;
208	dev->sysdev.cls = &vic_class;
209
210	err = sysdev_register(&dev->sysdev);
211	if (err) {
212	printk(KERN_ERR "%s: failed to register device\n",
213	__func__);
214	return err;
215	}
216	}
217
218	return 0;
219	}
220
221	late_initcall(vic_pm_init);
222
223	static struct vic_device *vic_from_irq(unsigned int irq)
224	{
225	struct vic_device *v = vic_devices;
226	unsigned int base_irq = irq & ~31;
227	int id;
228
229	for (id = 0; id < vic_id; id++, v++) {
230	if (v->irq == base_irq)
231	return v;
232	}
233
234	return NULL;
235	}
236
237	static int vic_set_wake(unsigned int irq, unsigned int on)
238	{
239	struct vic_device *v = vic_from_irq(irq);
240	unsigned int off = irq & 31;
3f1a567d	241	u32 bit = 1 << off;
c07f87f2 BD	242
	243	if (!v)
	244	return -EINVAL;
	245
3f1a567d BD	246	if (!(bit & v->resume_sources))
	247	return -EINVAL;
	248
c07f87f2	249	if (on)
3f1a567d	250	v->resume_irqs \|= bit;
c07f87f2	251	else
3f1a567d	252	v->resume_irqs &= ~bit;
c07f87f2 BD	253
	254	return 0;
	255	}
	256
	257	#else
	258	static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
	259
	260	#define vic_set_wake NULL
	261	#endif /* CONFIG_PM */
	262
38c677cb DB	263	static struct irq_chip vic_chip = {
38c677cb DB	264	.name = "VIC",
8c81b524	265	.ack = vic_ack_irq,
fa0fe48f RK	266	.mask = vic_mask_irq,
fa0fe48f RK	267	.unmask = vic_unmask_irq,
c07f87f2	268	.set_wake = vic_set_wake,
fa0fe48f RK	269	};
fa0fe48f RK	270
87e8824b AR	271	/* The PL190 cell from ARM has been modified by ST, so handle both here */
	272	static void vik_init_st(void __iomem *base, unsigned int irq_start,
	273	u32 vic_sources);
	274
	275	enum vic_vendor {
	276	VENDOR_ARM = 0x41,
	277	VENDOR_ST = 0x80,
	278	};
	279
824b5b5e RK	280	/**
	281	* vic_init - initialise a vectored interrupt controller
	282	* @base: iomem base address
	283	* @irq_start: starting interrupt number, must be muliple of 32
	284	* @vic_sources: bitmask of interrupt sources to allow
c07f87f2	285	* @resume_sources: bitmask of interrupt sources to allow for resume
824b5b5e RK	286	*/
824b5b5e RK	287	void __init vic_init(void __iomem *base, unsigned int irq_start,
c07f87f2	288	u32 vic_sources, u32 resume_sources)
fa0fe48f RK	289	{
fa0fe48f RK	290	unsigned int i;
87e8824b AR	291	u32 cellid = 0;
	292	enum vic_vendor vendor;
	293
	294	/* Identify which VIC cell this one is, by reading the ID */
	295	for (i = 0; i < 4; i++) {
	296	u32 addr = ((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
	297	cellid \|= (readl(addr) & 0xff) << (8 * i);
	298	}
	299	vendor = (cellid >> 12) & 0xff;
	300	printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
	301	base, cellid, vendor);
	302
	303	switch(vendor) {
	304	case VENDOR_ST:
	305	vik_init_st(base, irq_start, vic_sources);
	306	return;
	307	default:
	308	printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
	309	/* fall through */
	310	case VENDOR_ARM:
	311	break;
	312	}
fa0fe48f	313
fa0fe48f RK	314	/* Disable all interrupts initially. */
fa0fe48f RK	315
824b5b5e RK	316	writel(0, base + VIC_INT_SELECT);
	317	writel(0, base + VIC_INT_ENABLE);
	318	writel(~0, base + VIC_INT_ENABLE_CLEAR);
	319	writel(0, base + VIC_IRQ_STATUS);
	320	writel(0, base + VIC_ITCR);
	321	writel(~0, base + VIC_INT_SOFT_CLEAR);
fa0fe48f RK	322
	323	/*
	324	* Make sure we clear all existing interrupts
	325	*/
a801cd61	326	writel(0, base + VIC_PL190_VECT_ADDR);
fa0fe48f RK	327	for (i = 0; i < 19; i++) {
	328	unsigned int value;
	329
a801cd61 BD	330	value = readl(base + VIC_PL190_VECT_ADDR);
a801cd61 BD	331	writel(value, base + VIC_PL190_VECT_ADDR);
fa0fe48f RK	332	}
fa0fe48f RK	333
c07f87f2	334	vic_init2(base);
fa0fe48f RK	335
fa0fe48f RK	336	for (i = 0; i < 32; i++) {
fa0fe48f	337	if (vic_sources & (1 << i)) {
77f4025b LW	338	unsigned int irq = irq_start + i;
	339
	340	set_irq_chip(irq, &vic_chip);
	341	set_irq_chip_data(irq, base);
10dd5ce2	342	set_irq_handler(irq, handle_level_irq);
fa0fe48f RK	343	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	344	}
	345	}
c07f87f2 BD	346
c07f87f2 BD	347	vic_pm_register(base, irq_start, resume_sources);
fa0fe48f	348	}
87e8824b AR	349
	350	/*
	351	* The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
	352	* The original cell has 32 interrupts, while the modified one has 64,
	353	* replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
	354	* the probe function is called twice, with base set to offset 000
	355	* and 020 within the page. We call this "second block".
	356	*/
	357	static void __init vik_init_st(void __iomem *base, unsigned int irq_start,
	358	u32 vic_sources)
	359	{
	360	unsigned int i;
	361	int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
	362
	363	/* Disable all interrupts initially. */
	364
	365	writel(0, base + VIC_INT_SELECT);
	366	writel(0, base + VIC_INT_ENABLE);
	367	writel(~0, base + VIC_INT_ENABLE_CLEAR);
	368	writel(0, base + VIC_IRQ_STATUS);
	369	writel(0, base + VIC_ITCR);
	370	writel(~0, base + VIC_INT_SOFT_CLEAR);
	371
	372	/*
	373	* Make sure we clear all existing interrupts. The vector registers
	374	* in this cell are after the second block of general registers,
	375	* so we can address them using standard offsets, but only from
	376	* the second base address, which is 0x20 in the page
	377	*/
	378	if (vic_2nd_block) {
	379	writel(0, base + VIC_PL190_VECT_ADDR);
	380	for (i = 0; i < 19; i++) {
	381	unsigned int value;
	382
	383	value = readl(base + VIC_PL190_VECT_ADDR);
	384	writel(value, base + VIC_PL190_VECT_ADDR);
	385	}
	386	/* ST has 16 vectors as well, but we don't enable them by now */
	387	for (i = 0; i < 16; i++) {
	388	void __iomem reg = base + VIC_VECT_CNTL0 + (i 4);
	389	writel(0, reg);
	390	}
	391
	392	writel(32, base + VIC_PL190_DEF_VECT_ADDR);
	393	}
	394
	395	for (i = 0; i < 32; i++) {
	396	if (vic_sources & (1 << i)) {
	397	unsigned int irq = irq_start + i;
	398
	399	set_irq_chip(irq, &vic_chip);
	400	set_irq_chip_data(irq, base);
	401	set_irq_handler(irq, handle_level_irq);
	402	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	403	}
	404	}
	405	}