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fa0fe48f RK |
1 | /* |
2 | * linux/arch/arm/common/vic.c | |
3 | * | |
4 | * Copyright (C) 1999 - 2003 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | #include <linux/init.h> | |
22 | #include <linux/list.h> | |
fced80c7 | 23 | #include <linux/io.h> |
c07f87f2 | 24 | #include <linux/sysdev.h> |
59fcf48f | 25 | #include <linux/device.h> |
f17a1f06 | 26 | #include <linux/amba/bus.h> |
fa0fe48f | 27 | |
fa0fe48f RK |
28 | #include <asm/mach/irq.h> |
29 | #include <asm/hardware/vic.h> | |
30 | ||
8c81b524 AR |
31 | static void vic_ack_irq(unsigned int irq) |
32 | { | |
33 | void __iomem *base = get_irq_chip_data(irq); | |
34 | irq &= 31; | |
35 | writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); | |
36 | /* moreover, clear the soft-triggered, in case it was the reason */ | |
37 | writel(1 << irq, base + VIC_INT_SOFT_CLEAR); | |
38 | } | |
39 | ||
fa0fe48f RK |
40 | static void vic_mask_irq(unsigned int irq) |
41 | { | |
10dd5ce2 | 42 | void __iomem *base = get_irq_chip_data(irq); |
824b5b5e RK |
43 | irq &= 31; |
44 | writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); | |
fa0fe48f RK |
45 | } |
46 | ||
47 | static void vic_unmask_irq(unsigned int irq) | |
48 | { | |
10dd5ce2 | 49 | void __iomem *base = get_irq_chip_data(irq); |
824b5b5e RK |
50 | irq &= 31; |
51 | writel(1 << irq, base + VIC_INT_ENABLE); | |
fa0fe48f RK |
52 | } |
53 | ||
c07f87f2 BD |
54 | /** |
55 | * vic_init2 - common initialisation code | |
56 | * @base: Base of the VIC. | |
57 | * | |
58 | * Common initialisation code for registeration | |
59 | * and resume. | |
60 | */ | |
61 | static void vic_init2(void __iomem *base) | |
62 | { | |
63 | int i; | |
64 | ||
65 | for (i = 0; i < 16; i++) { | |
66 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); | |
67 | writel(VIC_VECT_CNTL_ENABLE | i, reg); | |
68 | } | |
69 | ||
70 | writel(32, base + VIC_PL190_DEF_VECT_ADDR); | |
71 | } | |
72 | ||
73 | #if defined(CONFIG_PM) | |
74 | /** | |
75 | * struct vic_device - VIC PM device | |
76 | * @sysdev: The system device which is registered. | |
77 | * @irq: The IRQ number for the base of the VIC. | |
78 | * @base: The register base for the VIC. | |
79 | * @resume_sources: A bitmask of interrupts for resume. | |
80 | * @resume_irqs: The IRQs enabled for resume. | |
81 | * @int_select: Save for VIC_INT_SELECT. | |
82 | * @int_enable: Save for VIC_INT_ENABLE. | |
83 | * @soft_int: Save for VIC_INT_SOFT. | |
84 | * @protect: Save for VIC_PROTECT. | |
85 | */ | |
86 | struct vic_device { | |
87 | struct sys_device sysdev; | |
88 | ||
89 | void __iomem *base; | |
90 | int irq; | |
91 | u32 resume_sources; | |
92 | u32 resume_irqs; | |
93 | u32 int_select; | |
94 | u32 int_enable; | |
95 | u32 soft_int; | |
96 | u32 protect; | |
97 | }; | |
98 | ||
99 | /* we cannot allocate memory when VICs are initially registered */ | |
100 | static struct vic_device vic_devices[CONFIG_ARM_VIC_NR]; | |
101 | ||
102 | static inline struct vic_device *to_vic(struct sys_device *sys) | |
103 | { | |
104 | return container_of(sys, struct vic_device, sysdev); | |
105 | } | |
106 | ||
107 | static int vic_id; | |
108 | ||
109 | static int vic_class_resume(struct sys_device *dev) | |
110 | { | |
111 | struct vic_device *vic = to_vic(dev); | |
112 | void __iomem *base = vic->base; | |
113 | ||
114 | printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); | |
115 | ||
116 | /* re-initialise static settings */ | |
117 | vic_init2(base); | |
118 | ||
119 | writel(vic->int_select, base + VIC_INT_SELECT); | |
120 | writel(vic->protect, base + VIC_PROTECT); | |
121 | ||
122 | /* set the enabled ints and then clear the non-enabled */ | |
123 | writel(vic->int_enable, base + VIC_INT_ENABLE); | |
124 | writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); | |
125 | ||
126 | /* and the same for the soft-int register */ | |
127 | ||
128 | writel(vic->soft_int, base + VIC_INT_SOFT); | |
129 | writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
134 | static int vic_class_suspend(struct sys_device *dev, pm_message_t state) | |
135 | { | |
136 | struct vic_device *vic = to_vic(dev); | |
137 | void __iomem *base = vic->base; | |
138 | ||
139 | printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base); | |
140 | ||
141 | vic->int_select = readl(base + VIC_INT_SELECT); | |
142 | vic->int_enable = readl(base + VIC_INT_ENABLE); | |
143 | vic->soft_int = readl(base + VIC_INT_SOFT); | |
144 | vic->protect = readl(base + VIC_PROTECT); | |
145 | ||
146 | /* set the interrupts (if any) that are used for | |
147 | * resuming the system */ | |
148 | ||
149 | writel(vic->resume_irqs, base + VIC_INT_ENABLE); | |
150 | writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); | |
151 | ||
152 | return 0; | |
153 | } | |
154 | ||
155 | struct sysdev_class vic_class = { | |
156 | .name = "vic", | |
157 | .suspend = vic_class_suspend, | |
158 | .resume = vic_class_resume, | |
159 | }; | |
160 | ||
161 | /** | |
162 | * vic_pm_register - Register a VIC for later power management control | |
163 | * @base: The base address of the VIC. | |
164 | * @irq: The base IRQ for the VIC. | |
165 | * @resume_sources: bitmask of interrupts allowed for resume sources. | |
166 | * | |
167 | * Register the VIC with the system device tree so that it can be notified | |
168 | * of suspend and resume requests and ensure that the correct actions are | |
169 | * taken to re-instate the settings on resume. | |
170 | */ | |
171 | static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources) | |
172 | { | |
173 | struct vic_device *v; | |
174 | ||
175 | if (vic_id >= ARRAY_SIZE(vic_devices)) | |
176 | printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); | |
177 | else { | |
178 | v = &vic_devices[vic_id]; | |
179 | v->base = base; | |
180 | v->resume_sources = resume_sources; | |
181 | v->irq = irq; | |
182 | vic_id++; | |
183 | } | |
184 | } | |
185 | ||
186 | /** | |
187 | * vic_pm_init - initicall to register VIC pm | |
188 | * | |
189 | * This is called via late_initcall() to register | |
190 | * the resources for the VICs due to the early | |
191 | * nature of the VIC's registration. | |
192 | */ | |
193 | static int __init vic_pm_init(void) | |
194 | { | |
195 | struct vic_device *dev = vic_devices; | |
196 | int err; | |
197 | int id; | |
198 | ||
199 | if (vic_id == 0) | |
200 | return 0; | |
201 | ||
202 | err = sysdev_class_register(&vic_class); | |
203 | if (err) { | |
204 | printk(KERN_ERR "%s: cannot register class\n", __func__); | |
205 | return err; | |
206 | } | |
207 | ||
208 | for (id = 0; id < vic_id; id++, dev++) { | |
209 | dev->sysdev.id = id; | |
210 | dev->sysdev.cls = &vic_class; | |
211 | ||
212 | err = sysdev_register(&dev->sysdev); | |
213 | if (err) { | |
214 | printk(KERN_ERR "%s: failed to register device\n", | |
215 | __func__); | |
216 | return err; | |
217 | } | |
218 | } | |
219 | ||
220 | return 0; | |
221 | } | |
222 | ||
223 | late_initcall(vic_pm_init); | |
224 | ||
225 | static struct vic_device *vic_from_irq(unsigned int irq) | |
226 | { | |
227 | struct vic_device *v = vic_devices; | |
228 | unsigned int base_irq = irq & ~31; | |
229 | int id; | |
230 | ||
231 | for (id = 0; id < vic_id; id++, v++) { | |
232 | if (v->irq == base_irq) | |
233 | return v; | |
234 | } | |
235 | ||
236 | return NULL; | |
237 | } | |
238 | ||
239 | static int vic_set_wake(unsigned int irq, unsigned int on) | |
240 | { | |
241 | struct vic_device *v = vic_from_irq(irq); | |
242 | unsigned int off = irq & 31; | |
3f1a567d | 243 | u32 bit = 1 << off; |
c07f87f2 BD |
244 | |
245 | if (!v) | |
246 | return -EINVAL; | |
247 | ||
3f1a567d BD |
248 | if (!(bit & v->resume_sources)) |
249 | return -EINVAL; | |
250 | ||
c07f87f2 | 251 | if (on) |
3f1a567d | 252 | v->resume_irqs |= bit; |
c07f87f2 | 253 | else |
3f1a567d | 254 | v->resume_irqs &= ~bit; |
c07f87f2 BD |
255 | |
256 | return 0; | |
257 | } | |
258 | ||
259 | #else | |
260 | static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { } | |
261 | ||
262 | #define vic_set_wake NULL | |
263 | #endif /* CONFIG_PM */ | |
264 | ||
38c677cb DB |
265 | static struct irq_chip vic_chip = { |
266 | .name = "VIC", | |
8c81b524 | 267 | .ack = vic_ack_irq, |
fa0fe48f RK |
268 | .mask = vic_mask_irq, |
269 | .unmask = vic_unmask_irq, | |
c07f87f2 | 270 | .set_wake = vic_set_wake, |
fa0fe48f RK |
271 | }; |
272 | ||
87e8824b AR |
273 | /* The PL190 cell from ARM has been modified by ST, so handle both here */ |
274 | static void vik_init_st(void __iomem *base, unsigned int irq_start, | |
275 | u32 vic_sources); | |
276 | ||
824b5b5e RK |
277 | /** |
278 | * vic_init - initialise a vectored interrupt controller | |
279 | * @base: iomem base address | |
280 | * @irq_start: starting interrupt number, must be muliple of 32 | |
281 | * @vic_sources: bitmask of interrupt sources to allow | |
c07f87f2 | 282 | * @resume_sources: bitmask of interrupt sources to allow for resume |
824b5b5e RK |
283 | */ |
284 | void __init vic_init(void __iomem *base, unsigned int irq_start, | |
c07f87f2 | 285 | u32 vic_sources, u32 resume_sources) |
fa0fe48f RK |
286 | { |
287 | unsigned int i; | |
87e8824b | 288 | u32 cellid = 0; |
f17a1f06 | 289 | enum amba_vendor vendor; |
87e8824b AR |
290 | |
291 | /* Identify which VIC cell this one is, by reading the ID */ | |
292 | for (i = 0; i < 4; i++) { | |
293 | u32 addr = ((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); | |
294 | cellid |= (readl(addr) & 0xff) << (8 * i); | |
295 | } | |
296 | vendor = (cellid >> 12) & 0xff; | |
297 | printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n", | |
298 | base, cellid, vendor); | |
299 | ||
300 | switch(vendor) { | |
f17a1f06 | 301 | case AMBA_VENDOR_ST: |
87e8824b AR |
302 | vik_init_st(base, irq_start, vic_sources); |
303 | return; | |
304 | default: | |
305 | printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n"); | |
306 | /* fall through */ | |
f17a1f06 | 307 | case AMBA_VENDOR_ARM: |
87e8824b AR |
308 | break; |
309 | } | |
fa0fe48f | 310 | |
fa0fe48f RK |
311 | /* Disable all interrupts initially. */ |
312 | ||
824b5b5e RK |
313 | writel(0, base + VIC_INT_SELECT); |
314 | writel(0, base + VIC_INT_ENABLE); | |
315 | writel(~0, base + VIC_INT_ENABLE_CLEAR); | |
316 | writel(0, base + VIC_IRQ_STATUS); | |
317 | writel(0, base + VIC_ITCR); | |
318 | writel(~0, base + VIC_INT_SOFT_CLEAR); | |
fa0fe48f RK |
319 | |
320 | /* | |
321 | * Make sure we clear all existing interrupts | |
322 | */ | |
a801cd61 | 323 | writel(0, base + VIC_PL190_VECT_ADDR); |
fa0fe48f RK |
324 | for (i = 0; i < 19; i++) { |
325 | unsigned int value; | |
326 | ||
a801cd61 BD |
327 | value = readl(base + VIC_PL190_VECT_ADDR); |
328 | writel(value, base + VIC_PL190_VECT_ADDR); | |
fa0fe48f RK |
329 | } |
330 | ||
c07f87f2 | 331 | vic_init2(base); |
fa0fe48f RK |
332 | |
333 | for (i = 0; i < 32; i++) { | |
fa0fe48f | 334 | if (vic_sources & (1 << i)) { |
77f4025b LW |
335 | unsigned int irq = irq_start + i; |
336 | ||
337 | set_irq_chip(irq, &vic_chip); | |
338 | set_irq_chip_data(irq, base); | |
10dd5ce2 | 339 | set_irq_handler(irq, handle_level_irq); |
fa0fe48f RK |
340 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
341 | } | |
342 | } | |
c07f87f2 BD |
343 | |
344 | vic_pm_register(base, irq_start, resume_sources); | |
fa0fe48f | 345 | } |
87e8824b AR |
346 | |
347 | /* | |
348 | * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. | |
349 | * The original cell has 32 interrupts, while the modified one has 64, | |
350 | * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case | |
351 | * the probe function is called twice, with base set to offset 000 | |
352 | * and 020 within the page. We call this "second block". | |
353 | */ | |
354 | static void __init vik_init_st(void __iomem *base, unsigned int irq_start, | |
355 | u32 vic_sources) | |
356 | { | |
357 | unsigned int i; | |
358 | int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0; | |
359 | ||
360 | /* Disable all interrupts initially. */ | |
361 | ||
362 | writel(0, base + VIC_INT_SELECT); | |
363 | writel(0, base + VIC_INT_ENABLE); | |
364 | writel(~0, base + VIC_INT_ENABLE_CLEAR); | |
365 | writel(0, base + VIC_IRQ_STATUS); | |
366 | writel(0, base + VIC_ITCR); | |
367 | writel(~0, base + VIC_INT_SOFT_CLEAR); | |
368 | ||
369 | /* | |
370 | * Make sure we clear all existing interrupts. The vector registers | |
371 | * in this cell are after the second block of general registers, | |
372 | * so we can address them using standard offsets, but only from | |
373 | * the second base address, which is 0x20 in the page | |
374 | */ | |
375 | if (vic_2nd_block) { | |
376 | writel(0, base + VIC_PL190_VECT_ADDR); | |
377 | for (i = 0; i < 19; i++) { | |
378 | unsigned int value; | |
379 | ||
380 | value = readl(base + VIC_PL190_VECT_ADDR); | |
381 | writel(value, base + VIC_PL190_VECT_ADDR); | |
382 | } | |
383 | /* ST has 16 vectors as well, but we don't enable them by now */ | |
384 | for (i = 0; i < 16; i++) { | |
385 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); | |
386 | writel(0, reg); | |
387 | } | |
388 | ||
389 | writel(32, base + VIC_PL190_DEF_VECT_ADDR); | |
390 | } | |
391 | ||
392 | for (i = 0; i < 32; i++) { | |
393 | if (vic_sources & (1 << i)) { | |
394 | unsigned int irq = irq_start + i; | |
395 | ||
396 | set_irq_chip(irq, &vic_chip); | |
397 | set_irq_chip_data(irq, base); | |
398 | set_irq_handler(irq, handle_level_irq); | |
399 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
400 | } | |
401 | } | |
402 | } |