[deliverable/linux.git] / arch / arm / include / asm / barrier.h

#ifndef __ASM_BARRIER_H
#define __ASM_BARRIER_H

#ifndef __ASSEMBLY__
#include <asm/outercache.h>

#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");

#if __LINUX_ARM_ARCH__ >= 7 ||		\
	(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
#define sev()	__asm__ __volatile__ ("sev" : : : "memory")
#define wfe()	__asm__ __volatile__ ("wfe" : : : "memory")
#define wfi()	__asm__ __volatile__ ("wfi" : : : "memory")
#endif

#if __LINUX_ARM_ARCH__ >= 7
#define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory")
#define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory")
#define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory")
#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
				    : : "r" (0) : "memory")
#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
				    : : "r" (0) : "memory")
#define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
				    : : "r" (0) : "memory")
#elif defined(CONFIG_CPU_FA526)
#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
				    : : "r" (0) : "memory")
#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
				    : : "r" (0) : "memory")
#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
#else
#define isb(x) __asm__ __volatile__ ("" : : : "memory")
#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
				    : : "r" (0) : "memory")
#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
#endif

#ifdef CONFIG_ARCH_HAS_BARRIERS
#include <mach/barriers.h>
#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
#define mb()		do { dsb(); outer_sync(); } while (0)
#define rmb()		dsb()
#define wmb()		do { dsb(st); outer_sync(); } while (0)
#define dma_rmb()	dmb(osh)
#define dma_wmb()	dmb(oshst)
#else
#define mb()		barrier()
#define rmb()		barrier()
#define wmb()		barrier()
#define dma_rmb()	barrier()
#define dma_wmb()	barrier()
#endif

#ifndef CONFIG_SMP
#define smp_mb()	barrier()
#define smp_rmb()	barrier()
#define smp_wmb()	barrier()
#else
#define smp_mb()	dmb(ish)
#define smp_rmb()	smp_mb()
#define smp_wmb()	dmb(ishst)
#endif

#define smp_store_release(p, v)						\
do {									\
	compiletime_assert_atomic_type(*p);				\
	smp_mb();							\
	ACCESS_ONCE(*p) = (v);						\
} while (0)

#define smp_load_acquire(p)						\
({									\
	typeof(*p) ___p1 = ACCESS_ONCE(*p);				\
	compiletime_assert_atomic_type(*p);				\
	smp_mb();							\
	___p1;								\
})

#define read_barrier_depends()		do { } while(0)
#define smp_read_barrier_depends()	do { } while(0)

#define smp_store_mb(var, value)	do { WRITE_ONCE(var, value); smp_mb(); } while (0)

#define smp_mb__before_atomic()	smp_mb()
#define smp_mb__after_atomic()	smp_mb()

#endif /* !__ASSEMBLY__ */
#endif /* __ASM_BARRIER_H */
Commit	Line	Data
9f97da78 DH	1	#ifndef __ASM_BARRIER_H
	2	#define __ASM_BARRIER_H
	3
	4	#ifndef __ASSEMBLY__
b7782d3f	5	#include <asm/outercache.h>
9f97da78 DH	6
	7	#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
	8
	9	#if __LINUX_ARM_ARCH__ >= 7 \|\| \
	10	(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
	11	#define sev() __asm__ __volatile__ ("sev" : : : "memory")
	12	#define wfe() __asm__ __volatile__ ("wfe" : : : "memory")
	13	#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
	14	#endif
	15
	16	#if __LINUX_ARM_ARCH__ >= 7
3ea12806 WD	17	#define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory")
	18	#define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory")
	19	#define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory")
9f97da78	20	#elif defined(CONFIG_CPU_XSC3) \|\| __LINUX_ARM_ARCH__ == 6
3ea12806	21	#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
9f97da78	22	: : "r" (0) : "memory")
3ea12806	23	#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
9f97da78	24	: : "r" (0) : "memory")
3ea12806	25	#define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
9f97da78 DH	26	: : "r" (0) : "memory")
9f97da78 DH	27	#elif defined(CONFIG_CPU_FA526)
3ea12806	28	#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
9f97da78	29	: : "r" (0) : "memory")
3ea12806	30	#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
9f97da78	31	: : "r" (0) : "memory")
3ea12806	32	#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
9f97da78	33	#else
3ea12806 WD	34	#define isb(x) __asm__ __volatile__ ("" : : : "memory")
3ea12806 WD	35	#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
9f97da78	36	: : "r" (0) : "memory")
3ea12806	37	#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
9f97da78 DH	38	#endif
	39
	40	#ifdef CONFIG_ARCH_HAS_BARRIERS
	41	#include <mach/barriers.h>
	42	#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) \|\| defined(CONFIG_SMP)
9f97da78 DH	43	#define mb() do { dsb(); outer_sync(); } while (0)
9f97da78 DH	44	#define rmb() dsb()
3ea12806	45	#define wmb() do { dsb(st); outer_sync(); } while (0)
1077fa36 AD	46	#define dma_rmb() dmb(osh)
1077fa36 AD	47	#define dma_wmb() dmb(oshst)
9f97da78	48	#else
48aa820f RH	49	#define mb() barrier()
	50	#define rmb() barrier()
	51	#define wmb() barrier()
1077fa36 AD	52	#define dma_rmb() barrier()
1077fa36 AD	53	#define dma_wmb() barrier()
9f97da78 DH	54	#endif
	55
	56	#ifndef CONFIG_SMP
	57	#define smp_mb() barrier()
	58	#define smp_rmb() barrier()
	59	#define smp_wmb() barrier()
	60	#else
3ea12806 WD	61	#define smp_mb() dmb(ish)
	62	#define smp_rmb() smp_mb()
	63	#define smp_wmb() dmb(ishst)
9f97da78 DH	64	#endif
9f97da78 DH	65
47933ad4 PZ	66	#define smp_store_release(p, v) \
	67	do { \
	68	compiletime_assert_atomic_type(*p); \
	69	smp_mb(); \
	70	ACCESS_ONCE(*p) = (v); \
	71	} while (0)
	72
	73	#define smp_load_acquire(p) \
	74	({ \
	75	typeof(p) ___p1 = ACCESS_ONCE(p); \
	76	compiletime_assert_atomic_type(*p); \
	77	smp_mb(); \
	78	___p1; \
	79	})
	80
9f97da78 DH	81	#define read_barrier_depends() do { } while(0)
	82	#define smp_read_barrier_depends() do { } while(0)
	83
b92b8b35	84	#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0)
9f97da78	85
030d0178 PZ	86	#define smp_mb__before_atomic() smp_mb()
	87	#define smp_mb__after_atomic() smp_mb()
	88
9f97da78 DH	89	#endif /* !__ASSEMBLY__ */
9f97da78 DH	90	#endif /* __ASM_BARRIER_H */