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753790e7 RK |
1 | /* |
2 | * arch/arm/include/asm/glue-cache.h | |
3 | * | |
4 | * Copyright (C) 1999-2002 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #ifndef ASM_GLUE_CACHE_H | |
11 | #define ASM_GLUE_CACHE_H | |
12 | ||
13 | #include <asm/glue.h> | |
14 | ||
15 | /* | |
16 | * Cache Model | |
17 | * =========== | |
18 | */ | |
19 | #undef _CACHE | |
20 | #undef MULTI_CACHE | |
21 | ||
753790e7 RK |
22 | #if defined(CONFIG_CPU_CACHE_V4) |
23 | # ifdef _CACHE | |
24 | # define MULTI_CACHE 1 | |
25 | # else | |
26 | # define _CACHE v4 | |
27 | # endif | |
28 | #endif | |
29 | ||
30 | #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \ | |
31 | defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \ | |
32 | defined(CONFIG_CPU_ARM1026) | |
33 | # define MULTI_CACHE 1 | |
34 | #endif | |
35 | ||
36 | #if defined(CONFIG_CPU_FA526) | |
37 | # ifdef _CACHE | |
38 | # define MULTI_CACHE 1 | |
39 | # else | |
40 | # define _CACHE fa | |
41 | # endif | |
42 | #endif | |
43 | ||
44 | #if defined(CONFIG_CPU_ARM926T) | |
45 | # ifdef _CACHE | |
46 | # define MULTI_CACHE 1 | |
47 | # else | |
48 | # define _CACHE arm926 | |
49 | # endif | |
50 | #endif | |
51 | ||
52 | #if defined(CONFIG_CPU_ARM940T) | |
53 | # ifdef _CACHE | |
54 | # define MULTI_CACHE 1 | |
55 | # else | |
56 | # define _CACHE arm940 | |
57 | # endif | |
58 | #endif | |
59 | ||
60 | #if defined(CONFIG_CPU_ARM946E) | |
61 | # ifdef _CACHE | |
62 | # define MULTI_CACHE 1 | |
63 | # else | |
64 | # define _CACHE arm946 | |
65 | # endif | |
66 | #endif | |
67 | ||
68 | #if defined(CONFIG_CPU_CACHE_V4WB) | |
69 | # ifdef _CACHE | |
70 | # define MULTI_CACHE 1 | |
71 | # else | |
72 | # define _CACHE v4wb | |
73 | # endif | |
74 | #endif | |
75 | ||
76 | #if defined(CONFIG_CPU_XSCALE) | |
77 | # ifdef _CACHE | |
78 | # define MULTI_CACHE 1 | |
79 | # else | |
80 | # define _CACHE xscale | |
81 | # endif | |
82 | #endif | |
83 | ||
84 | #if defined(CONFIG_CPU_XSC3) | |
85 | # ifdef _CACHE | |
86 | # define MULTI_CACHE 1 | |
87 | # else | |
88 | # define _CACHE xsc3 | |
89 | # endif | |
90 | #endif | |
91 | ||
92 | #if defined(CONFIG_CPU_MOHAWK) | |
93 | # ifdef _CACHE | |
94 | # define MULTI_CACHE 1 | |
95 | # else | |
96 | # define _CACHE mohawk | |
97 | # endif | |
98 | #endif | |
99 | ||
100 | #if defined(CONFIG_CPU_FEROCEON) | |
101 | # define MULTI_CACHE 1 | |
102 | #endif | |
103 | ||
bd1274dc | 104 | #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) |
a67e1ce1 | 105 | # ifdef _CACHE |
753790e7 | 106 | # define MULTI_CACHE 1 |
a67e1ce1 RK |
107 | # else |
108 | # define _CACHE v6 | |
109 | # endif | |
753790e7 RK |
110 | #endif |
111 | ||
112 | #if defined(CONFIG_CPU_V7) | |
a67e1ce1 | 113 | # ifdef _CACHE |
753790e7 | 114 | # define MULTI_CACHE 1 |
a67e1ce1 RK |
115 | # else |
116 | # define _CACHE v7 | |
117 | # endif | |
753790e7 RK |
118 | #endif |
119 | ||
55bdd694 CM |
120 | #if defined(CONFIG_CPU_V7M) |
121 | # ifdef _CACHE | |
122 | # define MULTI_CACHE 1 | |
123 | # else | |
124 | # define _CACHE nop | |
125 | # endif | |
126 | #endif | |
127 | ||
753790e7 | 128 | #if !defined(_CACHE) && !defined(MULTI_CACHE) |
25985edc | 129 | #error Unknown cache maintenance model |
753790e7 RK |
130 | #endif |
131 | ||
55bdd694 | 132 | #ifndef __ASSEMBLER__ |
76ae0382 BW |
133 | static inline void nop_flush_icache_all(void) { } |
134 | static inline void nop_flush_kern_cache_all(void) { } | |
135 | static inline void nop_flush_kern_cache_louis(void) { } | |
136 | static inline void nop_flush_user_cache_all(void) { } | |
137 | static inline void nop_flush_user_cache_range(unsigned long a, | |
55bdd694 CM |
138 | unsigned long b, unsigned int c) { } |
139 | ||
76ae0382 BW |
140 | static inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { } |
141 | static inline int nop_coherent_user_range(unsigned long a, | |
55bdd694 | 142 | unsigned long b) { return 0; } |
76ae0382 | 143 | static inline void nop_flush_kern_dcache_area(void *a, size_t s) { } |
55bdd694 | 144 | |
76ae0382 | 145 | static inline void nop_dma_flush_range(const void *a, const void *b) { } |
55bdd694 | 146 | |
76ae0382 BW |
147 | static inline void nop_dma_map_area(const void *s, size_t l, int f) { } |
148 | static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { } | |
55bdd694 CM |
149 | #endif |
150 | ||
753790e7 RK |
151 | #ifndef MULTI_CACHE |
152 | #define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all) | |
153 | #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) | |
031bd879 | 154 | #define __cpuc_flush_kern_louis __glue(_CACHE,_flush_kern_cache_louis) |
753790e7 RK |
155 | #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all) |
156 | #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) | |
157 | #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) | |
158 | #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) | |
159 | #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) | |
160 | ||
161 | #define dmac_map_area __glue(_CACHE,_dma_map_area) | |
162 | #define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) | |
163 | #define dmac_flush_range __glue(_CACHE,_dma_flush_range) | |
164 | #endif | |
165 | ||
166 | #endif |