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1da177e4 | 1 | /* |
4baa9922 | 2 | * arch/arm/include/asm/io.h |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1996-2000 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Modifications: | |
11 | * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both | |
12 | * constant addresses and variable addresses. | |
13 | * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture | |
14 | * specific IO header files. | |
15 | * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. | |
16 | * 04-Apr-1999 PJB Added check_signature. | |
17 | * 12-Dec-1999 RMK More cleanups | |
18 | * 18-Jun-2000 RMK Removed virt_to_* and friends definitions | |
19 | * 05-Oct-2004 BJD Moved memory string functions to use void __iomem | |
20 | */ | |
21 | #ifndef __ASM_ARM_IO_H | |
22 | #define __ASM_ARM_IO_H | |
23 | ||
24 | #ifdef __KERNEL__ | |
25 | ||
7ddfe625 | 26 | #include <linux/string.h> |
1da177e4 | 27 | #include <linux/types.h> |
3d1975b5 | 28 | #include <linux/blk_types.h> |
1da177e4 LT |
29 | #include <asm/byteorder.h> |
30 | #include <asm/memory.h> | |
e5bfb72c | 31 | #include <asm-generic/pci_iomap.h> |
3d1975b5 | 32 | #include <xen/xen.h> |
1da177e4 LT |
33 | |
34 | /* | |
35 | * ISA I/O bus memory addresses are 1:1 with the physical address. | |
36 | */ | |
37 | #define isa_virt_to_bus virt_to_phys | |
38 | #define isa_page_to_bus page_to_phys | |
39 | #define isa_bus_to_virt phys_to_virt | |
40 | ||
c5ca95b5 EG |
41 | /* |
42 | * Atomic MMIO-wide IO modify | |
43 | */ | |
44 | extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set); | |
45 | extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set); | |
46 | ||
1da177e4 LT |
47 | /* |
48 | * Generic IO read/write. These perform native-endian accesses. Note | |
49 | * that some architectures will want to re-define __raw_{read,write}w. | |
50 | */ | |
84c4d3a6 TR |
51 | void __raw_writesb(volatile void __iomem *addr, const void *data, int bytelen); |
52 | void __raw_writesw(volatile void __iomem *addr, const void *data, int wordlen); | |
53 | void __raw_writesl(volatile void __iomem *addr, const void *data, int longlen); | |
1da177e4 | 54 | |
84c4d3a6 TR |
55 | void __raw_readsb(const volatile void __iomem *addr, void *data, int bytelen); |
56 | void __raw_readsw(const volatile void __iomem *addr, void *data, int wordlen); | |
57 | void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen); | |
1da177e4 | 58 | |
195bbcac WD |
59 | #if __LINUX_ARM_ARCH__ < 6 |
60 | /* | |
61 | * Half-word accesses are problematic with RiscPC due to limitations of | |
62 | * the bus. Rather than special-case the machine, just let the compiler | |
63 | * generate the access for CPUs prior to ARMv6. | |
64 | */ | |
65 | #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) | |
66 | #define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))) | |
67 | #else | |
68 | /* | |
69 | * When running under a hypervisor, we want to avoid I/O accesses with | |
70 | * writeback addressing modes as these incur a significant performance | |
71 | * overhead (the address generation must be emulated in software). | |
72 | */ | |
84c4d3a6 | 73 | #define __raw_writew __raw_writew |
195bbcac WD |
74 | static inline void __raw_writew(u16 val, volatile void __iomem *addr) |
75 | { | |
76 | asm volatile("strh %1, %0" | |
5bb5d66d | 77 | : : "Q" (*(volatile u16 __force *)addr), "r" (val)); |
195bbcac WD |
78 | } |
79 | ||
84c4d3a6 | 80 | #define __raw_readw __raw_readw |
195bbcac WD |
81 | static inline u16 __raw_readw(const volatile void __iomem *addr) |
82 | { | |
83 | u16 val; | |
5bb5d66d PH |
84 | asm volatile("ldrh %0, %1" |
85 | : "=r" (val) | |
86 | : "Q" (*(volatile u16 __force *)addr)); | |
195bbcac WD |
87 | return val; |
88 | } | |
89 | #endif | |
90 | ||
84c4d3a6 | 91 | #define __raw_writeb __raw_writeb |
195bbcac WD |
92 | static inline void __raw_writeb(u8 val, volatile void __iomem *addr) |
93 | { | |
94 | asm volatile("strb %1, %0" | |
5bb5d66d | 95 | : : "Qo" (*(volatile u8 __force *)addr), "r" (val)); |
195bbcac WD |
96 | } |
97 | ||
84c4d3a6 | 98 | #define __raw_writel __raw_writel |
195bbcac WD |
99 | static inline void __raw_writel(u32 val, volatile void __iomem *addr) |
100 | { | |
101 | asm volatile("str %1, %0" | |
5bb5d66d | 102 | : : "Qo" (*(volatile u32 __force *)addr), "r" (val)); |
195bbcac WD |
103 | } |
104 | ||
84c4d3a6 | 105 | #define __raw_readb __raw_readb |
195bbcac WD |
106 | static inline u8 __raw_readb(const volatile void __iomem *addr) |
107 | { | |
108 | u8 val; | |
5bb5d66d PH |
109 | asm volatile("ldrb %0, %1" |
110 | : "=r" (val) | |
111 | : "Qo" (*(volatile u8 __force *)addr)); | |
195bbcac WD |
112 | return val; |
113 | } | |
1da177e4 | 114 | |
84c4d3a6 | 115 | #define __raw_readl __raw_readl |
195bbcac WD |
116 | static inline u32 __raw_readl(const volatile void __iomem *addr) |
117 | { | |
118 | u32 val; | |
5bb5d66d PH |
119 | asm volatile("ldr %0, %1" |
120 | : "=r" (val) | |
121 | : "Qo" (*(volatile u32 __force *)addr)); | |
195bbcac WD |
122 | return val; |
123 | } | |
1da177e4 | 124 | |
67a1901f RK |
125 | /* |
126 | * Architecture ioremap implementation. | |
127 | */ | |
3603ab2b RK |
128 | #define MT_DEVICE 0 |
129 | #define MT_DEVICE_NONSHARED 1 | |
130 | #define MT_DEVICE_CACHED 2 | |
db5b7169 | 131 | #define MT_DEVICE_WC 3 |
3603ab2b | 132 | /* |
db5b7169 | 133 | * types 4 onwards can be found in asm/mach/map.h and are undefined |
3603ab2b RK |
134 | * for ioremap |
135 | */ | |
136 | ||
137 | /* | |
138 | * __arm_ioremap takes CPU physical address. | |
139 | * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page | |
31aa8fd6 RK |
140 | * The _caller variety takes a __builtin_return_address(0) value for |
141 | * /proc/vmalloc to use - and should only be used in non-inline functions. | |
3603ab2b | 142 | */ |
9b97173e | 143 | extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int, |
31aa8fd6 | 144 | void *); |
31aa8fd6 | 145 | extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int); |
9b97173e | 146 | extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached); |
1622605c | 147 | extern void __iounmap(volatile void __iomem *addr); |
4fe7ef3a | 148 | |
9b97173e | 149 | extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, |
4fe7ef3a RH |
150 | unsigned int, void *); |
151 | extern void (*arch_iounmap)(volatile void __iomem *); | |
67a1901f | 152 | |
1da177e4 LT |
153 | /* |
154 | * Bad read/write accesses... | |
155 | */ | |
156 | extern void __readwrite_bug(const char *fn); | |
157 | ||
0560cf5a RK |
158 | /* |
159 | * A typesafe __io() helper | |
160 | */ | |
161 | static inline void __iomem *__typesafe_io(unsigned long addr) | |
162 | { | |
163 | return (void __iomem *)addr; | |
164 | } | |
165 | ||
6f6f6a70 RH |
166 | #define IOMEM(x) ((void __force __iomem *)(x)) |
167 | ||
c1928022 RK |
168 | /* IO barriers */ |
169 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE | |
9f97da78 | 170 | #include <asm/barrier.h> |
c1928022 RK |
171 | #define __iormb() rmb() |
172 | #define __iowmb() wmb() | |
173 | #else | |
174 | #define __iormb() do { } while (0) | |
175 | #define __iowmb() do { } while (0) | |
176 | #endif | |
177 | ||
c2794437 RH |
178 | /* PCI fixed i/o mapping */ |
179 | #define PCI_IO_VIRT_BASE 0xfee00000 | |
dad13e3c | 180 | #define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE) |
c2794437 | 181 | |
1c8c3cf0 TP |
182 | #if defined(CONFIG_PCI) |
183 | void pci_ioremap_set_mem_type(int mem_type); | |
184 | #else | |
185 | static inline void pci_ioremap_set_mem_type(int mem_type) {} | |
186 | #endif | |
187 | ||
c2794437 RH |
188 | extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); |
189 | ||
1da177e4 LT |
190 | /* |
191 | * Now, pick up the machine-defined IO definitions | |
192 | */ | |
c334bc15 | 193 | #ifdef CONFIG_NEED_MACH_IO_H |
a09e64fb | 194 | #include <mach/io.h> |
c2794437 RH |
195 | #elif defined(CONFIG_PCI) |
196 | #define IO_SPACE_LIMIT ((resource_size_t)0xfffff) | |
197 | #define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT)) | |
c334bc15 | 198 | #else |
1ac02d79 | 199 | #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT) |
c334bc15 | 200 | #endif |
1da177e4 | 201 | |
04e1c838 RK |
202 | /* |
203 | * This is the limit of PC card/PCI/ISA IO space, which is by default | |
204 | * 64K if we have PC card, PCI or ISA support. Otherwise, default to | |
205 | * zero to prevent ISA/PCI drivers claiming IO space (and potentially | |
206 | * oopsing.) | |
207 | * | |
208 | * Only set this larger if you really need inb() et.al. to operate over | |
209 | * a larger address space. Note that SOC_COMMON ioremaps each sockets | |
210 | * IO space area, and so inb() et.al. must be defined to operate as per | |
211 | * readb() et.al. on such platforms. | |
212 | */ | |
213 | #ifndef IO_SPACE_LIMIT | |
214 | #if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE) | |
215 | #define IO_SPACE_LIMIT ((resource_size_t)0xffffffff) | |
216 | #elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD) | |
217 | #define IO_SPACE_LIMIT ((resource_size_t)0xffff) | |
218 | #else | |
219 | #define IO_SPACE_LIMIT ((resource_size_t)0) | |
220 | #endif | |
221 | #endif | |
222 | ||
1da177e4 LT |
223 | /* |
224 | * IO port access primitives | |
225 | * ------------------------- | |
226 | * | |
227 | * The ARM doesn't have special IO access instructions; all IO is memory | |
228 | * mapped. Note that these are defined to perform little endian accesses | |
229 | * only. Their primary purpose is to access PCI and ISA peripherals. | |
230 | * | |
231 | * Note that for a big endian machine, this implies that the following | |
c79ebfa8 | 232 | * big endian mode connectivity is in place, as described by numerous |
1da177e4 LT |
233 | * ARM documents: |
234 | * | |
235 | * PCI: D0-D7 D8-D15 D16-D23 D24-D31 | |
236 | * ARM: D24-D31 D16-D23 D8-D15 D0-D7 | |
237 | * | |
238 | * The machine specific io.h include defines __io to translate an "IO" | |
239 | * address to a memory address. | |
240 | * | |
241 | * Note that we prevent GCC re-ordering or caching values in expressions | |
242 | * by introducing sequence points into the in*() definitions. Note that | |
243 | * __raw_* do not guarantee this behaviour. | |
244 | * | |
245 | * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. | |
246 | */ | |
247 | #ifdef __io | |
c1928022 RK |
248 | #define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); }) |
249 | #define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \ | |
250 | cpu_to_le16(v),__io(p)); }) | |
251 | #define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \ | |
252 | cpu_to_le32(v),__io(p)); }) | |
1da177e4 | 253 | |
c1928022 | 254 | #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; }) |
05f9869b | 255 | #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \ |
c1928022 | 256 | __raw_readw(__io(p))); __iormb(); __v; }) |
05f9869b | 257 | #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \ |
c1928022 | 258 | __raw_readl(__io(p))); __iormb(); __v; }) |
1da177e4 LT |
259 | |
260 | #define outsb(p,d,l) __raw_writesb(__io(p),d,l) | |
261 | #define outsw(p,d,l) __raw_writesw(__io(p),d,l) | |
262 | #define outsl(p,d,l) __raw_writesl(__io(p),d,l) | |
263 | ||
264 | #define insb(p,d,l) __raw_readsb(__io(p),d,l) | |
265 | #define insw(p,d,l) __raw_readsw(__io(p),d,l) | |
266 | #define insl(p,d,l) __raw_readsl(__io(p),d,l) | |
267 | #endif | |
268 | ||
1da177e4 LT |
269 | /* |
270 | * String version of IO memory access ops: | |
271 | */ | |
d2f60748 RK |
272 | extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t); |
273 | extern void _memcpy_toio(volatile void __iomem *, const void *, size_t); | |
274 | extern void _memset_io(volatile void __iomem *, int, size_t); | |
1da177e4 LT |
275 | |
276 | #define mmiowb() | |
277 | ||
278 | /* | |
279 | * Memory access primitives | |
280 | * ------------------------ | |
281 | * | |
282 | * These perform PCI memory accesses via an ioremap region. They don't | |
283 | * take an address as such, but a cookie. | |
284 | * | |
285 | * Again, this are defined to perform little endian accesses. See the | |
286 | * IO port primitives for more information. | |
287 | */ | |
5621caac RH |
288 | #ifndef readl |
289 | #define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) | |
b0c1264f | 290 | #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ |
5621caac | 291 | __raw_readw(c)); __r; }) |
b0c1264f | 292 | #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ |
5621caac | 293 | __raw_readl(c)); __r; }) |
e936771a | 294 | |
af06bb9f RK |
295 | #define writeb_relaxed(v,c) __raw_writeb(v,c) |
296 | #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c) | |
297 | #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) | |
e936771a | 298 | |
b92b3612 RK |
299 | #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) |
300 | #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) | |
301 | #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) | |
302 | ||
303 | #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); }) | |
304 | #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) | |
305 | #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) | |
306 | ||
5621caac RH |
307 | #define readsb(p,d,l) __raw_readsb(p,d,l) |
308 | #define readsw(p,d,l) __raw_readsw(p,d,l) | |
309 | #define readsl(p,d,l) __raw_readsl(p,d,l) | |
1da177e4 | 310 | |
5621caac RH |
311 | #define writesb(p,d,l) __raw_writesb(p,d,l) |
312 | #define writesw(p,d,l) __raw_writesw(p,d,l) | |
313 | #define writesl(p,d,l) __raw_writesl(p,d,l) | |
1da177e4 | 314 | |
7ddfe625 RK |
315 | #ifndef __ARMBE__ |
316 | static inline void memset_io(volatile void __iomem *dst, unsigned c, | |
317 | size_t count) | |
318 | { | |
1bd46782 RK |
319 | extern void mmioset(void *, unsigned int, size_t); |
320 | mmioset((void __force *)dst, c, count); | |
7ddfe625 RK |
321 | } |
322 | #define memset_io(dst,c,count) memset_io(dst,c,count) | |
323 | ||
324 | static inline void memcpy_fromio(void *to, const volatile void __iomem *from, | |
325 | size_t count) | |
326 | { | |
1bd46782 RK |
327 | extern void mmiocpy(void *, const void *, size_t); |
328 | mmiocpy(to, (const void __force *)from, count); | |
7ddfe625 RK |
329 | } |
330 | #define memcpy_fromio(to,from,count) memcpy_fromio(to,from,count) | |
331 | ||
332 | static inline void memcpy_toio(volatile void __iomem *to, const void *from, | |
333 | size_t count) | |
334 | { | |
1bd46782 RK |
335 | extern void mmiocpy(void *, const void *, size_t); |
336 | mmiocpy((void __force *)to, from, count); | |
7ddfe625 RK |
337 | } |
338 | #define memcpy_toio(to,from,count) memcpy_toio(to,from,count) | |
339 | ||
340 | #else | |
5621caac RH |
341 | #define memset_io(c,v,l) _memset_io(c,(v),(l)) |
342 | #define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l)) | |
343 | #define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l)) | |
7ddfe625 | 344 | #endif |
1da177e4 | 345 | |
5621caac | 346 | #endif /* readl */ |
1da177e4 | 347 | |
1da177e4 | 348 | /* |
ac5e2f17 | 349 | * ioremap() and friends. |
1da177e4 | 350 | * |
ac5e2f17 RK |
351 | * ioremap() takes a resource address, and size. Due to the ARM memory |
352 | * types, it is important to use the correct ioremap() function as each | |
353 | * mapping has specific properties. | |
9d4ae727 | 354 | * |
ac5e2f17 RK |
355 | * Function Memory type Cacheability Cache hint |
356 | * ioremap() Device n/a n/a | |
357 | * ioremap_nocache() Device n/a n/a | |
358 | * ioremap_cache() Normal Writeback Read allocate | |
359 | * ioremap_wc() Normal Non-cacheable n/a | |
360 | * ioremap_wt() Normal Non-cacheable n/a | |
361 | * | |
362 | * All device mappings have the following properties: | |
363 | * - no access speculation | |
364 | * - no repetition (eg, on return from an exception) | |
365 | * - number, order and size of accesses are maintained | |
366 | * - unaligned accesses are "unpredictable" | |
367 | * - writes may be delayed before they hit the endpoint device | |
368 | * | |
369 | * ioremap_nocache() is the same as ioremap() as there are too many device | |
370 | * drivers using this for device registers, and documentation which tells | |
371 | * people to use it for such for this to be any different. This is not a | |
372 | * safe fallback for memory-like mappings, or memory regions where the | |
373 | * compiler may generate unaligned accesses - eg, via inlining its own | |
374 | * memcpy. | |
375 | * | |
376 | * All normal memory mappings have the following properties: | |
377 | * - reads can be repeated with no side effects | |
378 | * - repeated reads return the last value written | |
379 | * - reads can fetch additional locations without side effects | |
380 | * - writes can be repeated (in certain cases) with no side effects | |
381 | * - writes can be merged before accessing the target | |
382 | * - unaligned accesses can be supported | |
383 | * - ordering is not guaranteed without explicit dependencies or barrier | |
384 | * instructions | |
385 | * - writes may be delayed before they hit the endpoint memory | |
386 | * | |
387 | * The cache hint is only a performance hint: CPUs may alias these hints. | |
388 | * Eg, a CPU not implementing read allocate but implementing write allocate | |
389 | * will provide a write allocate mapping instead. | |
1da177e4 | 390 | */ |
20a1080d RK |
391 | void __iomem *ioremap(resource_size_t res_cookie, size_t size); |
392 | #define ioremap ioremap | |
393 | #define ioremap_nocache ioremap | |
394 | ||
395 | void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size); | |
396 | #define ioremap_cache ioremap_cache | |
397 | ||
398 | void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size); | |
399 | #define ioremap_wc ioremap_wc | |
400 | #define ioremap_wt ioremap_wc | |
401 | ||
402 | void iounmap(volatile void __iomem *iomem_cookie); | |
403 | #define iounmap iounmap | |
1da177e4 | 404 | |
09f0551d | 405 | /* |
84c4d3a6 | 406 | * io{read,write}{16,32}be() macros |
09f0551d | 407 | */ |
84c4d3a6 TR |
408 | #define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; }) |
409 | #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; }) | |
09f0551d | 410 | |
84c4d3a6 TR |
411 | #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); }) |
412 | #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); }) | |
09f0551d | 413 | |
84c4d3a6 TR |
414 | #ifndef ioport_map |
415 | #define ioport_map ioport_map | |
09f0551d | 416 | extern void __iomem *ioport_map(unsigned long port, unsigned int nr); |
84c4d3a6 TR |
417 | #endif |
418 | #ifndef ioport_unmap | |
419 | #define ioport_unmap ioport_unmap | |
09f0551d | 420 | extern void ioport_unmap(void __iomem *addr); |
7533fca8 | 421 | #endif |
09f0551d RK |
422 | |
423 | struct pci_dev; | |
424 | ||
84c4d3a6 | 425 | #define pci_iounmap pci_iounmap |
09f0551d RK |
426 | extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); |
427 | ||
84c4d3a6 TR |
428 | /* |
429 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | |
430 | * access | |
431 | */ | |
432 | #define xlate_dev_mem_ptr(p) __va(p) | |
433 | ||
434 | /* | |
435 | * Convert a virtual cached pointer to an uncached pointer | |
436 | */ | |
437 | #define xlate_dev_kmem_ptr(p) p | |
438 | ||
439 | #include <asm-generic/io.h> | |
440 | ||
1da177e4 LT |
441 | /* |
442 | * can the hardware map this into one segment or not, given no other | |
443 | * constraints. | |
444 | */ | |
445 | #define BIOVEC_MERGEABLE(vec1, vec2) \ | |
446 | ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) | |
447 | ||
ffc555be | 448 | struct bio_vec; |
3d1975b5 SS |
449 | extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, |
450 | const struct bio_vec *vec2); | |
451 | #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ | |
452 | (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ | |
453 | (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2))) | |
454 | ||
95ba71f7 | 455 | #ifdef CONFIG_MMU |
51635ad2 | 456 | #define ARCH_HAS_VALID_PHYS_ADDR_RANGE |
7e6735c3 | 457 | extern int valid_phys_addr_range(phys_addr_t addr, size_t size); |
51635ad2 | 458 | extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); |
087aaffc | 459 | extern int devmem_is_allowed(unsigned long pfn); |
95ba71f7 | 460 | #endif |
51635ad2 | 461 | |
1645f20b RK |
462 | /* |
463 | * Register ISA memory and port locations for glibc iopl/inb/outb | |
464 | * emulation. | |
465 | */ | |
466 | extern void register_isa_ports(unsigned int mmio, unsigned int io, | |
467 | unsigned int io_shift); | |
468 | ||
1da177e4 LT |
469 | #endif /* __KERNEL__ */ |
470 | #endif /* __ASM_ARM_IO_H */ |