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1da177e4 | 1 | /* |
4baa9922 | 2 | * arch/arm/include/asm/io.h |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1996-2000 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Modifications: | |
11 | * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both | |
12 | * constant addresses and variable addresses. | |
13 | * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture | |
14 | * specific IO header files. | |
15 | * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. | |
16 | * 04-Apr-1999 PJB Added check_signature. | |
17 | * 12-Dec-1999 RMK More cleanups | |
18 | * 18-Jun-2000 RMK Removed virt_to_* and friends definitions | |
19 | * 05-Oct-2004 BJD Moved memory string functions to use void __iomem | |
20 | */ | |
21 | #ifndef __ASM_ARM_IO_H | |
22 | #define __ASM_ARM_IO_H | |
23 | ||
24 | #ifdef __KERNEL__ | |
25 | ||
26 | #include <linux/types.h> | |
3d1975b5 | 27 | #include <linux/blk_types.h> |
1da177e4 LT |
28 | #include <asm/byteorder.h> |
29 | #include <asm/memory.h> | |
e5bfb72c | 30 | #include <asm-generic/pci_iomap.h> |
3d1975b5 | 31 | #include <xen/xen.h> |
1da177e4 LT |
32 | |
33 | /* | |
34 | * ISA I/O bus memory addresses are 1:1 with the physical address. | |
35 | */ | |
36 | #define isa_virt_to_bus virt_to_phys | |
37 | #define isa_page_to_bus page_to_phys | |
38 | #define isa_bus_to_virt phys_to_virt | |
39 | ||
c5ca95b5 EG |
40 | /* |
41 | * Atomic MMIO-wide IO modify | |
42 | */ | |
43 | extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set); | |
44 | extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set); | |
45 | ||
1da177e4 LT |
46 | /* |
47 | * Generic IO read/write. These perform native-endian accesses. Note | |
48 | * that some architectures will want to re-define __raw_{read,write}w. | |
49 | */ | |
84c4d3a6 TR |
50 | void __raw_writesb(volatile void __iomem *addr, const void *data, int bytelen); |
51 | void __raw_writesw(volatile void __iomem *addr, const void *data, int wordlen); | |
52 | void __raw_writesl(volatile void __iomem *addr, const void *data, int longlen); | |
1da177e4 | 53 | |
84c4d3a6 TR |
54 | void __raw_readsb(const volatile void __iomem *addr, void *data, int bytelen); |
55 | void __raw_readsw(const volatile void __iomem *addr, void *data, int wordlen); | |
56 | void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen); | |
1da177e4 | 57 | |
195bbcac WD |
58 | #if __LINUX_ARM_ARCH__ < 6 |
59 | /* | |
60 | * Half-word accesses are problematic with RiscPC due to limitations of | |
61 | * the bus. Rather than special-case the machine, just let the compiler | |
62 | * generate the access for CPUs prior to ARMv6. | |
63 | */ | |
64 | #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) | |
65 | #define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))) | |
66 | #else | |
67 | /* | |
68 | * When running under a hypervisor, we want to avoid I/O accesses with | |
69 | * writeback addressing modes as these incur a significant performance | |
70 | * overhead (the address generation must be emulated in software). | |
71 | */ | |
84c4d3a6 | 72 | #define __raw_writew __raw_writew |
195bbcac WD |
73 | static inline void __raw_writew(u16 val, volatile void __iomem *addr) |
74 | { | |
75 | asm volatile("strh %1, %0" | |
7629a9f6 | 76 | : "+Q" (*(volatile u16 __force *)addr) |
195bbcac WD |
77 | : "r" (val)); |
78 | } | |
79 | ||
84c4d3a6 | 80 | #define __raw_readw __raw_readw |
195bbcac WD |
81 | static inline u16 __raw_readw(const volatile void __iomem *addr) |
82 | { | |
83 | u16 val; | |
84 | asm volatile("ldrh %1, %0" | |
7629a9f6 | 85 | : "+Q" (*(volatile u16 __force *)addr), |
195bbcac WD |
86 | "=r" (val)); |
87 | return val; | |
88 | } | |
89 | #endif | |
90 | ||
84c4d3a6 | 91 | #define __raw_writeb __raw_writeb |
195bbcac WD |
92 | static inline void __raw_writeb(u8 val, volatile void __iomem *addr) |
93 | { | |
94 | asm volatile("strb %1, %0" | |
95 | : "+Qo" (*(volatile u8 __force *)addr) | |
96 | : "r" (val)); | |
97 | } | |
98 | ||
84c4d3a6 | 99 | #define __raw_writel __raw_writel |
195bbcac WD |
100 | static inline void __raw_writel(u32 val, volatile void __iomem *addr) |
101 | { | |
102 | asm volatile("str %1, %0" | |
103 | : "+Qo" (*(volatile u32 __force *)addr) | |
104 | : "r" (val)); | |
105 | } | |
106 | ||
84c4d3a6 | 107 | #define __raw_readb __raw_readb |
195bbcac WD |
108 | static inline u8 __raw_readb(const volatile void __iomem *addr) |
109 | { | |
110 | u8 val; | |
111 | asm volatile("ldrb %1, %0" | |
112 | : "+Qo" (*(volatile u8 __force *)addr), | |
113 | "=r" (val)); | |
114 | return val; | |
115 | } | |
1da177e4 | 116 | |
84c4d3a6 | 117 | #define __raw_readl __raw_readl |
195bbcac WD |
118 | static inline u32 __raw_readl(const volatile void __iomem *addr) |
119 | { | |
120 | u32 val; | |
121 | asm volatile("ldr %1, %0" | |
122 | : "+Qo" (*(volatile u32 __force *)addr), | |
123 | "=r" (val)); | |
124 | return val; | |
125 | } | |
1da177e4 | 126 | |
67a1901f RK |
127 | /* |
128 | * Architecture ioremap implementation. | |
129 | */ | |
3603ab2b RK |
130 | #define MT_DEVICE 0 |
131 | #define MT_DEVICE_NONSHARED 1 | |
132 | #define MT_DEVICE_CACHED 2 | |
db5b7169 | 133 | #define MT_DEVICE_WC 3 |
3603ab2b | 134 | /* |
db5b7169 | 135 | * types 4 onwards can be found in asm/mach/map.h and are undefined |
3603ab2b RK |
136 | * for ioremap |
137 | */ | |
138 | ||
139 | /* | |
140 | * __arm_ioremap takes CPU physical address. | |
141 | * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page | |
31aa8fd6 RK |
142 | * The _caller variety takes a __builtin_return_address(0) value for |
143 | * /proc/vmalloc to use - and should only be used in non-inline functions. | |
3603ab2b | 144 | */ |
31aa8fd6 RK |
145 | extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long, |
146 | size_t, unsigned int, void *); | |
9b97173e | 147 | extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int, |
31aa8fd6 RK |
148 | void *); |
149 | ||
150 | extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int); | |
9b97173e LA |
151 | extern void __iomem *__arm_ioremap(phys_addr_t, size_t, unsigned int); |
152 | extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached); | |
1622605c | 153 | extern void __iounmap(volatile void __iomem *addr); |
4fe7ef3a RH |
154 | extern void __arm_iounmap(volatile void __iomem *addr); |
155 | ||
9b97173e | 156 | extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, |
4fe7ef3a RH |
157 | unsigned int, void *); |
158 | extern void (*arch_iounmap)(volatile void __iomem *); | |
67a1901f | 159 | |
1da177e4 LT |
160 | /* |
161 | * Bad read/write accesses... | |
162 | */ | |
163 | extern void __readwrite_bug(const char *fn); | |
164 | ||
0560cf5a RK |
165 | /* |
166 | * A typesafe __io() helper | |
167 | */ | |
168 | static inline void __iomem *__typesafe_io(unsigned long addr) | |
169 | { | |
170 | return (void __iomem *)addr; | |
171 | } | |
172 | ||
6f6f6a70 RH |
173 | #define IOMEM(x) ((void __force __iomem *)(x)) |
174 | ||
c1928022 RK |
175 | /* IO barriers */ |
176 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE | |
9f97da78 | 177 | #include <asm/barrier.h> |
c1928022 RK |
178 | #define __iormb() rmb() |
179 | #define __iowmb() wmb() | |
180 | #else | |
181 | #define __iormb() do { } while (0) | |
182 | #define __iowmb() do { } while (0) | |
183 | #endif | |
184 | ||
c2794437 RH |
185 | /* PCI fixed i/o mapping */ |
186 | #define PCI_IO_VIRT_BASE 0xfee00000 | |
dad13e3c | 187 | #define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE) |
c2794437 | 188 | |
1c8c3cf0 TP |
189 | #if defined(CONFIG_PCI) |
190 | void pci_ioremap_set_mem_type(int mem_type); | |
191 | #else | |
192 | static inline void pci_ioremap_set_mem_type(int mem_type) {} | |
193 | #endif | |
194 | ||
c2794437 RH |
195 | extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); |
196 | ||
1da177e4 LT |
197 | /* |
198 | * Now, pick up the machine-defined IO definitions | |
199 | */ | |
c334bc15 | 200 | #ifdef CONFIG_NEED_MACH_IO_H |
a09e64fb | 201 | #include <mach/io.h> |
c2794437 RH |
202 | #elif defined(CONFIG_PCI) |
203 | #define IO_SPACE_LIMIT ((resource_size_t)0xfffff) | |
204 | #define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT)) | |
c334bc15 | 205 | #else |
1ac02d79 | 206 | #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT) |
c334bc15 | 207 | #endif |
1da177e4 | 208 | |
04e1c838 RK |
209 | /* |
210 | * This is the limit of PC card/PCI/ISA IO space, which is by default | |
211 | * 64K if we have PC card, PCI or ISA support. Otherwise, default to | |
212 | * zero to prevent ISA/PCI drivers claiming IO space (and potentially | |
213 | * oopsing.) | |
214 | * | |
215 | * Only set this larger if you really need inb() et.al. to operate over | |
216 | * a larger address space. Note that SOC_COMMON ioremaps each sockets | |
217 | * IO space area, and so inb() et.al. must be defined to operate as per | |
218 | * readb() et.al. on such platforms. | |
219 | */ | |
220 | #ifndef IO_SPACE_LIMIT | |
221 | #if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE) | |
222 | #define IO_SPACE_LIMIT ((resource_size_t)0xffffffff) | |
223 | #elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD) | |
224 | #define IO_SPACE_LIMIT ((resource_size_t)0xffff) | |
225 | #else | |
226 | #define IO_SPACE_LIMIT ((resource_size_t)0) | |
227 | #endif | |
228 | #endif | |
229 | ||
1da177e4 LT |
230 | /* |
231 | * IO port access primitives | |
232 | * ------------------------- | |
233 | * | |
234 | * The ARM doesn't have special IO access instructions; all IO is memory | |
235 | * mapped. Note that these are defined to perform little endian accesses | |
236 | * only. Their primary purpose is to access PCI and ISA peripherals. | |
237 | * | |
238 | * Note that for a big endian machine, this implies that the following | |
c79ebfa8 | 239 | * big endian mode connectivity is in place, as described by numerous |
1da177e4 LT |
240 | * ARM documents: |
241 | * | |
242 | * PCI: D0-D7 D8-D15 D16-D23 D24-D31 | |
243 | * ARM: D24-D31 D16-D23 D8-D15 D0-D7 | |
244 | * | |
245 | * The machine specific io.h include defines __io to translate an "IO" | |
246 | * address to a memory address. | |
247 | * | |
248 | * Note that we prevent GCC re-ordering or caching values in expressions | |
249 | * by introducing sequence points into the in*() definitions. Note that | |
250 | * __raw_* do not guarantee this behaviour. | |
251 | * | |
252 | * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. | |
253 | */ | |
254 | #ifdef __io | |
c1928022 RK |
255 | #define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); }) |
256 | #define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \ | |
257 | cpu_to_le16(v),__io(p)); }) | |
258 | #define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \ | |
259 | cpu_to_le32(v),__io(p)); }) | |
1da177e4 | 260 | |
c1928022 | 261 | #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; }) |
05f9869b | 262 | #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \ |
c1928022 | 263 | __raw_readw(__io(p))); __iormb(); __v; }) |
05f9869b | 264 | #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \ |
c1928022 | 265 | __raw_readl(__io(p))); __iormb(); __v; }) |
1da177e4 LT |
266 | |
267 | #define outsb(p,d,l) __raw_writesb(__io(p),d,l) | |
268 | #define outsw(p,d,l) __raw_writesw(__io(p),d,l) | |
269 | #define outsl(p,d,l) __raw_writesl(__io(p),d,l) | |
270 | ||
271 | #define insb(p,d,l) __raw_readsb(__io(p),d,l) | |
272 | #define insw(p,d,l) __raw_readsw(__io(p),d,l) | |
273 | #define insl(p,d,l) __raw_readsl(__io(p),d,l) | |
274 | #endif | |
275 | ||
1da177e4 LT |
276 | /* |
277 | * String version of IO memory access ops: | |
278 | */ | |
d2f60748 RK |
279 | extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t); |
280 | extern void _memcpy_toio(volatile void __iomem *, const void *, size_t); | |
281 | extern void _memset_io(volatile void __iomem *, int, size_t); | |
1da177e4 LT |
282 | |
283 | #define mmiowb() | |
284 | ||
285 | /* | |
286 | * Memory access primitives | |
287 | * ------------------------ | |
288 | * | |
289 | * These perform PCI memory accesses via an ioremap region. They don't | |
290 | * take an address as such, but a cookie. | |
291 | * | |
292 | * Again, this are defined to perform little endian accesses. See the | |
293 | * IO port primitives for more information. | |
294 | */ | |
5621caac RH |
295 | #ifndef readl |
296 | #define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) | |
b0c1264f | 297 | #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ |
5621caac | 298 | __raw_readw(c)); __r; }) |
b0c1264f | 299 | #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ |
5621caac | 300 | __raw_readl(c)); __r; }) |
e936771a | 301 | |
af06bb9f RK |
302 | #define writeb_relaxed(v,c) __raw_writeb(v,c) |
303 | #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c) | |
304 | #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) | |
e936771a | 305 | |
b92b3612 RK |
306 | #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) |
307 | #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) | |
308 | #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) | |
309 | ||
310 | #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); }) | |
311 | #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) | |
312 | #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) | |
313 | ||
5621caac RH |
314 | #define readsb(p,d,l) __raw_readsb(p,d,l) |
315 | #define readsw(p,d,l) __raw_readsw(p,d,l) | |
316 | #define readsl(p,d,l) __raw_readsl(p,d,l) | |
1da177e4 | 317 | |
5621caac RH |
318 | #define writesb(p,d,l) __raw_writesb(p,d,l) |
319 | #define writesw(p,d,l) __raw_writesw(p,d,l) | |
320 | #define writesl(p,d,l) __raw_writesl(p,d,l) | |
1da177e4 | 321 | |
5621caac RH |
322 | #define memset_io(c,v,l) _memset_io(c,(v),(l)) |
323 | #define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l)) | |
324 | #define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l)) | |
1da177e4 | 325 | |
5621caac | 326 | #endif /* readl */ |
1da177e4 | 327 | |
1da177e4 LT |
328 | /* |
329 | * ioremap and friends. | |
330 | * | |
331 | * ioremap takes a PCI memory address, as specified in | |
395cf969 | 332 | * Documentation/io-mapping.txt. |
9d4ae727 | 333 | * |
1da177e4 | 334 | */ |
21a5365b RH |
335 | #define ioremap(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE) |
336 | #define ioremap_nocache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE) | |
92341c83 | 337 | #define ioremap_cache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_CACHED) |
21a5365b | 338 | #define ioremap_wc(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_WC) |
556269c1 | 339 | #define ioremap_wt(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE) |
21a5365b | 340 | #define iounmap __arm_iounmap |
1da177e4 | 341 | |
09f0551d | 342 | /* |
84c4d3a6 | 343 | * io{read,write}{16,32}be() macros |
09f0551d | 344 | */ |
84c4d3a6 TR |
345 | #define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; }) |
346 | #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; }) | |
09f0551d | 347 | |
84c4d3a6 TR |
348 | #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); }) |
349 | #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); }) | |
09f0551d | 350 | |
84c4d3a6 TR |
351 | #ifndef ioport_map |
352 | #define ioport_map ioport_map | |
09f0551d | 353 | extern void __iomem *ioport_map(unsigned long port, unsigned int nr); |
84c4d3a6 TR |
354 | #endif |
355 | #ifndef ioport_unmap | |
356 | #define ioport_unmap ioport_unmap | |
09f0551d | 357 | extern void ioport_unmap(void __iomem *addr); |
7533fca8 | 358 | #endif |
09f0551d RK |
359 | |
360 | struct pci_dev; | |
361 | ||
84c4d3a6 | 362 | #define pci_iounmap pci_iounmap |
09f0551d RK |
363 | extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); |
364 | ||
84c4d3a6 TR |
365 | /* |
366 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | |
367 | * access | |
368 | */ | |
369 | #define xlate_dev_mem_ptr(p) __va(p) | |
370 | ||
371 | /* | |
372 | * Convert a virtual cached pointer to an uncached pointer | |
373 | */ | |
374 | #define xlate_dev_kmem_ptr(p) p | |
375 | ||
376 | #include <asm-generic/io.h> | |
377 | ||
1da177e4 LT |
378 | /* |
379 | * can the hardware map this into one segment or not, given no other | |
380 | * constraints. | |
381 | */ | |
382 | #define BIOVEC_MERGEABLE(vec1, vec2) \ | |
383 | ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) | |
384 | ||
ffc555be | 385 | struct bio_vec; |
3d1975b5 SS |
386 | extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, |
387 | const struct bio_vec *vec2); | |
388 | #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ | |
389 | (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ | |
390 | (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2))) | |
391 | ||
95ba71f7 | 392 | #ifdef CONFIG_MMU |
51635ad2 | 393 | #define ARCH_HAS_VALID_PHYS_ADDR_RANGE |
7e6735c3 | 394 | extern int valid_phys_addr_range(phys_addr_t addr, size_t size); |
51635ad2 | 395 | extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); |
087aaffc | 396 | extern int devmem_is_allowed(unsigned long pfn); |
95ba71f7 | 397 | #endif |
51635ad2 | 398 | |
1645f20b RK |
399 | /* |
400 | * Register ISA memory and port locations for glibc iopl/inb/outb | |
401 | * emulation. | |
402 | */ | |
403 | extern void register_isa_ports(unsigned int mmio, unsigned int io, | |
404 | unsigned int io_shift); | |
405 | ||
1da177e4 LT |
406 | #endif /* __KERNEL__ */ |
407 | #endif /* __ASM_ARM_IO_H */ |